2011-06-21 00:47:27 +07:00
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/*
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2014-05-06 00:16:08 +07:00
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* Copyright (C) 2011 - 2014 Xilinx
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2011-06-21 00:47:27 +07:00
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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2016-11-15 20:50:38 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2012-11-01 01:24:48 +07:00
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compatible = "xlnx,zynq-7000";
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2011-06-21 00:47:27 +07:00
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2013-11-27 08:04:49 +07:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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2015-11-10 01:51:51 +07:00
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cpu0: cpu@0 {
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2013-11-27 08:04:49 +07:00
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&clkc 3>;
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2014-04-05 06:14:12 +07:00
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clock-latency = <1000>;
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2014-05-03 04:07:32 +07:00
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cpu0-supply = <®ulator_vccpint>;
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2014-02-20 06:14:44 +07:00
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operating-points = <
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/* kHz uV */
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666667 1000000
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333334 1000000
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>;
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2013-11-27 08:04:49 +07:00
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};
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2015-11-10 01:51:51 +07:00
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cpu1: cpu@1 {
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2013-11-27 08:04:49 +07:00
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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clocks = <&clkc 3>;
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};
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};
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2016-11-15 21:02:18 +07:00
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pmu@f8891000 {
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2013-03-20 19:37:01 +07:00
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 5 4>, <0 6 4>;
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interrupt-parent = <&intc>;
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2016-11-16 15:29:57 +07:00
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reg = <0xf8891000 0x1000>,
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<0xf8893000 0x1000>;
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2013-03-20 19:37:01 +07:00
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};
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2016-11-15 21:02:18 +07:00
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regulator_vccpint: fixedregulator {
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2014-05-03 04:07:32 +07:00
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compatible = "regulator-fixed";
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regulator-name = "VCCPINT";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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2015-02-12 16:59:17 +07:00
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amba: amba {
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2011-06-21 00:47:27 +07:00
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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2012-11-01 01:24:48 +07:00
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interrupt-parent = <&intc>;
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2011-06-21 00:47:27 +07:00
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ranges;
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2014-09-24 20:28:59 +07:00
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adc: adc@f8007100 {
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2014-06-05 23:05:23 +07:00
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compatible = "xlnx,zynq-xadc-1.00.a";
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reg = <0xf8007100 0x20>;
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interrupts = <0 7 4>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 12>;
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2014-07-23 20:03:03 +07:00
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};
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can0: can@e0008000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 19>, <&clkc 36>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0008000 0x1000>;
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interrupts = <0 28 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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can1: can@e0009000 {
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compatible = "xlnx,zynq-can-1.0";
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status = "disabled";
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clocks = <&clkc 20>, <&clkc 37>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0009000 0x1000>;
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interrupts = <0 51 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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2014-07-11 01:53:38 +07:00
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gpio0: gpio@e000a000 {
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compatible = "xlnx,zynq-gpio-1.0";
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#gpio-cells = <2>;
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clocks = <&clkc 42>;
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gpio-controller;
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2015-10-23 23:25:31 +07:00
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interrupt-controller;
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#interrupt-cells = <2>;
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2014-07-11 01:53:38 +07:00
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interrupt-parent = <&intc>;
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interrupts = <0 20 4>;
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reg = <0xe000a000 0x1000>;
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2014-06-05 23:05:23 +07:00
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};
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2014-05-06 00:16:08 +07:00
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i2c0: i2c@e0004000 {
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2014-04-05 04:27:56 +07:00
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 38>;
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interrupt-parent = <&intc>;
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interrupts = <0 25 4>;
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reg = <0xe0004000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2014-05-06 00:16:08 +07:00
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i2c1: i2c@e0005000 {
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2014-04-05 04:27:56 +07:00
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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clocks = <&clkc 39>;
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interrupt-parent = <&intc>;
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interrupts = <0 48 4>;
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reg = <0xe0005000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2011-06-21 00:47:27 +07:00
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intc: interrupt-controller@f8f01000 {
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2012-10-18 07:46:49 +07:00
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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2011-06-21 00:47:27 +07:00
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interrupt-controller;
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2012-10-18 07:46:49 +07:00
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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2011-06-21 00:47:27 +07:00
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};
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2014-09-24 20:16:01 +07:00
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L2: cache-controller@f8f02000 {
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2012-10-24 05:34:22 +07:00
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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2015-07-18 09:23:55 +07:00
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interrupts = <0 2 4>;
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2013-08-01 06:24:59 +07:00
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arm,data-latency = <3 2 2>;
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arm,tag-latency = <2 2 2>;
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2012-10-24 05:34:22 +07:00
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cache-unified;
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cache-level = <2>;
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};
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2014-09-24 20:53:39 +07:00
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mc: memory-controller@f8006000 {
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2014-09-03 04:19:08 +07:00
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compatible = "xlnx,zynq-ddrc-a05";
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reg = <0xf8006000 0x1000>;
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2014-10-20 20:15:47 +07:00
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};
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2014-09-03 04:19:08 +07:00
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2014-05-06 00:16:08 +07:00
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uart0: serial@e0000000 {
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2014-04-05 07:23:45 +07:00
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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2013-06-13 23:37:16 +07:00
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status = "disabled";
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2013-05-14 00:46:38 +07:00
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clocks = <&clkc 23>, <&clkc 40>;
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2014-04-05 07:23:45 +07:00
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clock-names = "uart_clk", "pclk";
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2011-06-21 00:47:27 +07:00
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reg = <0xE0000000 0x1000>;
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2012-10-18 07:46:49 +07:00
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interrupts = <0 27 4>;
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2011-06-21 00:47:27 +07:00
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};
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2012-11-01 02:45:17 +07:00
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2014-05-06 00:16:08 +07:00
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uart1: serial@e0001000 {
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2014-04-05 07:23:45 +07:00
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compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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2013-06-13 23:37:16 +07:00
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status = "disabled";
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2013-05-14 00:46:38 +07:00
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clocks = <&clkc 24>, <&clkc 41>;
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2014-04-05 07:23:45 +07:00
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clock-names = "uart_clk", "pclk";
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2012-11-01 02:45:17 +07:00
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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};
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2012-11-09 01:04:26 +07:00
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2014-07-25 18:12:31 +07:00
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spi0: spi@e0006000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0006000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 26 4>;
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clocks = <&clkc 25>, <&clkc 34>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@e0007000 {
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compatible = "xlnx,zynq-spi-r1p6";
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reg = <0xe0007000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 49 4>;
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clocks = <&clkc 26>, <&clkc 35>;
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clock-names = "ref_clk", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2013-12-12 00:29:49 +07:00
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gem0: ethernet@e000b000 {
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2015-05-28 03:00:01 +07:00
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compatible = "cdns,zynq-gem", "cdns,gem";
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2014-09-16 22:08:38 +07:00
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reg = <0xe000b000 0x1000>;
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2013-12-12 00:29:49 +07:00
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status = "disabled";
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interrupts = <0 22 4>;
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clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
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clock-names = "pclk", "hclk", "tx_clk";
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2014-08-20 22:56:58 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-12-12 00:29:49 +07:00
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};
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gem1: ethernet@e000c000 {
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2015-05-28 03:00:01 +07:00
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compatible = "cdns,zynq-gem", "cdns,gem";
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2014-09-16 22:08:38 +07:00
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reg = <0xe000c000 0x1000>;
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2013-12-12 00:29:49 +07:00
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status = "disabled";
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interrupts = <0 45 4>;
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clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
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clock-names = "pclk", "hclk", "tx_clk";
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2014-08-20 22:56:58 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-12-12 00:29:49 +07:00
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};
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2014-05-06 00:16:08 +07:00
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sdhci0: sdhci@e0100000 {
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2013-12-03 01:02:37 +07:00
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&intc>;
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interrupts = <0 24 4>;
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reg = <0xe0100000 0x1000>;
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2014-08-21 17:45:05 +07:00
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};
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2013-12-03 01:02:37 +07:00
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2014-05-06 00:16:08 +07:00
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sdhci1: sdhci@e0101000 {
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2013-12-03 01:02:37 +07:00
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 22>, <&clkc 33>;
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interrupt-parent = <&intc>;
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interrupts = <0 47 4>;
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reg = <0xe0101000 0x1000>;
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2014-08-21 17:45:05 +07:00
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};
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2013-12-03 01:02:37 +07:00
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2012-11-09 01:04:26 +07:00
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slcr: slcr@f8000000 {
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2013-11-18 22:48:19 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
|
2015-11-05 15:46:06 +07:00
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compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
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2012-11-09 01:04:26 +07:00
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reg = <0xF8000000 0x1000>;
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2013-11-18 22:48:19 +07:00
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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fclk-enable = <0>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
|
2012-11-09 01:04:26 +07:00
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};
|
2015-01-09 22:43:50 +07:00
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2015-07-31 08:13:55 +07:00
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rstc: rstc@200 {
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compatible = "xlnx,zynq-reset";
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reg = <0x200 0x48>;
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#reset-cells = <1>;
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syscon = <&slcr>;
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};
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2015-01-09 22:43:50 +07:00
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,pinctrl-zynq";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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};
|
2012-11-09 01:04:26 +07:00
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};
|
2012-11-01 02:56:14 +07:00
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|
2014-07-25 06:00:15 +07:00
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dmac_s: dmac@f8003000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xf8003000 0x1000>;
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interrupt-parent = <&intc>;
|
2014-08-21 16:27:05 +07:00
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interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
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"dma4", "dma5", "dma6", "dma7";
|
2014-07-25 06:00:15 +07:00
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interrupts = <0 13 4>,
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<0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>,
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<0 40 4>, <0 41 4>,
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|
<0 42 4>, <0 43 4>;
|
|
|
|
#dma-cells = <1>;
|
|
|
|
#dma-channels = <8>;
|
|
|
|
#dma-requests = <4>;
|
|
|
|
clocks = <&clkc 27>;
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
};
|
|
|
|
|
2013-07-31 14:19:59 +07:00
|
|
|
devcfg: devcfg@f8007000 {
|
|
|
|
compatible = "xlnx,zynq-devcfg-1.0";
|
|
|
|
reg = <0xf8007000 0x100>;
|
2015-10-17 05:42:29 +07:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <0 8 4>;
|
|
|
|
clocks = <&clkc 12>;
|
|
|
|
clock-names = "ref_clk";
|
|
|
|
syscon = <&slcr>;
|
2014-08-21 17:45:05 +07:00
|
|
|
};
|
2013-07-31 14:19:59 +07:00
|
|
|
|
2013-09-19 01:48:38 +07:00
|
|
|
global_timer: timer@f8f00200 {
|
|
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
|
|
reg = <0xf8f00200 0x20>;
|
|
|
|
interrupts = <1 11 0x301>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
clocks = <&clkc 4>;
|
|
|
|
};
|
|
|
|
|
2014-05-06 00:16:08 +07:00
|
|
|
ttc0: timer@f8001000 {
|
2013-03-20 16:15:28 +07:00
|
|
|
interrupt-parent = <&intc>;
|
2014-05-06 00:16:08 +07:00
|
|
|
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
|
2013-03-20 16:15:28 +07:00
|
|
|
compatible = "cdns,ttc";
|
2013-05-14 00:46:38 +07:00
|
|
|
clocks = <&clkc 6>;
|
2012-11-01 02:56:14 +07:00
|
|
|
reg = <0xF8001000 0x1000>;
|
|
|
|
};
|
|
|
|
|
2014-05-06 00:16:08 +07:00
|
|
|
ttc1: timer@f8002000 {
|
2013-03-20 16:15:28 +07:00
|
|
|
interrupt-parent = <&intc>;
|
2014-05-06 00:16:08 +07:00
|
|
|
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
|
2013-03-20 16:15:28 +07:00
|
|
|
compatible = "cdns,ttc";
|
2013-05-14 00:46:38 +07:00
|
|
|
clocks = <&clkc 6>;
|
2012-11-01 02:56:14 +07:00
|
|
|
reg = <0xF8002000 0x1000>;
|
|
|
|
};
|
2014-05-06 00:16:08 +07:00
|
|
|
|
|
|
|
scutimer: timer@f8f00600 {
|
2013-03-27 19:36:39 +07:00
|
|
|
interrupt-parent = <&intc>;
|
2014-05-06 00:16:08 +07:00
|
|
|
interrupts = <1 13 0x301>;
|
2013-03-27 19:36:39 +07:00
|
|
|
compatible = "arm,cortex-a9-twd-timer";
|
2014-05-06 00:16:08 +07:00
|
|
|
reg = <0xf8f00600 0x20>;
|
2013-05-14 00:46:38 +07:00
|
|
|
clocks = <&clkc 4>;
|
2014-08-21 17:45:05 +07:00
|
|
|
};
|
2014-10-02 20:09:15 +07:00
|
|
|
|
2014-12-02 23:07:11 +07:00
|
|
|
usb0: usb@e0002000 {
|
|
|
|
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&clkc 28>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <0 21 4>;
|
|
|
|
reg = <0xe0002000 0x1000>;
|
|
|
|
phy_type = "ulpi";
|
|
|
|
};
|
|
|
|
|
|
|
|
usb1: usb@e0003000 {
|
|
|
|
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&clkc 29>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <0 44 4>;
|
|
|
|
reg = <0xe0003000 0x1000>;
|
|
|
|
phy_type = "ulpi";
|
|
|
|
};
|
|
|
|
|
2014-10-02 20:09:15 +07:00
|
|
|
watchdog0: watchdog@f8005000 {
|
|
|
|
clocks = <&clkc 45>;
|
2015-01-15 19:45:08 +07:00
|
|
|
compatible = "cdns,wdt-r1p2";
|
2014-10-02 20:09:15 +07:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <0 9 1>;
|
|
|
|
reg = <0xf8005000 0x1000>;
|
|
|
|
timeout-sec = <10>;
|
|
|
|
};
|
2011-06-21 00:47:27 +07:00
|
|
|
};
|
|
|
|
};
|