2019-06-04 15:11:33 +07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2005-04-17 05:20:36 +07:00
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/*
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2010-08-09 02:58:20 +07:00
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* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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2005-04-17 05:20:36 +07:00
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*
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2006-05-23 16:50:56 +07:00
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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2005-04-17 05:20:36 +07:00
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*
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2006-05-23 16:50:56 +07:00
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* Changelog:
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* See git changelog.
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2005-04-17 05:20:36 +07:00
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*/
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2017-08-04 22:29:10 +07:00
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#ifndef __LINUX_MTD_RAWNAND_H
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#define __LINUX_MTD_RAWNAND_H
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2005-04-17 05:20:36 +07:00
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#include <linux/mtd/mtd.h>
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2009-09-21 04:28:14 +07:00
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#include <linux/mtd/flashchip.h>
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2009-09-21 04:28:04 +07:00
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#include <linux/mtd/bbm.h>
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2018-09-07 05:38:51 +07:00
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#include <linux/mtd/jedec.h>
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2018-10-25 20:21:08 +07:00
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#include <linux/mtd/nand.h>
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2018-09-07 05:38:50 +07:00
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#include <linux/mtd/onfi.h>
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2018-11-20 17:57:20 +07:00
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#include <linux/mutex.h>
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2018-07-05 17:27:29 +07:00
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#include <linux/of.h>
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2018-03-19 20:47:28 +07:00
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#include <linux/types.h>
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2005-04-17 05:20:36 +07:00
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2018-09-06 19:05:14 +07:00
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struct nand_chip;
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2015-01-23 15:22:27 +07:00
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2005-04-17 05:20:36 +07:00
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/* The maximum number of NAND chips in an array */
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#define NAND_MAX_CHIPS 8
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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2006-05-24 04:25:53 +07:00
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*
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* These are bits which can be or'ed to set/clear multiple
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* bits in one go.
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*/
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2005-04-17 05:20:36 +07:00
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/* Select the chip by setting nCE to low */
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2006-05-24 04:25:53 +07:00
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#define NAND_NCE 0x01
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2005-04-17 05:20:36 +07:00
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/* Select the command latch by setting CLE to high */
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2006-05-24 04:25:53 +07:00
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#define NAND_CLE 0x02
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2005-04-17 05:20:36 +07:00
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/* Select the address latch by setting ALE to high */
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2006-05-24 04:25:53 +07:00
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#define NAND_ALE 0x04
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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
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#define NAND_CTRL_CHANGE 0x80
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2005-04-17 05:20:36 +07:00
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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2006-06-21 01:05:05 +07:00
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#define NAND_CMD_RNDOUT 5
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2005-04-17 05:20:36 +07:00
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_SEQIN 0x80
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2006-06-21 01:05:05 +07:00
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#define NAND_CMD_RNDIN 0x85
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2005-04-17 05:20:36 +07:00
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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2010-08-30 23:32:14 +07:00
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#define NAND_CMD_PARAM 0xec
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2012-09-13 13:57:52 +07:00
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#define NAND_CMD_GET_FEATURES 0xee
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#define NAND_CMD_SET_FEATURES 0xef
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2005-04-17 05:20:36 +07:00
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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2006-06-21 01:05:05 +07:00
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#define NAND_CMD_RNDOUTSTART 0xE0
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2005-04-17 05:20:36 +07:00
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#define NAND_CMD_CACHEDPROG 0x15
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2006-05-24 04:25:53 +07:00
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#define NAND_CMD_NONE -1
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2005-04-17 05:20:36 +07:00
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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2017-03-16 15:35:58 +07:00
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#define NAND_DATA_IFACE_CHECK_ONLY -1
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2005-11-07 18:15:31 +07:00
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/*
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2005-04-17 05:20:36 +07:00
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* Constants for ECC_MODES
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*/
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2006-05-23 17:00:46 +07:00
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typedef enum {
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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2009-09-19 02:51:47 +07:00
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NAND_ECC_HW_OOB_FIRST,
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2017-04-29 16:06:43 +07:00
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NAND_ECC_ON_DIE,
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2006-05-23 17:00:46 +07:00
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} nand_ecc_modes_t;
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2005-04-17 05:20:36 +07:00
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2016-03-23 17:19:00 +07:00
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enum nand_ecc_algo {
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NAND_ECC_UNKNOWN,
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NAND_ECC_HAMMING,
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NAND_ECC_BCH,
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2018-06-25 04:27:22 +07:00
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NAND_ECC_RS,
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2016-03-23 17:19:00 +07:00
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};
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2005-04-17 05:20:36 +07:00
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/*
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* Constants for Hardware ECC
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2005-01-24 10:07:46 +07:00
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*/
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2005-04-17 05:20:36 +07:00
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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2011-06-24 04:12:08 +07:00
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/* Enable Hardware ECC before syndrome is read back from flash */
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2005-04-17 05:20:36 +07:00
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#define NAND_ECC_READSYN 2
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2015-12-31 02:32:04 +07:00
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/*
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* Enable generic NAND 'page erased' check. This check is only done when
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* ecc.correct() returns -EBADMSG.
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* Set this flag if your implementation does not fix bitflips in erased
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* pages and you want to rely on the default implementation.
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*/
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#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
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2016-06-08 22:04:22 +07:00
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#define NAND_ECC_MAXIMIZE BIT(1)
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2015-12-31 02:32:04 +07:00
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2018-09-04 21:23:28 +07:00
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/*
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* When using software implementation of Hamming, we can specify which byte
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* ordering should be used.
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*/
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#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
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2010-10-05 17:41:01 +07:00
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/*
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* Option constants for bizarre disfunctionality and real
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* features.
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*/
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2011-06-24 04:12:08 +07:00
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/* Buswidth is 16 bit */
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2005-04-17 05:20:36 +07:00
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#define NAND_BUSWIDTH_16 0x00000002
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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2013-03-13 23:51:31 +07:00
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/*
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* Chip requires ready check on read (for auto-incremented sequential read).
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* True only for small page devices; large page devices do not support
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* autoincrement.
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*/
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#define NAND_NEED_READRDY 0x00000100
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2006-09-28 20:38:36 +07:00
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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2010-02-23 01:39:40 +07:00
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/* Device is one of 'new' xD cards that expose fake nand command set */
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#define NAND_BROKEN_XD 0x00000400
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/* Device behaves just like nand, but is readonly */
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#define NAND_ROM 0x00000800
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2012-08-14 04:35:30 +07:00
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/* Device supports subpage reads */
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#define NAND_SUBPAGE_READ 0x00001000
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2015-12-02 18:01:05 +07:00
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/*
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* Some MLC NANDs need data scrambling to limit bitflips caused by repeated
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* patterns.
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*/
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#define NAND_NEED_SCRAMBLING 0x00002000
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2017-09-13 09:05:50 +07:00
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/* Device needs 3rd row address cycle */
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#define NAND_ROW_ADDR_3 0x00004000
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2005-04-17 05:20:36 +07:00
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/* Options valid for Samsung large page devices */
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2013-03-04 19:56:18 +07:00
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#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
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2005-04-17 05:20:36 +07:00
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/* Macros to identify the above */
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2012-08-14 04:35:30 +07:00
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#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
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2005-04-17 05:20:36 +07:00
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2019-04-17 19:36:34 +07:00
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/*
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* There are different places where the manufacturer stores the factory bad
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* block markers.
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*
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* Position within the block: Each of these pages needs to be checked for a
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* bad block marking pattern.
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*/
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2019-04-17 19:36:36 +07:00
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#define NAND_BBM_FIRSTPAGE 0x01000000
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2019-04-17 19:36:34 +07:00
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#define NAND_BBM_SECONDPAGE 0x02000000
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#define NAND_BBM_LASTPAGE 0x04000000
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/* Position within the OOB data of the page */
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#define NAND_BBM_POS_SMALL 5
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#define NAND_BBM_POS_LARGE 0
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2005-04-17 05:20:36 +07:00
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/* Non chip related options */
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2005-02-09 19:20:00 +07:00
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/* This option skips the bbt scan during initialization. */
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2011-06-01 06:31:26 +07:00
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#define NAND_SKIP_BBTSCAN 0x00010000
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2009-11-03 01:12:33 +07:00
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/* Chip may not exist, so silence any errors in scan */
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2011-06-01 06:31:26 +07:00
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#define NAND_SCAN_SILENT_NODEV 0x00040000
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2012-11-06 17:51:44 +07:00
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/*
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* Autodetect nand buswidth with readid/onfi.
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* This suppose the driver will configure the hardware in 8 bits mode
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* when calling nand_scan_ident, and update its configuration
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* before calling nand_scan_tail.
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*/
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#define NAND_BUSWIDTH_AUTO 0x00080000
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2015-06-27 07:43:58 +07:00
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/*
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* This option could be defined by controller drivers to protect against
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* kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
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*/
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#define NAND_USE_BOUNCE_BUFFER 0x00100000
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2009-11-03 01:12:33 +07:00
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2016-10-01 15:24:03 +07:00
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/*
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2018-09-07 05:38:36 +07:00
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* In case your controller is implementing ->legacy.cmd_ctrl() and is relying
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* on the default ->cmdfunc() implementation, you may want to let the core
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* handle the tCCS delay which is required when a column change (RNDIN or
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* RNDOUT) is requested.
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2016-10-01 15:24:03 +07:00
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* If your controller already takes care of this delay, you don't need to set
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* this flag.
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*/
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#define NAND_WAIT_TCCS 0x00200000
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2018-06-25 04:27:23 +07:00
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/*
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* Whether the NAND chip is a boot medium. Drivers might use this information
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* to select ECC algorithms supported by the boot ROM or similar restrictions.
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*/
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#define NAND_IS_BOOT_MEDIUM 0x00400000
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2018-11-11 14:55:24 +07:00
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/*
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* Do not try to tweak the timings at runtime. This is needed when the
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* controller initializes the timings on itself or when it relies on
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* configuration done by the bootloader.
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*/
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#define NAND_KEEP_TIMINGS 0x00800000
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2006-09-28 20:38:36 +07:00
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/* Cell info constants */
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#define NAND_CI_CHIPNR_MSK 0x03
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#define NAND_CI_CELLTYPE_MSK 0x0C
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2013-09-25 13:58:11 +07:00
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#define NAND_CI_CELLTYPE_SHIFT 2
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2005-04-17 05:20:36 +07:00
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2018-03-19 20:47:26 +07:00
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/**
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* struct nand_parameters - NAND generic parameters from the parameter page
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* @model: Model name
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* @supports_set_get_features: The NAND chip supports setting/getting features
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2018-03-19 20:47:28 +07:00
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* @set_feature_list: Bitmap of features that can be set
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* @get_feature_list: Bitmap of features that can be get
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2018-03-19 20:47:27 +07:00
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* @onfi: ONFI specific parameters
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2018-03-19 20:47:26 +07:00
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*/
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struct nand_parameters {
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2018-03-19 20:47:27 +07:00
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/* Generic parameters */
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2018-07-25 20:31:51 +07:00
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const char *model;
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2018-03-19 20:47:26 +07:00
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bool supports_set_get_features;
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2018-03-19 20:47:28 +07:00
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DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
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DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
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2018-03-19 20:47:27 +07:00
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/* ONFI parameters */
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2018-07-25 20:31:52 +07:00
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struct onfi_params *onfi;
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2018-03-19 20:47:26 +07:00
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};
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2017-06-30 00:08:30 +07:00
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/* The maximum expected count of bytes in the NAND ID sequence */
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#define NAND_MAX_ID_LEN 8
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2016-05-25 00:20:05 +07:00
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/**
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* struct nand_id - NAND id structure
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2017-06-30 00:08:30 +07:00
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* @data: buffer containing the id bytes.
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2016-05-25 00:20:05 +07:00
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* @len: ID length.
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*/
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struct nand_id {
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2017-06-30 00:08:30 +07:00
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u8 data[NAND_MAX_ID_LEN];
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2016-05-25 00:20:05 +07:00
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int len;
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};
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2017-06-07 18:52:10 +07:00
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/**
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* struct nand_ecc_step_info - ECC step information of ECC engine
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* @stepsize: data bytes per ECC step
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* @strengths: array of supported strengths
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* @nstrengths: number of supported strengths
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*/
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struct nand_ecc_step_info {
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int stepsize;
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const int *strengths;
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int nstrengths;
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};
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/**
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* struct nand_ecc_caps - capability of ECC engine
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* @stepinfos: array of ECC step information
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* @nstepinfos: number of ECC step information
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* @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
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*/
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struct nand_ecc_caps {
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const struct nand_ecc_step_info *stepinfos;
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int nstepinfos;
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int (*calc_ecc_bytes)(int step_size, int strength);
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};
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mtd: nand: add a shorthand to generate nand_ecc_caps structure
struct nand_ecc_caps was designed as flexible as possible to support
multiple stepsizes (like sunxi_nand.c).
So, we need to write multiple arrays even for the simplest case.
I guess many controllers support a single stepsize, so here is a
shorthand macro for the case.
It allows to describe like ...
NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15);
... instead of
static const int denali_pci_ecc_strengths[] = {8, 15};
static const struct nand_ecc_step_info denali_pci_ecc_stepinfo = {
.stepsize = 512,
.strengths = denali_pci_ecc_strengths,
.nstrengths = ARRAY_SIZE(denali_pci_ecc_strengths),
};
static const struct nand_ecc_caps denali_pci_ecc_caps = {
.stepinfos = &denali_pci_ecc_stepinfo,
.nstepinfos = 1,
.calc_ecc_bytes = denali_calc_ecc_bytes,
};
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-06-07 18:52:11 +07:00
|
|
|
/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
|
|
|
|
#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
|
|
|
|
static const int __name##_strengths[] = { __VA_ARGS__ }; \
|
|
|
|
static const struct nand_ecc_step_info __name##_stepinfo = { \
|
|
|
|
.stepsize = __step, \
|
|
|
|
.strengths = __name##_strengths, \
|
|
|
|
.nstrengths = ARRAY_SIZE(__name##_strengths), \
|
|
|
|
}; \
|
|
|
|
static const struct nand_ecc_caps __name = { \
|
|
|
|
.stepinfos = &__name##_stepinfo, \
|
|
|
|
.nstepinfos = 1, \
|
|
|
|
.calc_ecc_bytes = __calc, \
|
|
|
|
}
|
|
|
|
|
2006-05-23 17:00:46 +07:00
|
|
|
/**
|
2011-06-24 04:12:08 +07:00
|
|
|
* struct nand_ecc_ctrl - Control structure for ECC
|
|
|
|
* @mode: ECC mode
|
2016-03-23 17:19:00 +07:00
|
|
|
* @algo: ECC algorithm
|
2011-06-24 04:12:08 +07:00
|
|
|
* @steps: number of ECC steps per page
|
|
|
|
* @size: data bytes per ECC step
|
|
|
|
* @bytes: ECC bytes per step
|
2012-03-12 04:21:10 +07:00
|
|
|
* @strength: max number of correctible bits per ECC step
|
2011-06-24 04:12:08 +07:00
|
|
|
* @total: total number of ECC bytes per page
|
|
|
|
* @prepad: padding information for syndrome based ECC generators
|
|
|
|
* @postpad: padding information for syndrome based ECC generators
|
2015-12-31 02:32:04 +07:00
|
|
|
* @options: ECC specific options (see NAND_ECC_XXX flags defined above)
|
2011-06-24 04:12:08 +07:00
|
|
|
* @priv: pointer to private ECC control data
|
2017-12-05 15:47:16 +07:00
|
|
|
* @calc_buf: buffer for calculated ECC, size is oobsize.
|
|
|
|
* @code_buf: buffer for ECC read from flash, size is oobsize.
|
2011-06-24 04:12:08 +07:00
|
|
|
* @hwctl: function to control hardware ECC generator. Must only
|
2006-05-23 17:00:46 +07:00
|
|
|
* be provided if an hardware ECC is available
|
2011-06-24 04:12:08 +07:00
|
|
|
* @calculate: function for ECC calculation or readback from ECC hardware
|
2015-12-31 02:32:03 +07:00
|
|
|
* @correct: function for ECC correction, matching to ECC generator (sw/hw).
|
|
|
|
* Should return a positive number representing the number of
|
|
|
|
* corrected bitflips, -EBADMSG if the number of bitflips exceed
|
|
|
|
* ECC strength, or any other error code if the error is not
|
|
|
|
* directly related to correction.
|
|
|
|
* If -EBADMSG is returned the input buffers should be left
|
|
|
|
* untouched.
|
2014-10-20 15:46:14 +07:00
|
|
|
* @read_page_raw: function to read a raw page without ECC. This function
|
|
|
|
* should hide the specific layout used by the ECC
|
|
|
|
* controller and always return contiguous in-band and
|
|
|
|
* out-of-band data even if they're not stored
|
|
|
|
* contiguously on the NAND chip (e.g.
|
|
|
|
* NAND_ECC_HW_SYNDROME interleaves in-band and
|
|
|
|
* out-of-band data).
|
|
|
|
* @write_page_raw: function to write a raw page without ECC. This function
|
|
|
|
* should hide the specific layout used by the ECC
|
|
|
|
* controller and consider the passed data as contiguous
|
|
|
|
* in-band and out-of-band data. ECC controller is
|
|
|
|
* responsible for doing the appropriate transformations
|
|
|
|
* to adapt to its specific layout (e.g.
|
|
|
|
* NAND_ECC_HW_SYNDROME interleaves in-band and
|
|
|
|
* out-of-band data).
|
2011-06-24 04:12:08 +07:00
|
|
|
* @read_page: function to read a page according to the ECC generator
|
2012-09-11 22:59:03 +07:00
|
|
|
* requirements; returns maximum number of bitflips corrected in
|
2017-03-30 13:45:47 +07:00
|
|
|
* any single ECC step, -EIO hw error
|
2012-09-11 22:59:03 +07:00
|
|
|
* @read_subpage: function to read parts of the page covered by ECC;
|
|
|
|
* returns same as read_page()
|
2013-03-15 19:25:53 +07:00
|
|
|
* @write_subpage: function to write parts of the page covered by ECC.
|
2011-06-24 04:12:08 +07:00
|
|
|
* @write_page: function to write a page according to the ECC generator
|
2010-10-05 17:41:01 +07:00
|
|
|
* requirements.
|
2011-08-31 08:45:37 +07:00
|
|
|
* @write_oob_raw: function to write chip OOB data without ECC
|
2011-08-31 08:45:38 +07:00
|
|
|
* @read_oob_raw: function to read chip OOB data without ECC
|
2006-06-29 11:48:27 +07:00
|
|
|
* @read_oob: function to read chip OOB data
|
|
|
|
* @write_oob: function to write chip OOB data
|
2006-05-23 17:00:46 +07:00
|
|
|
*/
|
|
|
|
struct nand_ecc_ctrl {
|
2010-10-08 02:48:27 +07:00
|
|
|
nand_ecc_modes_t mode;
|
2016-03-23 17:19:00 +07:00
|
|
|
enum nand_ecc_algo algo;
|
2010-10-08 02:48:27 +07:00
|
|
|
int steps;
|
|
|
|
int size;
|
|
|
|
int bytes;
|
|
|
|
int total;
|
2012-03-12 04:21:10 +07:00
|
|
|
int strength;
|
2010-10-08 02:48:27 +07:00
|
|
|
int prepad;
|
|
|
|
int postpad;
|
2015-12-31 02:32:04 +07:00
|
|
|
unsigned int options;
|
2011-03-11 17:05:33 +07:00
|
|
|
void *priv;
|
2017-12-05 15:47:16 +07:00
|
|
|
u8 *calc_buf;
|
|
|
|
u8 *code_buf;
|
2018-09-06 19:05:17 +07:00
|
|
|
void (*hwctl)(struct nand_chip *chip, int mode);
|
2018-09-06 19:05:18 +07:00
|
|
|
int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
|
|
|
|
uint8_t *ecc_code);
|
2018-09-06 19:05:19 +07:00
|
|
|
int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
|
|
|
|
uint8_t *calc_ecc);
|
2018-09-06 19:05:20 +07:00
|
|
|
int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
|
|
|
|
int oob_required, int page);
|
2018-09-06 19:05:21 +07:00
|
|
|
int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
|
|
|
|
int oob_required, int page);
|
2018-09-06 19:05:20 +07:00
|
|
|
int (*read_page)(struct nand_chip *chip, uint8_t *buf,
|
|
|
|
int oob_required, int page);
|
|
|
|
int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
|
|
|
|
uint32_t len, uint8_t *buf, int page);
|
2018-09-06 19:05:21 +07:00
|
|
|
int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
|
|
|
|
uint32_t data_len, const uint8_t *data_buf,
|
|
|
|
int oob_required, int page);
|
|
|
|
int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
|
|
|
|
int oob_required, int page);
|
|
|
|
int (*write_oob_raw)(struct nand_chip *chip, int page);
|
2018-09-06 19:05:20 +07:00
|
|
|
int (*read_oob_raw)(struct nand_chip *chip, int page);
|
|
|
|
int (*read_oob)(struct nand_chip *chip, int page);
|
2018-09-06 19:05:21 +07:00
|
|
|
int (*write_oob)(struct nand_chip *chip, int page);
|
2006-05-26 23:52:08 +07:00
|
|
|
};
|
|
|
|
|
2016-09-15 15:32:46 +07:00
|
|
|
/**
|
|
|
|
* struct nand_sdr_timings - SDR NAND chip timings
|
|
|
|
*
|
|
|
|
* This struct defines the timing requirements of a SDR NAND chip.
|
|
|
|
* These information can be found in every NAND datasheets and the timings
|
|
|
|
* meaning are described in the ONFI specifications:
|
|
|
|
* www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
|
|
|
|
* Parameters)
|
|
|
|
*
|
|
|
|
* All these timings are expressed in picoseconds.
|
|
|
|
*
|
2016-10-01 15:24:02 +07:00
|
|
|
* @tBERS_max: Block erase time
|
|
|
|
* @tCCS_min: Change column setup time
|
|
|
|
* @tPROG_max: Page program time
|
|
|
|
* @tR_max: Page read time
|
2016-09-15 15:32:46 +07:00
|
|
|
* @tALH_min: ALE hold time
|
|
|
|
* @tADL_min: ALE to data loading time
|
|
|
|
* @tALS_min: ALE setup time
|
|
|
|
* @tAR_min: ALE to RE# delay
|
|
|
|
* @tCEA_max: CE# access time
|
2016-11-22 09:32:08 +07:00
|
|
|
* @tCEH_min: CE# high hold time
|
2016-09-15 15:32:46 +07:00
|
|
|
* @tCH_min: CE# hold time
|
|
|
|
* @tCHZ_max: CE# high to output hi-Z
|
|
|
|
* @tCLH_min: CLE hold time
|
|
|
|
* @tCLR_min: CLE to RE# delay
|
|
|
|
* @tCLS_min: CLE setup time
|
|
|
|
* @tCOH_min: CE# high to output hold
|
|
|
|
* @tCS_min: CE# setup time
|
|
|
|
* @tDH_min: Data hold time
|
|
|
|
* @tDS_min: Data setup time
|
|
|
|
* @tFEAT_max: Busy time for Set Features and Get Features
|
|
|
|
* @tIR_min: Output hi-Z to RE# low
|
|
|
|
* @tITC_max: Interface and Timing Mode Change time
|
|
|
|
* @tRC_min: RE# cycle time
|
|
|
|
* @tREA_max: RE# access time
|
|
|
|
* @tREH_min: RE# high hold time
|
|
|
|
* @tRHOH_min: RE# high to output hold
|
|
|
|
* @tRHW_min: RE# high to WE# low
|
|
|
|
* @tRHZ_max: RE# high to output hi-Z
|
|
|
|
* @tRLOH_min: RE# low to output hold
|
|
|
|
* @tRP_min: RE# pulse width
|
|
|
|
* @tRR_min: Ready to RE# low (data only)
|
|
|
|
* @tRST_max: Device reset time, measured from the falling edge of R/B# to the
|
|
|
|
* rising edge of R/B#.
|
|
|
|
* @tWB_max: WE# high to SR[6] low
|
|
|
|
* @tWC_min: WE# cycle time
|
|
|
|
* @tWH_min: WE# high hold time
|
|
|
|
* @tWHR_min: WE# high to RE# low
|
|
|
|
* @tWP_min: WE# pulse width
|
|
|
|
* @tWW_min: WP# transition to WE# low
|
|
|
|
*/
|
|
|
|
struct nand_sdr_timings {
|
2017-07-31 15:31:27 +07:00
|
|
|
u64 tBERS_max;
|
2016-10-01 15:24:02 +07:00
|
|
|
u32 tCCS_min;
|
2017-07-31 15:31:27 +07:00
|
|
|
u64 tPROG_max;
|
|
|
|
u64 tR_max;
|
2016-09-15 15:32:46 +07:00
|
|
|
u32 tALH_min;
|
|
|
|
u32 tADL_min;
|
|
|
|
u32 tALS_min;
|
|
|
|
u32 tAR_min;
|
|
|
|
u32 tCEA_max;
|
|
|
|
u32 tCEH_min;
|
|
|
|
u32 tCH_min;
|
|
|
|
u32 tCHZ_max;
|
|
|
|
u32 tCLH_min;
|
|
|
|
u32 tCLR_min;
|
|
|
|
u32 tCLS_min;
|
|
|
|
u32 tCOH_min;
|
|
|
|
u32 tCS_min;
|
|
|
|
u32 tDH_min;
|
|
|
|
u32 tDS_min;
|
|
|
|
u32 tFEAT_max;
|
|
|
|
u32 tIR_min;
|
|
|
|
u32 tITC_max;
|
|
|
|
u32 tRC_min;
|
|
|
|
u32 tREA_max;
|
|
|
|
u32 tREH_min;
|
|
|
|
u32 tRHOH_min;
|
|
|
|
u32 tRHW_min;
|
|
|
|
u32 tRHZ_max;
|
|
|
|
u32 tRLOH_min;
|
|
|
|
u32 tRP_min;
|
|
|
|
u32 tRR_min;
|
|
|
|
u64 tRST_max;
|
|
|
|
u32 tWB_max;
|
|
|
|
u32 tWC_min;
|
|
|
|
u32 tWH_min;
|
|
|
|
u32 tWHR_min;
|
|
|
|
u32 tWP_min;
|
|
|
|
u32 tWW_min;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enum nand_data_interface_type - NAND interface timing type
|
|
|
|
* @NAND_SDR_IFACE: Single Data Rate interface
|
|
|
|
*/
|
|
|
|
enum nand_data_interface_type {
|
|
|
|
NAND_SDR_IFACE,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_data_interface - NAND interface timing
|
2018-05-07 16:35:52 +07:00
|
|
|
* @type: type of the timing
|
|
|
|
* @timings: The timing, type according to @type
|
|
|
|
* @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
|
2016-09-15 15:32:46 +07:00
|
|
|
*/
|
|
|
|
struct nand_data_interface {
|
|
|
|
enum nand_data_interface_type type;
|
|
|
|
union {
|
|
|
|
struct nand_sdr_timings sdr;
|
|
|
|
} timings;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* nand_get_sdr_timings - get SDR timing from data interface
|
|
|
|
* @conf: The data interface
|
|
|
|
*/
|
|
|
|
static inline const struct nand_sdr_timings *
|
|
|
|
nand_get_sdr_timings(const struct nand_data_interface *conf)
|
|
|
|
{
|
|
|
|
if (conf->type != NAND_SDR_IFACE)
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
|
|
|
return &conf->timings.sdr;
|
|
|
|
}
|
|
|
|
|
2017-11-09 20:16:45 +07:00
|
|
|
/**
|
|
|
|
* struct nand_op_cmd_instr - Definition of a command instruction
|
|
|
|
* @opcode: the command to issue in one cycle
|
|
|
|
*/
|
|
|
|
struct nand_op_cmd_instr {
|
|
|
|
u8 opcode;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_addr_instr - Definition of an address instruction
|
|
|
|
* @naddrs: length of the @addrs array
|
|
|
|
* @addrs: array containing the address cycles to issue
|
|
|
|
*/
|
|
|
|
struct nand_op_addr_instr {
|
|
|
|
unsigned int naddrs;
|
|
|
|
const u8 *addrs;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_data_instr - Definition of a data instruction
|
|
|
|
* @len: number of data bytes to move
|
2018-05-07 16:35:52 +07:00
|
|
|
* @buf: buffer to fill
|
|
|
|
* @buf.in: buffer to fill when reading from the NAND chip
|
|
|
|
* @buf.out: buffer to read from when writing to the NAND chip
|
2017-11-09 20:16:45 +07:00
|
|
|
* @force_8bit: force 8-bit access
|
|
|
|
*
|
|
|
|
* Please note that "in" and "out" are inverted from the ONFI specification
|
|
|
|
* and are from the controller perspective, so a "in" is a read from the NAND
|
|
|
|
* chip while a "out" is a write to the NAND chip.
|
|
|
|
*/
|
|
|
|
struct nand_op_data_instr {
|
|
|
|
unsigned int len;
|
|
|
|
union {
|
|
|
|
void *in;
|
|
|
|
const void *out;
|
|
|
|
} buf;
|
|
|
|
bool force_8bit;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_waitrdy_instr - Definition of a wait ready instruction
|
|
|
|
* @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
|
|
|
|
*/
|
|
|
|
struct nand_op_waitrdy_instr {
|
|
|
|
unsigned int timeout_ms;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enum nand_op_instr_type - Definition of all instruction types
|
|
|
|
* @NAND_OP_CMD_INSTR: command instruction
|
|
|
|
* @NAND_OP_ADDR_INSTR: address instruction
|
|
|
|
* @NAND_OP_DATA_IN_INSTR: data in instruction
|
|
|
|
* @NAND_OP_DATA_OUT_INSTR: data out instruction
|
|
|
|
* @NAND_OP_WAITRDY_INSTR: wait ready instruction
|
|
|
|
*/
|
|
|
|
enum nand_op_instr_type {
|
|
|
|
NAND_OP_CMD_INSTR,
|
|
|
|
NAND_OP_ADDR_INSTR,
|
|
|
|
NAND_OP_DATA_IN_INSTR,
|
|
|
|
NAND_OP_DATA_OUT_INSTR,
|
|
|
|
NAND_OP_WAITRDY_INSTR,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_instr - Instruction object
|
|
|
|
* @type: the instruction type
|
2018-05-07 16:35:52 +07:00
|
|
|
* @ctx: extra data associated to the instruction. You'll have to use the
|
|
|
|
* appropriate element depending on @type
|
|
|
|
* @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
|
|
|
|
* @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
|
|
|
|
* @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
|
|
|
|
* or %NAND_OP_DATA_OUT_INSTR
|
|
|
|
* @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
|
2017-11-09 20:16:45 +07:00
|
|
|
* @delay_ns: delay the controller should apply after the instruction has been
|
|
|
|
* issued on the bus. Most modern controllers have internal timings
|
|
|
|
* control logic, and in this case, the controller driver can ignore
|
|
|
|
* this field.
|
|
|
|
*/
|
|
|
|
struct nand_op_instr {
|
|
|
|
enum nand_op_instr_type type;
|
|
|
|
union {
|
|
|
|
struct nand_op_cmd_instr cmd;
|
|
|
|
struct nand_op_addr_instr addr;
|
|
|
|
struct nand_op_data_instr data;
|
|
|
|
struct nand_op_waitrdy_instr waitrdy;
|
|
|
|
} ctx;
|
|
|
|
unsigned int delay_ns;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Special handling must be done for the WAITRDY timeout parameter as it usually
|
|
|
|
* is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
|
|
|
|
* tBERS (during an erase) which all of them are u64 values that cannot be
|
|
|
|
* divided by usual kernel macros and must be handled with the special
|
|
|
|
* DIV_ROUND_UP_ULL() macro.
|
2018-05-14 17:49:37 +07:00
|
|
|
*
|
|
|
|
* Cast to type of dividend is needed here to guarantee that the result won't
|
|
|
|
* be an unsigned long long when the dividend is an unsigned long (or smaller),
|
|
|
|
* which is what the compiler does when it sees ternary operator with 2
|
|
|
|
* different return types (picks the largest type to make sure there's no
|
|
|
|
* loss).
|
|
|
|
*/
|
|
|
|
#define __DIVIDE(dividend, divisor) ({ \
|
|
|
|
(__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
|
|
|
|
DIV_ROUND_UP(dividend, divisor) : \
|
|
|
|
DIV_ROUND_UP_ULL(dividend, divisor)); \
|
|
|
|
})
|
2017-11-09 20:16:45 +07:00
|
|
|
#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
|
|
|
|
#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
|
|
|
|
|
|
|
|
#define NAND_OP_CMD(id, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_CMD_INSTR, \
|
|
|
|
.ctx.cmd.opcode = id, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_ADDR(ncycles, cycles, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_ADDR_INSTR, \
|
|
|
|
.ctx.addr = { \
|
|
|
|
.naddrs = ncycles, \
|
|
|
|
.addrs = cycles, \
|
|
|
|
}, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_DATA_IN(l, b, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_IN_INSTR, \
|
|
|
|
.ctx.data = { \
|
|
|
|
.len = l, \
|
|
|
|
.buf.in = b, \
|
|
|
|
.force_8bit = false, \
|
|
|
|
}, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_DATA_OUT(l, b, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_OUT_INSTR, \
|
|
|
|
.ctx.data = { \
|
|
|
|
.len = l, \
|
|
|
|
.buf.out = b, \
|
|
|
|
.force_8bit = false, \
|
|
|
|
}, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_8BIT_DATA_IN(l, b, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_IN_INSTR, \
|
|
|
|
.ctx.data = { \
|
|
|
|
.len = l, \
|
|
|
|
.buf.in = b, \
|
|
|
|
.force_8bit = true, \
|
|
|
|
}, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_OUT_INSTR, \
|
|
|
|
.ctx.data = { \
|
|
|
|
.len = l, \
|
|
|
|
.buf.out = b, \
|
|
|
|
.force_8bit = true, \
|
|
|
|
}, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_WAIT_RDY(tout_ms, ns) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_WAITRDY_INSTR, \
|
|
|
|
.ctx.waitrdy.timeout_ms = tout_ms, \
|
|
|
|
.delay_ns = ns, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_subop - a sub operation
|
|
|
|
* @instrs: array of instructions
|
|
|
|
* @ninstrs: length of the @instrs array
|
|
|
|
* @first_instr_start_off: offset to start from for the first instruction
|
|
|
|
* of the sub-operation
|
|
|
|
* @last_instr_end_off: offset to end at (excluded) for the last instruction
|
|
|
|
* of the sub-operation
|
|
|
|
*
|
|
|
|
* Both @first_instr_start_off and @last_instr_end_off only apply to data or
|
|
|
|
* address instructions.
|
|
|
|
*
|
|
|
|
* When an operation cannot be handled as is by the NAND controller, it will
|
|
|
|
* be split by the parser into sub-operations which will be passed to the
|
|
|
|
* controller driver.
|
|
|
|
*/
|
|
|
|
struct nand_subop {
|
|
|
|
const struct nand_op_instr *instrs;
|
|
|
|
unsigned int ninstrs;
|
|
|
|
unsigned int first_instr_start_off;
|
|
|
|
unsigned int last_instr_end_off;
|
|
|
|
};
|
|
|
|
|
2018-07-19 05:09:12 +07:00
|
|
|
unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
|
|
|
|
unsigned int op_id);
|
|
|
|
unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
|
|
|
|
unsigned int op_id);
|
|
|
|
unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
|
|
|
|
unsigned int op_id);
|
|
|
|
unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
|
|
|
|
unsigned int op_id);
|
2017-11-09 20:16:45 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_parser_addr_constraints - Constraints for address instructions
|
|
|
|
* @maxcycles: maximum number of address cycles the controller can issue in a
|
|
|
|
* single step
|
|
|
|
*/
|
|
|
|
struct nand_op_parser_addr_constraints {
|
|
|
|
unsigned int maxcycles;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_parser_data_constraints - Constraints for data instructions
|
|
|
|
* @maxlen: maximum data length that the controller can handle in a single step
|
|
|
|
*/
|
|
|
|
struct nand_op_parser_data_constraints {
|
|
|
|
unsigned int maxlen;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_parser_pattern_elem - One element of a pattern
|
|
|
|
* @type: the instructuction type
|
|
|
|
* @optional: whether this element of the pattern is optional or mandatory
|
2018-05-07 16:35:52 +07:00
|
|
|
* @ctx: address or data constraint
|
|
|
|
* @ctx.addr: address constraint (number of cycles)
|
|
|
|
* @ctx.data: data constraint (data length)
|
2017-11-09 20:16:45 +07:00
|
|
|
*/
|
|
|
|
struct nand_op_parser_pattern_elem {
|
|
|
|
enum nand_op_instr_type type;
|
|
|
|
bool optional;
|
|
|
|
union {
|
|
|
|
struct nand_op_parser_addr_constraints addr;
|
|
|
|
struct nand_op_parser_data_constraints data;
|
2018-01-20 01:11:27 +07:00
|
|
|
} ctx;
|
2017-11-09 20:16:45 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_CMD_INSTR, \
|
|
|
|
.optional = _opt, \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_ADDR_INSTR, \
|
|
|
|
.optional = _opt, \
|
2018-01-20 01:11:27 +07:00
|
|
|
.ctx.addr.maxcycles = _maxcycles, \
|
2017-11-09 20:16:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_IN_INSTR, \
|
|
|
|
.optional = _opt, \
|
2018-01-20 01:11:27 +07:00
|
|
|
.ctx.data.maxlen = _maxlen, \
|
2017-11-09 20:16:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_DATA_OUT_INSTR, \
|
|
|
|
.optional = _opt, \
|
2018-01-20 01:11:27 +07:00
|
|
|
.ctx.data.maxlen = _maxlen, \
|
2017-11-09 20:16:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
|
|
|
|
{ \
|
|
|
|
.type = NAND_OP_WAITRDY_INSTR, \
|
|
|
|
.optional = _opt, \
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
|
|
|
|
* @elems: array of pattern elements
|
|
|
|
* @nelems: number of pattern elements in @elems array
|
|
|
|
* @exec: the function that will issue a sub-operation
|
|
|
|
*
|
|
|
|
* A pattern is a list of elements, each element reprensenting one instruction
|
|
|
|
* with its constraints. The pattern itself is used by the core to match NAND
|
|
|
|
* chip operation with NAND controller operations.
|
|
|
|
* Once a match between a NAND controller operation pattern and a NAND chip
|
|
|
|
* operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
|
|
|
|
* hook is called so that the controller driver can issue the operation on the
|
|
|
|
* bus.
|
|
|
|
*
|
|
|
|
* Controller drivers should declare as many patterns as they support and pass
|
|
|
|
* this list of patterns (created with the help of the following macro) to
|
|
|
|
* the nand_op_parser_exec_op() helper.
|
|
|
|
*/
|
|
|
|
struct nand_op_parser_pattern {
|
|
|
|
const struct nand_op_parser_pattern_elem *elems;
|
|
|
|
unsigned int nelems;
|
|
|
|
int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
|
|
|
|
};
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER_PATTERN(_exec, ...) \
|
|
|
|
{ \
|
|
|
|
.exec = _exec, \
|
2019-04-09 11:53:32 +07:00
|
|
|
.elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
|
2017-11-09 20:16:45 +07:00
|
|
|
.nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
|
|
|
|
sizeof(struct nand_op_parser_pattern_elem), \
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_op_parser - NAND controller operation parser descriptor
|
|
|
|
* @patterns: array of supported patterns
|
|
|
|
* @npatterns: length of the @patterns array
|
|
|
|
*
|
|
|
|
* The parser descriptor is just an array of supported patterns which will be
|
|
|
|
* iterated by nand_op_parser_exec_op() everytime it tries to execute an
|
|
|
|
* NAND operation (or tries to determine if a specific operation is supported).
|
|
|
|
*
|
|
|
|
* It is worth mentioning that patterns will be tested in their declaration
|
|
|
|
* order, and the first match will be taken, so it's important to order patterns
|
|
|
|
* appropriately so that simple/inefficient patterns are placed at the end of
|
|
|
|
* the list. Usually, this is where you put single instruction patterns.
|
|
|
|
*/
|
|
|
|
struct nand_op_parser {
|
|
|
|
const struct nand_op_parser_pattern *patterns;
|
|
|
|
unsigned int npatterns;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define NAND_OP_PARSER(...) \
|
|
|
|
{ \
|
2019-04-09 11:53:32 +07:00
|
|
|
.patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
|
2017-11-09 20:16:45 +07:00
|
|
|
.npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
|
|
|
|
sizeof(struct nand_op_parser_pattern), \
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_operation - NAND operation descriptor
|
2018-11-11 14:55:15 +07:00
|
|
|
* @cs: the CS line to select for this NAND operation
|
2017-11-09 20:16:45 +07:00
|
|
|
* @instrs: array of instructions to execute
|
|
|
|
* @ninstrs: length of the @instrs array
|
|
|
|
*
|
|
|
|
* The actual operation structure that will be passed to chip->exec_op().
|
|
|
|
*/
|
|
|
|
struct nand_operation {
|
2018-11-11 14:55:15 +07:00
|
|
|
unsigned int cs;
|
2017-11-09 20:16:45 +07:00
|
|
|
const struct nand_op_instr *instrs;
|
|
|
|
unsigned int ninstrs;
|
|
|
|
};
|
|
|
|
|
2018-11-11 14:55:15 +07:00
|
|
|
#define NAND_OPERATION(_cs, _instrs) \
|
2017-11-09 20:16:45 +07:00
|
|
|
{ \
|
2018-11-11 14:55:15 +07:00
|
|
|
.cs = _cs, \
|
2017-11-09 20:16:45 +07:00
|
|
|
.instrs = _instrs, \
|
|
|
|
.ninstrs = ARRAY_SIZE(_instrs), \
|
|
|
|
}
|
|
|
|
|
|
|
|
int nand_op_parser_exec_op(struct nand_chip *chip,
|
|
|
|
const struct nand_op_parser *parser,
|
|
|
|
const struct nand_operation *op, bool check_only);
|
2018-10-25 20:21:08 +07:00
|
|
|
|
2019-05-21 14:06:30 +07:00
|
|
|
static inline void nand_op_trace(const char *prefix,
|
|
|
|
const struct nand_op_instr *instr)
|
|
|
|
{
|
|
|
|
#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
|
|
|
|
switch (instr->type) {
|
|
|
|
case NAND_OP_CMD_INSTR:
|
|
|
|
pr_debug("%sCMD [0x%02x]\n", prefix,
|
|
|
|
instr->ctx.cmd.opcode);
|
|
|
|
break;
|
|
|
|
case NAND_OP_ADDR_INSTR:
|
|
|
|
pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
|
|
|
|
instr->ctx.addr.naddrs,
|
|
|
|
instr->ctx.addr.naddrs < 64 ?
|
|
|
|
instr->ctx.addr.naddrs : 64,
|
|
|
|
instr->ctx.addr.addrs);
|
|
|
|
break;
|
|
|
|
case NAND_OP_DATA_IN_INSTR:
|
|
|
|
pr_debug("%sDATA_IN [%d B%s]\n", prefix,
|
|
|
|
instr->ctx.data.len,
|
|
|
|
instr->ctx.data.force_8bit ?
|
|
|
|
", force 8-bit" : "");
|
|
|
|
break;
|
|
|
|
case NAND_OP_DATA_OUT_INSTR:
|
|
|
|
pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
|
|
|
|
instr->ctx.data.len,
|
|
|
|
instr->ctx.data.force_8bit ?
|
|
|
|
", force 8-bit" : "");
|
|
|
|
break;
|
|
|
|
case NAND_OP_WAITRDY_INSTR:
|
|
|
|
pr_debug("%sWAITRDY [max %d ms]\n", prefix,
|
|
|
|
instr->ctx.waitrdy.timeout_ms);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2018-11-11 14:55:23 +07:00
|
|
|
/**
|
|
|
|
* struct nand_controller_ops - Controller operations
|
|
|
|
*
|
|
|
|
* @attach_chip: this method is called after the NAND detection phase after
|
|
|
|
* flash ID and MTD fields such as erase size, page size and OOB
|
|
|
|
* size have been set up. ECC requirements are available if
|
|
|
|
* provided by the NAND chip or device tree. Typically used to
|
|
|
|
* choose the appropriate ECC configuration and allocate
|
|
|
|
* associated resources.
|
|
|
|
* This hook is optional.
|
|
|
|
* @detach_chip: free all resources allocated/claimed in
|
|
|
|
* nand_controller_ops->attach_chip().
|
|
|
|
* This hook is optional.
|
|
|
|
* @exec_op: controller specific method to execute NAND operations.
|
|
|
|
* This method replaces chip->legacy.cmdfunc(),
|
|
|
|
* chip->legacy.{read,write}_{buf,byte,word}(),
|
|
|
|
* chip->legacy.dev_ready() and chip->legacy.waifunc().
|
2018-11-11 14:55:24 +07:00
|
|
|
* @setup_data_interface: setup the data interface and timing. If
|
|
|
|
* chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
|
|
|
|
* means the configuration should not be applied but
|
|
|
|
* only checked.
|
|
|
|
* This hook is optional.
|
2018-11-11 14:55:23 +07:00
|
|
|
*/
|
|
|
|
struct nand_controller_ops {
|
|
|
|
int (*attach_chip)(struct nand_chip *chip);
|
|
|
|
void (*detach_chip)(struct nand_chip *chip);
|
|
|
|
int (*exec_op)(struct nand_chip *chip,
|
|
|
|
const struct nand_operation *op,
|
|
|
|
bool check_only);
|
2018-11-11 14:55:24 +07:00
|
|
|
int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
|
|
|
|
const struct nand_data_interface *conf);
|
2018-11-11 14:55:23 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct nand_controller - Structure used to describe a NAND controller
|
|
|
|
*
|
2018-11-20 17:57:20 +07:00
|
|
|
* @lock: lock used to serialize accesses to the NAND controller
|
2018-11-11 14:55:23 +07:00
|
|
|
* @ops: NAND controller operations.
|
|
|
|
*/
|
|
|
|
struct nand_controller {
|
2018-11-20 17:57:20 +07:00
|
|
|
struct mutex lock;
|
2018-11-11 14:55:23 +07:00
|
|
|
const struct nand_controller_ops *ops;
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline void nand_controller_init(struct nand_controller *nfc)
|
|
|
|
{
|
2018-11-20 17:57:20 +07:00
|
|
|
mutex_init(&nfc->lock);
|
2018-11-11 14:55:23 +07:00
|
|
|
}
|
2017-11-09 20:16:45 +07:00
|
|
|
|
2018-09-07 05:38:34 +07:00
|
|
|
/**
|
|
|
|
* struct nand_legacy - NAND chip legacy fields/hooks
|
|
|
|
* @IO_ADDR_R: address to read the 8 I/O lines of the flash device
|
|
|
|
* @IO_ADDR_W: address to write the 8 I/O lines of the flash device
|
2018-11-11 14:55:22 +07:00
|
|
|
* @select_chip: select/deselect a specific target/die
|
2018-09-07 05:38:35 +07:00
|
|
|
* @read_byte: read one byte from the chip
|
|
|
|
* @write_byte: write a single byte to the chip on the low 8 I/O lines
|
|
|
|
* @write_buf: write data from the buffer to the chip
|
|
|
|
* @read_buf: read data from the chip into the buffer
|
2018-09-07 05:38:36 +07:00
|
|
|
* @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
|
|
|
|
* to write command and address
|
|
|
|
* @cmdfunc: hardware specific function for writing commands to the chip.
|
2018-09-07 05:38:37 +07:00
|
|
|
* @dev_ready: hardware specific function for accessing device ready/busy line.
|
|
|
|
* If set to NULL no access to ready/busy is available and the
|
|
|
|
* ready/busy information is read from the chip status register.
|
|
|
|
* @waitfunc: hardware specific function for wait on ready.
|
2018-09-07 05:38:38 +07:00
|
|
|
* @block_bad: check if a block is bad, using OOB markers
|
|
|
|
* @block_markbad: mark a block bad
|
2018-09-07 05:38:40 +07:00
|
|
|
* @set_features: set the NAND chip features
|
|
|
|
* @get_features: get the NAND chip features
|
2018-09-07 05:38:41 +07:00
|
|
|
* @chip_delay: chip dependent delay for transferring data from array to read
|
|
|
|
* regs (tR).
|
2018-11-20 16:02:39 +07:00
|
|
|
* @dummy_controller: dummy controller implementation for drivers that can
|
|
|
|
* only control a single chip
|
2018-09-07 05:38:34 +07:00
|
|
|
*
|
|
|
|
* If you look at this structure you're already wrong. These fields/hooks are
|
|
|
|
* all deprecated.
|
|
|
|
*/
|
|
|
|
struct nand_legacy {
|
|
|
|
void __iomem *IO_ADDR_R;
|
|
|
|
void __iomem *IO_ADDR_W;
|
2018-11-11 14:55:22 +07:00
|
|
|
void (*select_chip)(struct nand_chip *chip, int cs);
|
2018-09-07 05:38:35 +07:00
|
|
|
u8 (*read_byte)(struct nand_chip *chip);
|
|
|
|
void (*write_byte)(struct nand_chip *chip, u8 byte);
|
|
|
|
void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
|
|
|
|
void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
|
2018-09-07 05:38:36 +07:00
|
|
|
void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
|
|
|
|
void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
|
|
|
|
int page_addr);
|
2018-09-07 05:38:37 +07:00
|
|
|
int (*dev_ready)(struct nand_chip *chip);
|
|
|
|
int (*waitfunc)(struct nand_chip *chip);
|
2018-09-07 05:38:38 +07:00
|
|
|
int (*block_bad)(struct nand_chip *chip, loff_t ofs);
|
|
|
|
int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
|
2018-09-07 05:38:40 +07:00
|
|
|
int (*set_features)(struct nand_chip *chip, int feature_addr,
|
|
|
|
u8 *subfeature_para);
|
|
|
|
int (*get_features)(struct nand_chip *chip, int feature_addr,
|
|
|
|
u8 *subfeature_para);
|
2018-09-07 05:38:41 +07:00
|
|
|
int chip_delay;
|
2018-11-20 16:02:39 +07:00
|
|
|
struct nand_controller dummy_controller;
|
2018-09-07 05:38:34 +07:00
|
|
|
};
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
|
|
|
* struct nand_chip - NAND Private Flash Chip Data
|
2018-10-25 20:21:08 +07:00
|
|
|
* @base: Inherit from the generic NAND device
|
2018-09-07 05:38:34 +07:00
|
|
|
* @legacy: All legacy fields/hooks. If you develop a new driver,
|
|
|
|
* don't even try to use any of these fields/hooks, and if
|
|
|
|
* you're modifying an existing driver that is using those
|
|
|
|
* fields/hooks, you should consider reworking the driver
|
|
|
|
* avoid using them.
|
mtd: nand: add generic READ RETRY support
Modern MLC (and even SLC?) NAND can experience a large number of
bitflips (beyond the recommended correctability capacity) due to drifts
in the voltage threshold (Vt). These bitflips can cause ECC errors to
occur well within the expected lifetime of the flash. To account for
this, some manufacturers provide a mechanism for shifting the Vt
threshold after a corrupted read.
The generic pattern seems to be that a particular flash has N read retry
modes (where N = 0, traditionally), and after an ECC failure, the host
should reconfigure the flash to use the next available mode, then retry
the read operation. This process repeats until all bitfips can be
corrected or until the host has tried all available retry modes.
This patch adds the infrastructure support for a
vendor-specific/flash-specific callback, used for setting the read-retry
mode (i.e., voltage threshold).
For now, this patch always returns the flash to mode 0 (the default
mode) after a successful read-retry, according to the flowchart found in
Micron's datasheets. This may need to change in the future if it is
determined that eventually, mode 0 is insufficient for the majority of
the flash cells (and so for performance reasons, we should leave the
flash in mode 1, 2, etc.).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-01-04 06:13:33 +07:00
|
|
|
* @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
|
|
|
|
* setting the read-retry mode. Mostly needed for MLC NAND.
|
2011-06-24 04:12:08 +07:00
|
|
|
* @ecc: [BOARDSPECIFIC] ECC control structure
|
2017-03-30 15:15:05 +07:00
|
|
|
* @buf_align: minimum buffer alignment required by a platform
|
2011-08-31 08:45:43 +07:00
|
|
|
* @oob_poi: "poison value buffer," used for laying out OOB data
|
|
|
|
* before writing
|
2010-10-05 17:41:01 +07:00
|
|
|
* @page_shift: [INTERN] number of address bits in a page (column
|
|
|
|
* address bits).
|
2005-04-17 05:20:36 +07:00
|
|
|
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
|
|
|
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
|
|
|
* @chip_shift: [INTERN] number of address bits in one chip
|
2010-10-05 17:41:01 +07:00
|
|
|
* @options: [BOARDSPECIFIC] various chip options. They can partly
|
|
|
|
* be set to inform nand_scan about special functionality.
|
|
|
|
* See the defines for further explanation.
|
2011-06-01 06:31:21 +07:00
|
|
|
* @bbt_options: [INTERN] bad block specific options. All options used
|
|
|
|
* here must come from bbm.h. By default, these options
|
|
|
|
* will be copied to the appropriate nand_bbt_descr's.
|
2010-10-05 17:41:01 +07:00
|
|
|
* @badblockpos: [INTERN] position of the bad block marker in the oob
|
|
|
|
* area.
|
2012-01-14 09:11:50 +07:00
|
|
|
* @badblockbits: [INTERN] minimum number of set bits in a good block's
|
|
|
|
* bad block marker position; i.e., BBM == 11110111b is
|
|
|
|
* not bad when badblockbits == 7
|
2014-09-23 01:11:50 +07:00
|
|
|
* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
|
2016-09-15 15:32:50 +07:00
|
|
|
* set to the actually used ONFI mode if the chip is
|
|
|
|
* ONFI compliant or deduced from the datasheet if
|
|
|
|
* the NAND chip is not ONFI compliant.
|
2005-04-17 05:20:36 +07:00
|
|
|
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
2017-12-05 15:47:16 +07:00
|
|
|
* @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
|
2018-10-28 22:12:45 +07:00
|
|
|
* @pagecache: Structure containing page cache related fields
|
|
|
|
* @pagecache.bitflips: Number of bitflips of the cached page
|
|
|
|
* @pagecache.page: Page number currently in the cache. -1 means no page is
|
|
|
|
* currently cached
|
2006-09-28 20:38:36 +07:00
|
|
|
* @subpagesize: [INTERN] holds the subpagesize
|
2016-05-25 00:20:05 +07:00
|
|
|
* @id: [INTERN] holds NAND ID
|
2018-03-19 20:47:26 +07:00
|
|
|
* @parameters: [INTERN] holds generic parameters under an easily
|
|
|
|
* readable form.
|
2016-11-22 09:32:08 +07:00
|
|
|
* @data_interface: [INTERN] NAND interface timing information
|
2018-11-11 14:55:15 +07:00
|
|
|
* @cur_cs: currently selected target. -1 means no target selected,
|
|
|
|
* otherwise we should always have cur_cs >= 0 &&
|
2018-10-29 17:58:29 +07:00
|
|
|
* cur_cs < nanddev_ntargets(). NAND Controller drivers
|
|
|
|
* should not modify this value, but they're allowed to
|
|
|
|
* read it.
|
mtd: nand: add generic READ RETRY support
Modern MLC (and even SLC?) NAND can experience a large number of
bitflips (beyond the recommended correctability capacity) due to drifts
in the voltage threshold (Vt). These bitflips can cause ECC errors to
occur well within the expected lifetime of the flash. To account for
this, some manufacturers provide a mechanism for shifting the Vt
threshold after a corrupted read.
The generic pattern seems to be that a particular flash has N read retry
modes (where N = 0, traditionally), and after an ECC failure, the host
should reconfigure the flash to use the next available mode, then retry
the read operation. This process repeats until all bitfips can be
corrected or until the host has tried all available retry modes.
This patch adds the infrastructure support for a
vendor-specific/flash-specific callback, used for setting the read-retry
mode (i.e., voltage threshold).
For now, this patch always returns the flash to mode 0 (the default
mode) after a successful read-retry, according to the flowchart found in
Micron's datasheets. This may need to change in the future if it is
determined that eventually, mode 0 is insufficient for the majority of
the flash cells (and so for performance reasons, we should leave the
flash in mode 1, 2, etc.).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-01-04 06:13:33 +07:00
|
|
|
* @read_retries: [INTERN] the number of read retry modes supported
|
2018-11-20 17:57:20 +07:00
|
|
|
* @lock: lock protecting the suspended field. Also used to
|
|
|
|
* serialize accesses to the NAND device.
|
|
|
|
* @suspended: set to 1 when the device is suspended, 0 when it's not.
|
2005-04-17 05:20:36 +07:00
|
|
|
* @bbt: [INTERN] bad block table pointer
|
2010-10-05 17:41:01 +07:00
|
|
|
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
|
|
|
|
* lookup.
|
2005-04-17 05:20:36 +07:00
|
|
|
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
2010-10-05 17:41:01 +07:00
|
|
|
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
|
|
|
|
* bad block scan.
|
|
|
|
* @controller: [REPLACEABLE] a pointer to a hardware controller
|
2011-06-24 04:12:08 +07:00
|
|
|
* structure which is shared among multiple independent
|
2010-10-05 17:41:01 +07:00
|
|
|
* devices.
|
2011-08-24 07:17:35 +07:00
|
|
|
* @priv: [OPTIONAL] pointer to private chip data
|
2016-06-08 14:32:55 +07:00
|
|
|
* @manufacturer: [INTERN] Contains manufacturer information
|
2018-05-07 16:35:52 +07:00
|
|
|
* @manufacturer.desc: [INTERN] Contains manufacturer's description
|
|
|
|
* @manufacturer.priv: [INTERN] Contains manufacturer private information
|
2005-04-17 05:20:36 +07:00
|
|
|
*/
|
2005-11-07 18:15:31 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
struct nand_chip {
|
2018-10-25 20:21:08 +07:00
|
|
|
struct nand_device base;
|
2018-09-07 05:38:34 +07:00
|
|
|
|
|
|
|
struct nand_legacy legacy;
|
2010-10-08 02:48:27 +07:00
|
|
|
|
2018-09-06 19:05:32 +07:00
|
|
|
int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
|
2016-09-15 15:32:50 +07:00
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
unsigned int options;
|
2011-06-01 06:31:21 +07:00
|
|
|
unsigned int bbt_options;
|
2010-10-08 02:48:27 +07:00
|
|
|
|
|
|
|
int page_shift;
|
|
|
|
int phys_erase_shift;
|
|
|
|
int bbt_erase_shift;
|
|
|
|
int chip_shift;
|
|
|
|
int pagemask;
|
2017-12-05 15:47:16 +07:00
|
|
|
u8 *data_buf;
|
2018-10-28 22:12:45 +07:00
|
|
|
|
|
|
|
struct {
|
|
|
|
unsigned int bitflips;
|
|
|
|
int page;
|
|
|
|
} pagecache;
|
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
int subpagesize;
|
2014-09-23 01:11:50 +07:00
|
|
|
int onfi_timing_mode_default;
|
2019-04-17 19:36:34 +07:00
|
|
|
unsigned int badblockpos;
|
2010-10-08 02:48:27 +07:00
|
|
|
int badblockbits;
|
|
|
|
|
2016-05-25 00:20:05 +07:00
|
|
|
struct nand_id id;
|
2018-03-19 20:47:26 +07:00
|
|
|
struct nand_parameters parameters;
|
2010-08-30 23:32:24 +07:00
|
|
|
|
2017-12-01 00:01:31 +07:00
|
|
|
struct nand_data_interface data_interface;
|
2016-09-15 15:32:50 +07:00
|
|
|
|
2018-11-11 14:55:15 +07:00
|
|
|
int cur_cs;
|
|
|
|
|
mtd: nand: add generic READ RETRY support
Modern MLC (and even SLC?) NAND can experience a large number of
bitflips (beyond the recommended correctability capacity) due to drifts
in the voltage threshold (Vt). These bitflips can cause ECC errors to
occur well within the expected lifetime of the flash. To account for
this, some manufacturers provide a mechanism for shifting the Vt
threshold after a corrupted read.
The generic pattern seems to be that a particular flash has N read retry
modes (where N = 0, traditionally), and after an ECC failure, the host
should reconfigure the flash to use the next available mode, then retry
the read operation. This process repeats until all bitfips can be
corrected or until the host has tried all available retry modes.
This patch adds the infrastructure support for a
vendor-specific/flash-specific callback, used for setting the read-retry
mode (i.e., voltage threshold).
For now, this patch always returns the flash to mode 0 (the default
mode) after a successful read-retry, according to the flowchart found in
Micron's datasheets. This may need to change in the future if it is
determined that eventually, mode 0 is insufficient for the majority of
the flash cells (and so for performance reasons, we should leave the
flash in mode 1, 2, etc.).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
2014-01-04 06:13:33 +07:00
|
|
|
int read_retries;
|
|
|
|
|
2018-11-20 17:57:20 +07:00
|
|
|
struct mutex lock;
|
|
|
|
unsigned int suspended : 1;
|
2006-05-26 23:52:08 +07:00
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
uint8_t *oob_poi;
|
2018-07-17 14:08:02 +07:00
|
|
|
struct nand_controller *controller;
|
2006-05-26 23:52:08 +07:00
|
|
|
|
|
|
|
struct nand_ecc_ctrl ecc;
|
2017-03-30 15:15:05 +07:00
|
|
|
unsigned long buf_align;
|
2006-05-26 23:52:08 +07:00
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
uint8_t *bbt;
|
|
|
|
struct nand_bbt_descr *bbt_td;
|
|
|
|
struct nand_bbt_descr *bbt_md;
|
2006-05-26 23:52:08 +07:00
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
struct nand_bbt_descr *badblock_pattern;
|
2006-05-26 23:52:08 +07:00
|
|
|
|
2010-10-08 02:48:27 +07:00
|
|
|
void *priv;
|
2016-06-08 14:32:55 +07:00
|
|
|
|
|
|
|
struct {
|
|
|
|
const struct nand_manufacturer *desc;
|
|
|
|
void *priv;
|
|
|
|
} manufacturer;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2016-02-04 01:06:15 +07:00
|
|
|
extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
|
|
|
|
extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
|
|
|
|
|
2015-11-16 20:37:35 +07:00
|
|
|
static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
|
|
|
|
{
|
2018-10-25 20:21:08 +07:00
|
|
|
return container_of(mtd, struct nand_chip, base.mtd);
|
2015-11-16 20:37:35 +07:00
|
|
|
}
|
|
|
|
|
2015-12-01 18:03:07 +07:00
|
|
|
static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
|
|
|
|
{
|
2018-10-25 20:21:08 +07:00
|
|
|
return &chip->base.mtd;
|
2015-12-01 18:03:07 +07:00
|
|
|
}
|
|
|
|
|
2015-12-10 15:00:39 +07:00
|
|
|
static inline void *nand_get_controller_data(struct nand_chip *chip)
|
|
|
|
{
|
|
|
|
return chip->priv;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
|
|
|
|
{
|
|
|
|
chip->priv = priv;
|
|
|
|
}
|
|
|
|
|
2016-06-08 14:32:55 +07:00
|
|
|
static inline void nand_set_manufacturer_data(struct nand_chip *chip,
|
|
|
|
void *priv)
|
|
|
|
{
|
|
|
|
chip->manufacturer.priv = priv;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
|
|
|
|
{
|
|
|
|
return chip->manufacturer.priv;
|
|
|
|
}
|
|
|
|
|
2018-10-25 20:05:39 +07:00
|
|
|
static inline void nand_set_flash_node(struct nand_chip *chip,
|
|
|
|
struct device_node *np)
|
|
|
|
{
|
|
|
|
mtd_set_of_node(nand_to_mtd(chip), np);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
|
|
|
|
{
|
|
|
|
return mtd_get_of_node(nand_to_mtd(chip));
|
|
|
|
}
|
|
|
|
|
2013-03-04 20:39:18 +07:00
|
|
|
/*
|
|
|
|
* A helper for defining older NAND chips where the second ID byte fully
|
|
|
|
* defined the chip, including the geometry (chip size, eraseblock size, page
|
2013-03-19 15:29:26 +07:00
|
|
|
* size). All these chips have 512 bytes NAND page size.
|
2013-03-04 20:39:18 +07:00
|
|
|
*/
|
2013-03-19 15:29:26 +07:00
|
|
|
#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
|
|
|
|
{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
|
|
|
|
.chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
|
2013-03-04 20:39:18 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* A helper for defining newer chips which report their page size and
|
|
|
|
* eraseblock size via the extended ID bytes.
|
|
|
|
*
|
|
|
|
* The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
|
|
|
|
* EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
|
|
|
|
* device ID now only represented a particular total chip size (and voltage,
|
|
|
|
* buswidth), and the page size, eraseblock size, and OOB size could vary while
|
|
|
|
* using the same device ID.
|
|
|
|
*/
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
|
|
|
|
{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
|
2013-03-04 20:39:18 +07:00
|
|
|
.options = (opts) }
|
|
|
|
|
2013-05-17 10:17:31 +07:00
|
|
|
#define NAND_ECC_INFO(_strength, _step) \
|
|
|
|
{ .strength_ds = (_strength), .step_ds = (_step) }
|
|
|
|
#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
|
|
|
|
#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
|
|
|
* struct nand_flash_dev - NAND Flash Device ID Structure
|
2013-03-04 21:05:00 +07:00
|
|
|
* @name: a human-readable name of the NAND chip
|
|
|
|
* @dev_id: the device ID (the second byte of the full chip ID array)
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
* @mfr_id: manufecturer ID part of the full chip ID array (refers the same
|
2019-03-22 06:52:41 +07:00
|
|
|
* memory address as ``id[0]``)
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
* @dev_id: device ID part of the full chip ID array (refers the same memory
|
2019-03-22 06:52:41 +07:00
|
|
|
* address as ``id[1]``)
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
* @id: full device ID array
|
2013-03-04 21:05:00 +07:00
|
|
|
* @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
|
|
|
|
* well as the eraseblock size) is determined from the extended NAND
|
|
|
|
* chip ID array)
|
|
|
|
* @chipsize: total chip size in MiB
|
2013-03-13 18:45:00 +07:00
|
|
|
* @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
|
2013-03-04 21:05:00 +07:00
|
|
|
* @options: stores various chip bit options
|
2013-03-15 10:00:59 +07:00
|
|
|
* @id_len: The valid length of the @id.
|
|
|
|
* @oobsize: OOB size
|
2014-07-28 04:31:53 +07:00
|
|
|
* @ecc: ECC correctability and step information from the datasheet.
|
2013-05-17 10:17:31 +07:00
|
|
|
* @ecc.strength_ds: The ECC correctability from the datasheet, same as the
|
|
|
|
* @ecc_strength_ds in nand_chip{}.
|
|
|
|
* @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
|
|
|
|
* @ecc_step_ds in nand_chip{}, also from the datasheet.
|
|
|
|
* For example, the "4bit ECC for each 512Byte" can be set with
|
|
|
|
* NAND_ECC_INFO(4, 512).
|
2014-09-23 01:11:50 +07:00
|
|
|
* @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
|
|
|
|
* reset. Should be deduced from timings described
|
|
|
|
* in the datasheet.
|
|
|
|
*
|
2005-04-17 05:20:36 +07:00
|
|
|
*/
|
|
|
|
struct nand_flash_dev {
|
|
|
|
char *name;
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
uint8_t mfr_id;
|
|
|
|
uint8_t dev_id;
|
|
|
|
};
|
2013-03-14 14:57:23 +07:00
|
|
|
uint8_t id[NAND_MAX_ID_LEN];
|
mtd: nand: provision full ID support
Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:
Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08
The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.
This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.
This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-03-04 21:26:56 +07:00
|
|
|
};
|
2013-03-13 18:45:00 +07:00
|
|
|
unsigned int pagesize;
|
|
|
|
unsigned int chipsize;
|
|
|
|
unsigned int erasesize;
|
|
|
|
unsigned int options;
|
2013-03-15 10:00:59 +07:00
|
|
|
uint16_t id_len;
|
|
|
|
uint16_t oobsize;
|
2013-05-17 10:17:31 +07:00
|
|
|
struct {
|
|
|
|
uint16_t strength_ds;
|
|
|
|
uint16_t step_ds;
|
|
|
|
} ecc;
|
2014-09-23 01:11:50 +07:00
|
|
|
int onfi_timing_mode_default;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2018-07-05 17:27:30 +07:00
|
|
|
int nand_create_bbt(struct nand_chip *chip);
|
2016-09-15 15:32:48 +07:00
|
|
|
|
2013-09-25 13:58:10 +07:00
|
|
|
/*
|
|
|
|
* Check if it is a SLC nand.
|
|
|
|
* The !nand_is_slc() can be used to check the MLC/TLC nand chips.
|
|
|
|
* We do not distinguish the MLC and TLC now.
|
|
|
|
*/
|
|
|
|
static inline bool nand_is_slc(struct nand_chip *chip)
|
|
|
|
{
|
2018-10-25 22:16:47 +07:00
|
|
|
WARN(nanddev_bits_per_cell(&chip->base) == 0,
|
2017-08-29 17:17:13 +07:00
|
|
|
"chip->bits_per_cell is used uninitialized\n");
|
2018-10-25 22:16:47 +07:00
|
|
|
return nanddev_bits_per_cell(&chip->base) == 1;
|
2013-09-25 13:58:10 +07:00
|
|
|
}
|
mtd: nand: force NAND_CMD_READID onto 8-bit bus
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults. Note that I don't touch sh_flctl.c, since it already
handles this problem slightly differently (note its comment "READID is
always performed using an 8-bit bus").
I have not tested this patch, as I only have x8 parts up for testing at
this point. Hopefully that can change soon...
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
2014-01-30 05:08:12 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Check if the opcode's address should be sent only on the lower 8 bits
|
|
|
|
* @command: opcode to check
|
|
|
|
*/
|
|
|
|
static inline int nand_opcode_8bits(unsigned int command)
|
|
|
|
{
|
2014-03-22 05:05:10 +07:00
|
|
|
switch (command) {
|
|
|
|
case NAND_CMD_READID:
|
|
|
|
case NAND_CMD_PARAM:
|
|
|
|
case NAND_CMD_GET_FEATURES:
|
|
|
|
case NAND_CMD_SET_FEATURES:
|
|
|
|
return 1;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
mtd: nand: force NAND_CMD_READID onto 8-bit bus
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults. Note that I don't touch sh_flctl.c, since it already
handles this problem slightly differently (note its comment "READID is
always performed using an 8-bit bus").
I have not tested this patch, as I only have x8 parts up for testing at
this point. Hopefully that can change soon...
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
2014-01-30 05:08:12 +07:00
|
|
|
}
|
|
|
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2015-09-03 23:03:38 +07:00
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int nand_check_erased_ecc_chunk(void *data, int datalen,
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void *ecc, int ecclen,
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void *extraoob, int extraooblen,
|
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int threshold);
|
2015-08-26 21:08:12 +07:00
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2018-06-20 14:27:28 +07:00
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int nand_ecc_choose_conf(struct nand_chip *chip,
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const struct nand_ecc_caps *caps, int oobavail);
|
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2015-08-26 21:08:12 +07:00
|
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/* Default write_oob implementation */
|
2018-09-06 19:05:21 +07:00
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int nand_write_oob_std(struct nand_chip *chip, int page);
|
2015-08-26 21:08:12 +07:00
|
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|
|
|
|
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/* Default read_oob implementation */
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2018-09-06 19:05:20 +07:00
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int nand_read_oob_std(struct nand_chip *chip, int page);
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2015-08-26 21:08:12 +07:00
|
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|
2017-05-26 22:10:15 +07:00
|
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/* Stub used by drivers that do not support GET/SET FEATURES operations */
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2018-09-06 19:05:31 +07:00
|
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int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
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|
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u8 *subfeature_param);
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2017-05-26 22:10:15 +07:00
|
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2017-04-29 16:06:44 +07:00
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/* Default read_page_raw implementation */
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2018-09-06 19:05:20 +07:00
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int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
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|
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int page);
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2017-04-29 16:06:44 +07:00
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/* Default write_page_raw implementation */
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2018-09-06 19:05:21 +07:00
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int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
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int oob_required, int page);
|
2017-04-29 16:06:44 +07:00
|
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2016-09-15 15:32:45 +07:00
|
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/* Reset and initialize a NAND device */
|
2016-10-24 21:46:20 +07:00
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int nand_reset(struct nand_chip *chip, int chipnr);
|
2016-09-15 15:32:45 +07:00
|
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|
2017-12-01 00:01:29 +07:00
|
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|
/* NAND operation helpers */
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int nand_reset_op(struct nand_chip *chip);
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int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
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|
|
unsigned int len);
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|
int nand_status_op(struct nand_chip *chip, u8 *status);
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|
|
int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
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|
|
int nand_read_page_op(struct nand_chip *chip, unsigned int page,
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|
|
unsigned int offset_in_page, void *buf, unsigned int len);
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|
|
int nand_change_read_column_op(struct nand_chip *chip,
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|
|
unsigned int offset_in_page, void *buf,
|
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|
|
unsigned int len, bool force_8bit);
|
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|
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int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
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|
|
unsigned int offset_in_page, void *buf, unsigned int len);
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|
int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
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|
|
unsigned int offset_in_page, const void *buf,
|
|
|
|
unsigned int len);
|
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|
|
int nand_prog_page_end_op(struct nand_chip *chip);
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int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
|
|
|
|
unsigned int offset_in_page, const void *buf,
|
|
|
|
unsigned int len);
|
|
|
|
int nand_change_write_column_op(struct nand_chip *chip,
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|
|
unsigned int offset_in_page, const void *buf,
|
|
|
|
unsigned int len, bool force_8bit);
|
|
|
|
int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
|
|
|
|
bool force_8bit);
|
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|
|
int nand_write_data_op(struct nand_chip *chip, const void *buf,
|
|
|
|
unsigned int len, bool force_8bit);
|
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|
|
|
2018-09-07 05:38:42 +07:00
|
|
|
/* Scan and identify a NAND device */
|
|
|
|
int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
|
|
|
|
struct nand_flash_dev *ids);
|
|
|
|
|
|
|
|
static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
|
|
|
|
{
|
|
|
|
return nand_scan_with_ids(chip, max_chips, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Internal helper for board drivers which need to override command function */
|
|
|
|
void nand_wait_ready(struct nand_chip *chip);
|
|
|
|
|
2018-07-25 20:31:50 +07:00
|
|
|
/*
|
|
|
|
* Free resources held by the NAND device, must be called on error after a
|
|
|
|
* sucessful nand_scan().
|
|
|
|
*/
|
2016-09-21 16:44:41 +07:00
|
|
|
void nand_cleanup(struct nand_chip *chip);
|
2018-07-25 20:31:50 +07:00
|
|
|
/* Unregister the MTD device and calls nand_cleanup() */
|
2018-09-06 19:05:15 +07:00
|
|
|
void nand_release(struct nand_chip *chip);
|
2016-09-21 16:44:41 +07:00
|
|
|
|
2017-11-09 20:16:45 +07:00
|
|
|
/*
|
|
|
|
* External helper for controller drivers that have to implement the WAITRDY
|
|
|
|
* instruction and have no physical pin to check it.
|
|
|
|
*/
|
|
|
|
int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
|
2018-10-16 02:41:28 +07:00
|
|
|
struct gpio_desc;
|
|
|
|
int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
|
|
|
|
unsigned long timeout_ms);
|
|
|
|
|
2018-11-11 14:55:14 +07:00
|
|
|
/* Select/deselect a NAND target. */
|
|
|
|
void nand_select_target(struct nand_chip *chip, unsigned int cs);
|
|
|
|
void nand_deselect_target(struct nand_chip *chip);
|
|
|
|
|
2018-10-28 21:27:55 +07:00
|
|
|
/**
|
|
|
|
* nand_get_data_buf() - Get the internal page buffer
|
|
|
|
* @chip: NAND chip object
|
|
|
|
*
|
|
|
|
* Returns the pre-allocated page buffer after invalidating the cache. This
|
|
|
|
* function should be used by drivers that do not want to allocate their own
|
|
|
|
* bounce buffer and still need such a buffer for specific operations (most
|
|
|
|
* commonly when reading OOB data only).
|
|
|
|
*
|
|
|
|
* Be careful to never call this function in the write/write_oob path, because
|
|
|
|
* the core may have placed the data to be written out in this buffer.
|
|
|
|
*
|
|
|
|
* Return: pointer to the page cache buffer
|
|
|
|
*/
|
|
|
|
static inline void *nand_get_data_buf(struct nand_chip *chip)
|
|
|
|
{
|
2018-10-28 22:12:45 +07:00
|
|
|
chip->pagecache.page = -1;
|
2018-10-28 21:27:55 +07:00
|
|
|
|
|
|
|
return chip->data_buf;
|
|
|
|
}
|
|
|
|
|
2017-08-04 22:29:10 +07:00
|
|
|
#endif /* __LINUX_MTD_RAWNAND_H */
|