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linux_dsm_epyc7002/arch/arm/boot/dts/sun5i.dtsi

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ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
/*
* Copyright 2012-2015 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
#include <dt-bindings/clock/sun5i-ccu.h>
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#include <dt-bindings/dma/sun4i-a10.h>
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
#include <dt-bindings/reset/sun5i-ccu.h>
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
/ {
interrupt-parent = <&intc>;
ARM: dts: sun5i: Remove skeleton to avoid warnings Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:41:42 +07:00
#address-cells = <1>;
#size-cells = <1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_CPU>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
};
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dts: sun5i: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:05:18 +07:00
framebuffer-lcd0 {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled";
};
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
ARM: dts: sun5i: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:05:18 +07:00
framebuffer-lcd0-tve0 {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
<&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
status = "disabled";
};
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
};
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dts: sun5i: Change clock node names to avoid warnings Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:34:40 +07:00
osc24M: clk-24M {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#clock-cells = <0>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
compatible = "fixed-clock";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
ARM: dts: sun5i: Change clock node names to avoid warnings Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:34:40 +07:00
osc32k: clk-32k {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
};
ARM: dts: sun5i: Add Video Engine and reserved memory nodes This adds nodes for the Video Engine and the associated reserved memory for sun5i-based platforms. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-07 05:24:39 +07:00
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
ARM: dts: sunxi: Remove the CMA node label There's no phandle pointing to the CMA pool, so it's label is unnecessary. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 21:30:17 +07:00
default-pool {
ARM: dts: sun5i: Add Video Engine and reserved memory nodes This adds nodes for the Video Engine and the associated reserved memory for sun5i-based platforms. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-07 05:24:39 +07:00
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x4a000000 0x6000000>;
reusable;
linux,cma-default;
};
};
ARM: dts: sun5i: Remove SoC node unit-name to avoid warnings Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-09-07 21:42:42 +07:00
soc {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 19:32:11 +07:00
dma-ranges;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
ranges;
ARM: dts: sun5i: Use most-qualified system control compatibles This switches the sun5i dtsi to use the most qualified compatibles for the system-control block (previously named SRAM controller) as well as the SRAM blocks. The node name for system control is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> [Maxime: Removed the A10 compatible for the driver] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-10 15:01:01 +07:00
system-control@1c00000 {
compatible = "allwinner,sun5i-a13-system-control";
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 21:53:44 +07:00
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
sram_a: sram@0 {
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 21:53:44 +07:00
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
ARM: dts: sun5i: Fix the SRAM A3-A4 declaration According to the system control bindings, the A3-A4 SRAM node should be a child node of the SRAM it belongs to. However, it was introduced at the same level, therefore breaking the binding. Fix this. Fixes: 85870196258f ("ARM: sun5i: a13: Merge common controllers into the common DTSI") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-11 16:25:08 +07:00
emac_sram: sram-section@8000 {
compatible = "allwinner,sun5i-a13-sram-a3-a4",
"allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
sram_d: sram@10000 {
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 21:53:44 +07:00
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
otg_sram: sram-section@0 {
ARM: dts: sun5i: Use most-qualified system control compatibles This switches the sun5i dtsi to use the most qualified compatibles for the system-control block (previously named SRAM controller) as well as the SRAM blocks. The node name for system control is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> [Maxime: Removed the A10 compatible for the driver] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-10 15:01:01 +07:00
compatible = "allwinner,sun5i-a13-sram-d",
"allwinner,sun4i-a10-sram-d";
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 21:53:44 +07:00
reg = <0x0000 0x1000>;
status = "disabled";
};
};
ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controller This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for sun5i-based platforms. The region is shared between the Video Engine and the CPU. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> [Maxime: Fixed the SRAM C size to take the C2 and C3 SRAM into account] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-10 15:01:03 +07:00
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun5i-a13-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 21:53:44 +07:00
};
ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 19:32:11 +07:00
mbus: dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
ARM: dts: sunxi: Use macros for references to CCU clocks A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06 15:59:33 +07:00
clocks = <&ccu CLK_MBUS>;
ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 19:32:11 +07:00
dma-ranges = <0x00000000 0x40000000 0x20000000>;
#interconnect-cells = <1>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
dma: dma-controller@1c02000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_DMA>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#dma-cells = <2>;
};
ARM: dts: sunxi: Conform to DT spec for NAND controller The NAND controller node name should be nand-controller and not nand as we used previously according to the devicetree specification. Let's fix our DTs. Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-02 04:13:55 +07:00
nfc: nand-controller@1c03000 {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
dma-names = "rxtx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
spi0: spi@1c05000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
<&dma SUN4I_DMA_DEDICATED 26>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
spi1: spi@1c06000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
<&dma SUN4I_DMA_DEDICATED 8>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
tve0: tv-encoder@1c0a000 {
ARM: sun5i: r8: Merge common controllers into the common DTSI Some controllers found in the R8 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>;
clocks = <&ccu CLK_AHB_TVE>;
resets = <&ccu RST_TVE>;
status = "disabled";
port {
ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-15 03:16:26 +07:00
tve0_in_tcon0: endpoint {
ARM: sun5i: r8: Merge common controllers into the common DTSI Some controllers found in the R8 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
remote-endpoint = <&tcon0_out_tve0>;
};
};
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
emac: ethernet@1c0b000 {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
clocks = <&ccu CLK_AHB_EMAC>;
allwinner,sram = <&emac_sram 1>;
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
mdio: mdio@1c0b080 {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
tcon0: lcd-controller@1c0c000 {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
ARM: dts: sunxi: Add missing dmas properties to TCON The TCON binding mandates a dmas phandle to the DMAengine channel used for that controller. However, since it's not used in the driver, some device trees have been missing it. Let's add it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-19 16:15:37 +07:00
dmas = <&dma SUN4I_DMA_DEDICATED 14>;
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
resets = <&ccu RST_LCD>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB_LCD>,
<&ccu CLK_TCON_CH0>,
<&ccu CLK_TCON_CH1>;
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon-pixel-clock";
ARM: dts: sunxi: Fix the TCON output clock Even though we shouldn't really have any external user of the clock provided by the TCON, if clock-output-names is set, then #clock-cells must be there as well. Fix this. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25 20:52:41 +07:00
#clock-cells = <0>;
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
reg = <0>;
ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-15 03:16:26 +07:00
tcon0_in_be0: endpoint {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
remote-endpoint = <&be0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
ARM: sun5i: r8: Merge common controllers into the common DTSI Some controllers found in the R8 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
tcon0_out_tve0: endpoint@1 {
reg = <1>;
remote-endpoint = <&tve0_in_tcon0>;
ARM: sun5i: a10s: Add the HDMI controller node The A10s has an HDMI controller connected to the second TCON channel. Add it to our DT. Since the TV Encoder was the only channel 1 user so far, also add the property now that we have several users. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Replaced CLK_PLL_VIDEO[01]_2X with raw numbers for now Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-05-17 14:40:49 +07:00
allwinner,tcon-channel = <1>;
ARM: sun5i: r8: Merge common controllers into the common DTSI Some controllers found in the R8 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
};
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
};
};
};
ARM: dts: sun5i: Add Video Engine and reserved memory nodes This adds nodes for the Video Engine and the associated reserved memory for sun5i-based platforms. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-07 05:24:39 +07:00
video-codec@1c0e000 {
compatible = "allwinner,sun5i-a13-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <53>;
allwinner,sram = <&ve_sram 1>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
mmc0: mmc@1c0f000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
interrupts = <32>;
ARM: dts: sun5i: Provide default muxing for relevant controllers The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-21 04:03:28 +07:00
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 22:27:09 +07:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
mmc1: mmc@1c10000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
interrupts = <33>;
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 22:27:09 +07:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
mmc2: mmc@1c11000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
interrupts = <34>;
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 22:27:09 +07:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
usb_otg: usb@1c13000 {
ARM: dts: sun5i: Add USB Dual Role Controller Add a node for the otg/drc usb controller to sun5i-a1*.dtsi. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-17 01:35:36 +07:00
compatible = "allwinner,sun4i-a10-musb";
reg = <0x01c13000 0x0400>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_OTG>;
ARM: dts: sun5i: Add USB Dual Role Controller Add a node for the otg/drc usb controller to sun5i-a1*.dtsi. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-17 01:35:36 +07:00
interrupts = <38>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
ARM: dts: sunxi: Add default dr_mode The USB OTG binding we have mandates to have a dr_mode property, yet not all boards are setting it. Since the generic otg binding states that the default mode should be the OTG mode, let's use that one in our DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25 20:52:53 +07:00
dr_mode = "otg";
ARM: dts: sun5i: Add USB Dual Role Controller Add a node for the otg/drc usb controller to sun5i-a1*.dtsi. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-17 01:35:36 +07:00
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
usbphy: phy@1c13400 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
ARM: sunxi: dts: Split USB PHY cells into an array Even though it doesn't make any difference at the binary level, the reg property is an array of cells, and should be represented as such. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-25 20:52:43 +07:00
reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reg-names = "phy_ctrl", "pmu1";
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_USB_PHY0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clock-names = "usb_phy";
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reset-names = "usb0_reset", "usb1_reset";
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
ehci0: usb@1c14000 {
ARM: dts: sun5i: Stop using different compatibles for ehci/ohci on a13 vs a10s The A13 and the A10s use the same die (this has been confirmed by Allwinner), as such there is no need to differentiate between the ehci/ohci parts of both, the only reasons there were different allwinner,sun5i-a*-foo compatible between these 2 parts is costemetically and because we could when we still had 2 completely different dtsi files. The allwinner,sun5i-a*-foo compatible strings are not used for binding at all, the actual driver binds to the generic-?hci compatible, so we can safely remove this cosmetical difference and simplify the dtsi files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-08 02:01:19 +07:00
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reg = <0x01c14000 0x100>;
interrupts = <39>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_EHCI>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
phys = <&usbphy 1>;
ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCI This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-02 18:26:50 +07:00
phy-names = "usb";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
ohci0: usb@1c14400 {
ARM: dts: sun5i: Stop using different compatibles for ehci/ohci on a13 vs a10s The A13 and the A10s use the same die (this has been confirmed by Allwinner), as such there is no need to differentiate between the ehci/ohci parts of both, the only reasons there were different allwinner,sun5i-a*-foo compatible between these 2 parts is costemetically and because we could when we still had 2 completely different dtsi files. The allwinner,sun5i-a*-foo compatible strings are not used for binding at all, the actual driver binds to the generic-?hci compatible, so we can safely remove this cosmetical difference and simplify the dtsi files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-08 02:01:19 +07:00
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reg = <0x01c14400 0x100>;
interrupts = <40>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
phys = <&usbphy 1>;
ARM: dts: sunxi: Revert phy-names removal for ECHI and OHCI This reverts commits 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI"), 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") and 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI"). It turns out that while the USB bindings were not mentionning it, the PHY client bindings were mandating that phy-names is set when phys is. Let's add it back. Fixes: 3d109bdca981 ("ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI") Fixes: 0a3df8bb6dad ("ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI") Fixes: 3c7ab90aaa28 ("arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCI") Reported-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20191002112651.100504-1-mripard@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-02 18:26:50 +07:00
phy-names = "usb";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
crypto: crypto-engine@1c15000 {
ARM: sun5i: add a cryptographic engine node Add a node for the cryptographic engine that can be found on sun5i SoCs. This cryptographic engine is compatible with the Allwinner cryptographic accelerator driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-02 02:39:04 +07:00
compatible = "allwinner,sun5i-a13-crypto",
"allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <54>;
clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
spi2: spi@1c17000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
<&dma SUN4I_DMA_DEDICATED 28>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
ccu: clock@1c20000 {
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
intc: interrupt-controller@1c20400 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
pio: pinctrl@1c20800 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reg = <0x01c20800 0x400>;
interrupts = <28>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
ARM: sunxi: Add the missing clocks to the pinctrl nodes The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-19 16:15:27 +07:00
clock-names = "apb", "hosc", "losc";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
gpio-controller;
interrupt-controller;
ARM: sunxi: dt: Convert users to the PIO interrupts binding The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-17 16:44:24 +07:00
#interrupt-cells = <3>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
#gpio-cells = <3>;
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:31:19 +07:00
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
emac_pd_pins: emac-pd-pins {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
"PD21", "PD22", "PD23", "PD24",
"PD25", "PD26", "PD27";
function = "emac";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
i2c0_pins: i2c0-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PB0", "PB1";
function = "i2c0";
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:31:19 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
i2c1_pins: i2c1-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PB15", "PB16";
function = "i2c1";
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:31:19 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
i2c2_pins: i2c2-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PB17", "PB18";
function = "i2c2";
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:31:19 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
ir0_rx_pin: ir0-rx-pin {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PB4";
function = "ir0";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
lcd_rgb565_pins: lcd-rgb565-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
ARM: sun5i: Add RGB 565 LCD pins Some boards use the LCD in RGB565. Enable the pin muxing option. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-02-26 08:15:30 +07:00
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
function = "lcd0";
ARM: sun5i: Add RGB 565 LCD pins Some boards use the LCD in RGB565. Enable the pin muxing option. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-02-26 08:15:30 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
lcd_rgb666_pins: lcd-rgb666-pins {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
function = "lcd0";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
mmc0_pins: mmc0-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
ARM: dts: sunxi: Explicitly enable pull-ups for MMC pins In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-17 16:34:38 +07:00
bias-pull-up;
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:31:19 +07:00
};
ARM: dts: sun5i: Add mmc2 pinmux settings Add A13 mmc2 pinmux settings, note these are for a 8bit bus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-08 02:01:20 +07:00
ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16 15:57:44 +07:00
mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PC6", "PC7", "PC8", "PC9",
ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16 15:57:44 +07:00
"PC10", "PC11";
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
ARM: dts: sun5i: Add mmc2 pinmux settings Add A13 mmc2 pinmux settings, note these are for a 8bit bus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-08 02:01:20 +07:00
};
ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI The uart3 pins are shared between the A10s and A13, move the pinctrl node to the common DTSI to avoid duplication. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-06-22 16:56:09 +07:00
ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16 15:57:44 +07:00
mmc2_8bit_pins: mmc2-8bit-pins {
ARM: dts: sun5i: add a pinctrl node for 4bit mmc2 Some board only use 4bit mode of mmc2. Add a pinctrl node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-12-22 03:02:34 +07:00
pins = "PC6", "PC7", "PC8", "PC9",
ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16 15:57:44 +07:00
"PC10", "PC11", "PC12", "PC13",
"PC14", "PC15";
ARM: dts: sun5i: add a pinctrl node for 4bit mmc2 Some board only use 4bit mode of mmc2. Add a pinctrl node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-12-22 03:02:34 +07:00
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
nand_pins: nand-pins {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PC0", "PC1", "PC2",
"PC5", "PC8", "PC9", "PC10",
"PC11", "PC12", "PC13", "PC14",
"PC15";
function = "nand0";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
nand_cs0_pin: nand-cs0-pin {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PC4";
function = "nand0";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
nand_rb0_pin: nand-rb0-pin {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PC6";
function = "nand0";
};
ARM: dts: sun5i: Reorder pinctrl nodes We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16 15:57:44 +07:00
pwm0_pin: pwm0-pin {
pins = "PB2";
function = "pwm";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
spi2_pe_pins: spi2-pe-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PE1", "PE2", "PE3";
function = "spi2";
ARM: sun5i: Add SPI2 pins All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-07-19 01:51:30 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
spi2_cs0_pe_pin: spi2-cs0-pe-pin {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PE0";
function = "spi2";
ARM: sun5i: Add SPI2 pins All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-07-19 01:51:30 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart1_pe_pins: uart1-pe-pins {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PE10", "PE11";
function = "uart1";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart1_pg_pins: uart1-pg-pins {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
pins = "PG3", "PG4";
function = "uart1";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart2_pd_pins: uart2-pd-pins {
ARM: sun5i: Add UART2 pin group There's one UART2 pin group that can be used across all sun5i SoCs. However, the A10s already has one pin group for that controller. Change the index of the one in the A10s DTSI, and add the common one to sun5i.dtsi Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-05 23:55:01 +07:00
pins = "PD2", "PD3";
function = "uart2";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
ARM: sun5i: Add UART2 pin group There's one UART2 pin group that can be used across all sun5i SoCs. However, the A10s already has one pin group for that controller. Change the index of the one in the A10s DTSI, and add the common one to sun5i.dtsi Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-05 23:55:01 +07:00
pins = "PD4", "PD5";
function = "uart2";
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart3_pg_pins: uart3-pg-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PG9", "PG10";
function = "uart3";
ARM: sun5i: dt: Add UART3 CTS and RTS pins Add a separate pinctrl node for the UART3 CTS and RTS pins shared between the A10s and A13. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-06-22 17:00:30 +07:00
};
ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-07 16:58:01 +07:00
uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
ARM: sunxi: Convert pinctrl nodes to generic bindings Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23 18:28:10 +07:00
pins = "PG11", "PG12";
function = "uart3";
ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI The uart3 pins are shared between the A10s and A13, move the pinctrl node to the common DTSI to avoid duplication. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-06-22 16:56:09 +07:00
};
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
timer@1c20c00 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
ARM: dts: sun5i: Add missing timers interrupts The timer unit in the sun5i die has 6 interrupts available. List all of them. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22 15:12:24 +07:00
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_HOSC>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
wdt: watchdog@1c20c90 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
ARM: dts: sunxi: Add missing watchdog interrupts The watchdog has an interrupt on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-21 21:38:34 +07:00
interrupts = <24>;
ARM: dts: sunxi: Add missing watchdog clocks The watchdog has a clock on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-21 21:38:35 +07:00
clocks = <&osc24M>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
ir0: ir@1c21800 {
ARM: sun5i: gr8: Use common sun5i DTSI Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun4i-a10-ir";
clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
clock-names = "apb", "ir";
interrupts = <5>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
lradc: lradc@1c22800 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
codec: codec@1c22c00 {
ARM: sun5i: Add the Audio codec DT node The A13 and A10s also have the audio codec present. List it in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2015-07-27 21:50:21 +07:00
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-codec";
reg = <0x01c22c00 0x40>;
interrupts = <30>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
ARM: sun5i: Add the Audio codec DT node The A13 and A10s also have the audio codec present. List it in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2015-07-27 21:50:21 +07:00
clock-names = "apb", "codec";
dmas = <&dma SUN4I_DMA_NORMAL 19>,
<&dma SUN4I_DMA_NORMAL 19>;
dma-names = "rx", "tx";
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
sid: eeprom@1c23800 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
rtp: rtp@1c25000 {
ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and later The touchscreen controller in the A13 and later has a different temperature curve than the one in the original A10, change the compatible for the A13 and later so that the kernel will use the correct curve. Reported-by: Tong Zhang <lovewilliam@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-09 03:53:42 +07:00
compatible = "allwinner,sun5i-a13-ts";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
reg = <0x01c25000 0x100>;
interrupts = <29>;
#thermal-sensor-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
uart0: serial@1c28000 {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_APB1_UART0>;
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
uart1: serial@1c28400 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB1_UART1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
uart2: serial@1c28800 {
ARM: sun5i: a10s: Merge common controllers into the common DTSI Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_APB1_UART2>;
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
uart3: serial@1c28c00 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB1_UART3>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
i2c0: i2c@1c2ac00 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB1_I2C0>;
ARM: dts: sun5i: Provide default muxing for relevant controllers The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-21 04:03:28 +07:00
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
i2c1: i2c@1c2b000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB1_I2C1>;
ARM: dts: sun5i: Provide default muxing for relevant controllers The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-21 04:03:28 +07:00
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
i2c2: i2c@1c2b400 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_APB1_I2C2>;
ARM: dts: sun5i: Provide default muxing for relevant controllers The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2018-11-21 04:03:28 +07:00
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
timer@1c60000 {
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <82>, <83>;
ARM: sun5i: Convert to CCU Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-10-16 03:36:19 +07:00
clocks = <&ccu CLK_AHB_HSTIMER>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
fe0: display-frontend@1e00000 {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun5i-a13-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <47>;
clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
<&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_FE>;
ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 19:32:11 +07:00
interconnects = <&mbus 19>;
interconnect-names = "dma-mem";
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
reg = <1>;
ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-15 03:16:26 +07:00
fe0_out_be0: endpoint {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
arm: dts: fix unit-address leading 0s Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-14 00:54:51 +07:00
be0: display-backend@1e60000 {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
compatible = "allwinner,sun5i-a13-display-backend";
reg = <0x01e60000 0x10000>;
ARM: dts: sun5i: Add interrupt for display backend The display backend on sun5i shares the same interrupt line as the display frontend. Add it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-27 21:38:47 +07:00
interrupts = <47>;
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_BE>;
ARM: dts: sun5i: Add the MBUS controller The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03 19:32:11 +07:00
interconnects = <&mbus 18>;
interconnect-names = "dma-mem";
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
reg = <0>;
ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-15 03:16:26 +07:00
be0_in_fe0: endpoint {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
reg = <1>;
ARM: dts: sun5i: Fix display pipeline endpoint warnings in DTC Since most of the display IPs have a single endpoint, having a reg property, a unit-address and #address-cells and #size-cells will emit a warning. Let's remove those. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-15 03:16:26 +07:00
be0_out_tcon0: endpoint {
ARM: sun5i: a13: Merge common controllers into the common DTSI Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-03 22:01:27 +07:00
remote-endpoint = <&tcon0_in_be0>;
};
};
};
};
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 22:30:48 +07:00
};
};
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