linux_dsm_epyc7002/arch/arm/mach-exynos/include/mach/regs-clock.h

/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 - Clock register definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__

#include <plat/cpu.h>
#include <mach/map.h>

#define EXYNOS_CLKREG(x)			(S5P_VA_CMU + (x))

#define EXYNOS4_CLKDIV_LEFTBUS			EXYNOS_CLKREG(0x04500)
#define EXYNOS4_CLKDIV_STAT_LEFTBUS		EXYNOS_CLKREG(0x04600)
#define EXYNOS4_CLKGATE_IP_LEFTBUS		EXYNOS_CLKREG(0x04800)

#define EXYNOS4_CLKDIV_RIGHTBUS			EXYNOS_CLKREG(0x08500)
#define EXYNOS4_CLKDIV_STAT_RIGHTBUS		EXYNOS_CLKREG(0x08600)
#define EXYNOS4_CLKGATE_IP_RIGHTBUS		EXYNOS_CLKREG(0x08800)

#define EXYNOS4_EPLL_LOCK			EXYNOS_CLKREG(0x0C010)
#define EXYNOS4_VPLL_LOCK			EXYNOS_CLKREG(0x0C020)

#define EXYNOS4_EPLL_CON0			EXYNOS_CLKREG(0x0C110)
#define EXYNOS4_EPLL_CON1			EXYNOS_CLKREG(0x0C114)
#define EXYNOS4_VPLL_CON0			EXYNOS_CLKREG(0x0C120)
#define EXYNOS4_VPLL_CON1			EXYNOS_CLKREG(0x0C124)

#define EXYNOS4_CLKSRC_TOP0			EXYNOS_CLKREG(0x0C210)
#define EXYNOS4_CLKSRC_TOP1			EXYNOS_CLKREG(0x0C214)
#define EXYNOS4_CLKSRC_CAM			EXYNOS_CLKREG(0x0C220)
#define EXYNOS4_CLKSRC_TV			EXYNOS_CLKREG(0x0C224)
#define EXYNOS4_CLKSRC_MFC			EXYNOS_CLKREG(0x0C228)
#define EXYNOS4_CLKSRC_G3D			EXYNOS_CLKREG(0x0C22C)
#define EXYNOS4_CLKSRC_IMAGE			EXYNOS_CLKREG(0x0C230)
#define EXYNOS4_CLKSRC_LCD0			EXYNOS_CLKREG(0x0C234)
#define EXYNOS4_CLKSRC_MAUDIO			EXYNOS_CLKREG(0x0C23C)
#define EXYNOS4_CLKSRC_FSYS			EXYNOS_CLKREG(0x0C240)
#define EXYNOS4_CLKSRC_PERIL0			EXYNOS_CLKREG(0x0C250)
#define EXYNOS4_CLKSRC_PERIL1			EXYNOS_CLKREG(0x0C254)

#define EXYNOS4_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x0C310)
#define EXYNOS4_CLKSRC_MASK_CAM			EXYNOS_CLKREG(0x0C320)
#define EXYNOS4_CLKSRC_MASK_TV			EXYNOS_CLKREG(0x0C324)
#define EXYNOS4_CLKSRC_MASK_LCD0		EXYNOS_CLKREG(0x0C334)
#define EXYNOS4_CLKSRC_MASK_MAUDIO		EXYNOS_CLKREG(0x0C33C)
#define EXYNOS4_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x0C340)
#define EXYNOS4_CLKSRC_MASK_PERIL0		EXYNOS_CLKREG(0x0C350)
#define EXYNOS4_CLKSRC_MASK_PERIL1		EXYNOS_CLKREG(0x0C354)

#define EXYNOS4_CLKDIV_TOP			EXYNOS_CLKREG(0x0C510)
#define EXYNOS4_CLKDIV_CAM			EXYNOS_CLKREG(0x0C520)
#define EXYNOS4_CLKDIV_TV			EXYNOS_CLKREG(0x0C524)
#define EXYNOS4_CLKDIV_MFC			EXYNOS_CLKREG(0x0C528)
#define EXYNOS4_CLKDIV_G3D			EXYNOS_CLKREG(0x0C52C)
#define EXYNOS4_CLKDIV_IMAGE			EXYNOS_CLKREG(0x0C530)
#define EXYNOS4_CLKDIV_LCD0			EXYNOS_CLKREG(0x0C534)
#define EXYNOS4_CLKDIV_MAUDIO			EXYNOS_CLKREG(0x0C53C)
#define EXYNOS4_CLKDIV_FSYS0			EXYNOS_CLKREG(0x0C540)
#define EXYNOS4_CLKDIV_FSYS1			EXYNOS_CLKREG(0x0C544)
#define EXYNOS4_CLKDIV_FSYS2			EXYNOS_CLKREG(0x0C548)
#define EXYNOS4_CLKDIV_FSYS3			EXYNOS_CLKREG(0x0C54C)
#define EXYNOS4_CLKDIV_PERIL0			EXYNOS_CLKREG(0x0C550)
#define EXYNOS4_CLKDIV_PERIL1			EXYNOS_CLKREG(0x0C554)
#define EXYNOS4_CLKDIV_PERIL2			EXYNOS_CLKREG(0x0C558)
#define EXYNOS4_CLKDIV_PERIL3			EXYNOS_CLKREG(0x0C55C)
#define EXYNOS4_CLKDIV_PERIL4			EXYNOS_CLKREG(0x0C560)
#define EXYNOS4_CLKDIV_PERIL5			EXYNOS_CLKREG(0x0C564)
#define EXYNOS4_CLKDIV2_RATIO			EXYNOS_CLKREG(0x0C580)

#define EXYNOS4_CLKDIV_STAT_TOP			EXYNOS_CLKREG(0x0C610)

#define EXYNOS4_CLKGATE_SCLKCAM			EXYNOS_CLKREG(0x0C820)
#define EXYNOS4_CLKGATE_IP_CAM			EXYNOS_CLKREG(0x0C920)
#define EXYNOS4_CLKGATE_IP_TV			EXYNOS_CLKREG(0x0C924)
#define EXYNOS4_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x0C928)
#define EXYNOS4_CLKGATE_IP_G3D			EXYNOS_CLKREG(0x0C92C)
#define EXYNOS4_CLKGATE_IP_IMAGE		(soc_is_exynos4210() ? \
						EXYNOS_CLKREG(0x0C930) : \
						EXYNOS_CLKREG(0x04930))
#define EXYNOS4210_CLKGATE_IP_IMAGE		EXYNOS_CLKREG(0x0C930)
#define EXYNOS4212_CLKGATE_IP_IMAGE		EXYNOS_CLKREG(0x04930)
#define EXYNOS4_CLKGATE_IP_LCD0			EXYNOS_CLKREG(0x0C934)
#define EXYNOS4_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x0C940)
#define EXYNOS4_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x0C94C)
#define EXYNOS4_CLKGATE_IP_PERIL		EXYNOS_CLKREG(0x0C950)
#define EXYNOS4_CLKGATE_IP_PERIR		(soc_is_exynos4210() ? \
						EXYNOS_CLKREG(0x0C960) : \
						EXYNOS_CLKREG(0x08960))
#define EXYNOS4210_CLKGATE_IP_PERIR		EXYNOS_CLKREG(0x0C960)
#define EXYNOS4212_CLKGATE_IP_PERIR		EXYNOS_CLKREG(0x08960)
#define EXYNOS4_CLKGATE_BLOCK			EXYNOS_CLKREG(0x0C970)

#define EXYNOS4_CLKSRC_MASK_DMC			EXYNOS_CLKREG(0x10300)
#define EXYNOS4_CLKSRC_DMC			EXYNOS_CLKREG(0x10200)
#define EXYNOS4_CLKDIV_DMC0			EXYNOS_CLKREG(0x10500)
#define EXYNOS4_CLKDIV_DMC1			EXYNOS_CLKREG(0x10504)
#define EXYNOS4_CLKDIV_STAT_DMC0		EXYNOS_CLKREG(0x10600)
#define EXYNOS4_CLKGATE_IP_DMC			EXYNOS_CLKREG(0x10900)

#define EXYNOS4_APLL_LOCK			EXYNOS_CLKREG(0x14000)
#define EXYNOS4_MPLL_LOCK			(soc_is_exynos4210() ? \
						EXYNOS_CLKREG(0x14004) :  \
						EXYNOS_CLKREG(0x10008))
#define EXYNOS4_APLL_CON0			EXYNOS_CLKREG(0x14100)
#define EXYNOS4_APLL_CON1			EXYNOS_CLKREG(0x14104)
#define EXYNOS4_MPLL_CON0			(soc_is_exynos4210() ? \
						EXYNOS_CLKREG(0x14108) : \
						EXYNOS_CLKREG(0x10108))
#define EXYNOS4_MPLL_CON1			(soc_is_exynos4210() ? \
						EXYNOS_CLKREG(0x1410C) : \
						EXYNOS_CLKREG(0x1010C))

#define EXYNOS4_CLKSRC_CPU			EXYNOS_CLKREG(0x14200)
#define EXYNOS4_CLKMUX_STATCPU			EXYNOS_CLKREG(0x14400)

#define EXYNOS4_CLKDIV_CPU			EXYNOS_CLKREG(0x14500)
#define EXYNOS4_CLKDIV_CPU1			EXYNOS_CLKREG(0x14504)
#define EXYNOS4_CLKDIV_STATCPU			EXYNOS_CLKREG(0x14600)
#define EXYNOS4_CLKDIV_STATCPU1			EXYNOS_CLKREG(0x14604)

#define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
#define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)

#define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */

#define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
#define EXYNOS4_APLLCON0_LOCKED_SHIFT		(29)
#define EXYNOS4_APLL_VAL_1000			((250 << 16) | (6 << 8) | 1)
#define EXYNOS4_APLL_VAL_800			((200 << 16) | (6 << 8) | 1)

#define EXYNOS4_EPLLCON0_ENABLE_SHIFT		(31)
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT		(29)

#define EXYNOS4_VPLLCON0_ENABLE_SHIFT		(31)
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT		(29)

#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)

#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT		(0)
#define EXYNOS4_CLKDIV_CPU0_CORE_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT	(4)
#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT	(8)
#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT	(12)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT		(16)
#define EXYNOS4_CLKDIV_CPU0_ATB_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT		(24)
#define EXYNOS4_CLKDIV_CPU0_APLL_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT		28
#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)

#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT		0
#define EXYNOS4_CLKDIV_CPU1_COPY_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT		4
#define EXYNOS4_CLKDIV_CPU1_HPM_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT		8
#define EXYNOS4_CLKDIV_CPU1_CORES_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT		(0)
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT		(8)
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT		(12)
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT		(16)
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT		(20)
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT		(24)
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT	(28)
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT	(0)
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT	(4)
#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK		(0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT	(8)
#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT	(12)
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT	(16)
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)

#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT		(0)
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT		(4)
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)

/* Only for EXYNOS4210 */

#define EXYNOS4210_CLKSRC_LCD1			EXYNOS_CLKREG(0x0C238)
#define EXYNOS4210_CLKSRC_MASK_LCD1		EXYNOS_CLKREG(0x0C338)
#define EXYNOS4210_CLKDIV_LCD1			EXYNOS_CLKREG(0x0C538)
#define EXYNOS4210_CLKGATE_IP_LCD1		EXYNOS_CLKREG(0x0C938)

/* Compatibility defines and inclusion */

#include <mach/regs-pmu.h>

#define S5P_EPLL_CON				EXYNOS4_EPLL_CON0

#endif /* __ASM_ARCH_REGS_CLOCK_H */
ARM: EXYNOS4: Update Clock part This patch updates Clock part of EXYNOS4 according to the change of ARCH name, EXYNOS4. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-02-14 14:08:04 +07:00			`/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h`
ARM: S5PV310: Add Clock and PLL support This patch adds clock and pll support for S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-07-27 15:52:39 +07:00			`*`
ARM: EXYNOS4: Update Clock part This patch updates Clock part of EXYNOS4 according to the change of ARCH name, EXYNOS4. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-02-14 14:08:04 +07:00			`* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.`
			`* http://www.samsung.com`
ARM: S5PV310: Add Clock and PLL support This patch adds clock and pll support for S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-07-27 15:52:39 +07:00			`*`
ARM: EXYNOS4: Update Clock part This patch updates Clock part of EXYNOS4 according to the change of ARCH name, EXYNOS4. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-02-14 14:08:04 +07:00			`* EXYNOS4 - Clock register definitions`
ARM: S5PV310: Add Clock and PLL support This patch adds clock and pll support for S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-07-27 15:52:39 +07:00			`*`
			`* This program is free software; you can redistribute it and/or modify`
			`* it under the terms of the GNU General Public License version 2 as`
			`* published by the Free Software Foundation.`
			`*/`

			`#ifndef __ASM_ARCH_REGS_CLOCK_H`
			`#define __ASM_ARCH_REGS_CLOCK_H __FILE__`

ARM: EXYNOS4: Add support clock for EXYNOS4212 This patch splits EXYNOS4 clock code to EXYNOS4 common, EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212 SoC with one kernel image. Of course, this patch adds some clock codes for EXYNOS4212 SoC. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-08-24 15:25:09 +07:00			`#include <plat/cpu.h>`
ARM: S5PV310: Add Clock and PLL support This patch adds clock and pll support for S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-07-27 15:52:39 +07:00			`#include <mach/map.h>`

ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2012-03-10 05:19:10 +07:00			`#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))`

			`#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)`
			`#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)`
			`#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)`

			`#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)`
			`#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)`
			`#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)`

			`#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)`
			`#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)`

			`#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)`
			`#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)`
			`#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)`
			`#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)`

			`#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)`
			`#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)`
			`#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)`
			`#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)`
			`#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)`
			`#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)`
			`#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)`
			`#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)`
			`#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)`
			`#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)`
			`#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)`
			`#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)`

			`#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)`
			`#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)`
			`#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)`
			`#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)`
			`#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)`
			`#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)`
			`#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)`
			`#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)`

			`#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)`
			`#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)`
			`#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)`
			`#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)`
			`#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)`
			`#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)`
			`#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)`
			`#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)`
			`#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)`
			`#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)`
			`#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)`
			`#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)`
			`#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)`
			`#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)`
			`#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)`
			`#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)`
			`#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)`
			`#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)`
			`#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)`

			`#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)`

			`#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)`
			`#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)`
			`#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)`
			`#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)`
			`#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)`
			`#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \`
			`EXYNOS_CLKREG(0x0C930) : \`
			`EXYNOS_CLKREG(0x04930))`
			`#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)`
			`#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)`
			`#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)`
			`#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)`
			`#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)`
			`#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)`
			`#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \`
			`EXYNOS_CLKREG(0x0C960) : \`
			`EXYNOS_CLKREG(0x08960))`
			`#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)`
			`#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)`
			`#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)`

			`#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)`
			`#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)`
			`#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)`
			`#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)`
			`#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)`
			`#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)`

			`#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)`
			`#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \`
			`EXYNOS_CLKREG(0x14004) : \`
			`EXYNOS_CLKREG(0x10008))`
			`#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)`
			`#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)`
			`#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \`
			`EXYNOS_CLKREG(0x14108) : \`
			`EXYNOS_CLKREG(0x10108))`
			`#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \`
			`EXYNOS_CLKREG(0x1410C) : \`
			`EXYNOS_CLKREG(0x1010C))`

			`#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)`
			`#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)`

			`#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)`
			`#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)`
			`#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)`
			`#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)`

			`#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)`
			`#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)`

			`#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */`

			`#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)`
			`#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)`
			`#define EXYNOS4_APLL_VAL_1000 ((250 << 16) \| (6 << 8) \| 1)`
			`#define EXYNOS4_APLL_VAL_800 ((200 << 16) \| (6 << 8) \| 1)`

			`#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)`
			`#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)`

			`#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)`
			`#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)`

			`#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)`
			`#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)`

			`#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)`
			`#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)`
			`#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)`
			`#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)`
			`#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)`
			`#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)`
			`#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)`
			`#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)`
ARM: EXYNOS: add clock registers for exynos4x12-cpufreq Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2012-02-02 10:31:01 +07:00			`#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28`
			`#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)`

			`#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0`
			`#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4`
			`#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)`
			`#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8`
			`#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)`
ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2012-03-10 05:19:10 +07:00
			`#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)`
			`#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)`
			`#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)`
			`#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)`
			`#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)`
			`#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)`
			`#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)`
			`#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)`
			`#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)`
			`#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)`

			`#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)`
			`#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)`
			`#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)`
			`#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)`

			`#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)`
			`#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)`
			`#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)`
			`#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)`
ARM: S5PV310: Update CMU registers for CPUFREQ This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210 CPUFREQ driver and modifies some register names according to datasheet. Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-09-18 08:59:31 +07:00
ARM: EXYNOS4: Add support clock for EXYNOS4212 This patch splits EXYNOS4 clock code to EXYNOS4 common, EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212 SoC with one kernel image. Of course, this patch adds some clock codes for EXYNOS4212 SoC. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-08-24 15:25:09 +07:00			`/* Only for EXYNOS4210 */`

ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2012-03-10 05:19:10 +07:00			`#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)`
			`#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)`
			`#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)`
			`#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)`
ARM: EXYNOS4: Add support clock for EXYNOS4212 This patch splits EXYNOS4 clock code to EXYNOS4 common, EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212 SoC with one kernel image. Of course, this patch adds some clock codes for EXYNOS4212 SoC. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-08-24 15:25:09 +07:00
ARM: S5P: Add support for common MIPI CSIS/DSIM D-PHY control Add common code for MIPI-CSIS and MIPI-DSIM drivers to support their corresponding D-PHY's enable and reset control. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2011-03-10 19:53:40 +07:00			`/* Compatibility defines and inclusion */`

			`#include <mach/regs-pmu.h>`
ARM: S5P: Reduce duplicated EPLL control codes S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-10-14 08:39:08 +07:00
ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2012-03-10 05:19:10 +07:00			`#define S5P_EPLL_CON EXYNOS4_EPLL_CON0`
ARM: S5P: Reduce duplicated EPLL control codes S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-10-14 08:39:08 +07:00
ARM: S5PV310: Add Clock and PLL support This patch adds clock and pll support for S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> 2010-07-27 15:52:39 +07:00			`#endif /* __ASM_ARCH_REGS_CLOCK_H */`