2005-10-10 19:50:37 +07:00
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/*
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*
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* Common boot and setup code.
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*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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2013-07-25 09:12:32 +07:00
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#define DEBUG
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2005-10-10 19:50:37 +07:00
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2011-07-23 05:24:23 +07:00
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#include <linux/export.h>
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2005-10-10 19:50:37 +07:00
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/delay.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/ioport.h>
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#include <linux/console.h>
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#include <linux/utsname.h>
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#include <linux/tty.h>
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#include <linux/root_dev.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/unistd.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
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#include <linux/bootmem.h>
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2006-11-11 13:25:02 +07:00
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#include <linux/pci.h>
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2008-04-17 11:35:01 +07:00
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#include <linux/lockdep.h>
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2010-07-12 11:36:09 +07:00
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#include <linux/memblock.h>
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2011-10-10 17:50:43 +07:00
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#include <linux/hugetlb.h>
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2014-06-04 14:50:47 +07:00
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#include <linux/memory.h>
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2015-04-09 09:52:56 +07:00
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#include <linux/nmi.h>
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2011-10-10 17:50:43 +07:00
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2005-10-10 19:50:37 +07:00
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#include <asm/io.h>
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2005-12-04 14:39:37 +07:00
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#include <asm/kdump.h>
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2005-10-10 19:50:37 +07:00
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#include <asm/prom.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/elf.h>
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#include <asm/machdep.h>
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#include <asm/paca.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/btext.h>
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#include <asm/nvram.h>
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#include <asm/setup.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/serial.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/firmware.h>
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2005-10-28 19:53:37 +07:00
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#include <asm/xmon.h>
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2005-11-07 05:49:43 +07:00
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#include <asm/udbg.h>
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2005-11-11 20:06:06 +07:00
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#include <asm/kexec.h>
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2009-07-24 06:15:47 +07:00
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#include <asm/mmu_context.h>
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2011-04-06 12:18:48 +07:00
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#include <asm/code-patching.h>
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KVM: PPC: Allocate RMAs (Real Mode Areas) at boot for use by guests
This adds infrastructure which will be needed to allow book3s_hv KVM to
run on older POWER processors, including PPC970, which don't support
the Virtual Real Mode Area (VRMA) facility, but only the Real Mode
Offset (RMO) facility. These processors require a physically
contiguous, aligned area of memory for each guest. When the guest does
an access in real mode (MMU off), the address is compared against a
limit value, and if it is lower, the address is ORed with an offset
value (from the Real Mode Offset Register (RMOR)) and the result becomes
the real address for the access. The size of the RMA has to be one of
a set of supported values, which usually includes 64MB, 128MB, 256MB
and some larger powers of 2.
Since we are unlikely to be able to allocate 64MB or more of physically
contiguous memory after the kernel has been running for a while, we
allocate a pool of RMAs at boot time using the bootmem allocator. The
size and number of the RMAs can be set using the kvm_rma_size=xx and
kvm_rma_count=xx kernel command line options.
KVM exports a new capability, KVM_CAP_PPC_RMA, to signal the availability
of the pool of preallocated RMAs. The capability value is 1 if the
processor can use an RMA but doesn't require one (because it supports
the VRMA facility), or 2 if the processor requires an RMA for each guest.
This adds a new ioctl, KVM_ALLOCATE_RMA, which allocates an RMA from the
pool and returns a file descriptor which can be used to map the RMA. It
also returns the size of the RMA in the argument structure.
Having an RMA means we will get multiple KMV_SET_USER_MEMORY_REGION
ioctl calls from userspace. To cope with this, we now preallocate the
kvm->arch.ram_pginfo array when the VM is created with a size sufficient
for up to 64GB of guest memory. Subsequently we will get rid of this
array and use memory associated with each memslot instead.
This moves most of the code that translates the user addresses into
host pfns (page frame numbers) out of kvmppc_prepare_vrma up one level
to kvmppc_core_prepare_memory_region. Also, instead of having to look
up the VMA for each page in order to check the page size, we now check
that the pages we get are compound pages of 16MB. However, if we are
adding memory that is mapped to an RMA, we don't bother with calling
get_user_pages_fast and instead just offset from the base pfn for the
RMA.
Typically the RMA gets added after vcpus are created, which makes it
inconvenient to have the LPCR (logical partition control register) value
in the vcpu->arch struct, since the LPCR controls whether the processor
uses RMA or VRMA for the guest. This moves the LPCR value into the
kvm->arch struct and arranges for the MER (mediated external request)
bit, which is the only bit that varies between vcpus, to be set in
assembly code when going into the guest if there is a pending external
interrupt request.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 07:25:44 +07:00
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#include <asm/kvm_ppc.h>
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2011-10-10 17:50:43 +07:00
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#include <asm/hugetlb.h>
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2016-03-24 18:04:04 +07:00
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#include <asm/livepatch.h>
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2016-07-05 12:03:49 +07:00
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#include <asm/opal.h>
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2005-10-10 19:50:37 +07:00
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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2013-03-20 13:30:12 +07:00
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int spinning_secondaries;
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2005-10-10 19:50:37 +07:00
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u64 ppc64_pft_size;
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2005-12-09 08:40:17 +07:00
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/* Pick defaults since we might want to patch instructions
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* before we've read this from the device tree.
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*/
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struct ppc64_caches ppc64_caches = {
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2006-09-07 02:34:41 +07:00
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.dline_size = 0x40,
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.log_dline_size = 6,
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.iline_size = 0x40,
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.log_iline_size = 6
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2005-12-09 08:40:17 +07:00
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};
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2005-10-10 19:50:37 +07:00
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EXPORT_SYMBOL_GPL(ppc64_caches);
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/*
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* These are used in binfmt_elf.c to put aux entries on the stack
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* for each elf executable being started.
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*/
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int dcache_bsize;
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int icache_bsize;
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int ucache_bsize;
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2013-10-12 07:22:38 +07:00
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#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
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static void setup_tlb_core_data(void)
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{
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int cpu;
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2014-03-08 03:48:35 +07:00
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BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
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2013-10-12 07:22:38 +07:00
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for_each_possible_cpu(cpu) {
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int first = cpu_first_thread_sibling(cpu);
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2015-10-07 10:48:09 +07:00
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/*
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* If we boot via kdump on a non-primary thread,
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* make sure we point at the thread that actually
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* set up this TLB.
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*/
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if (cpu_first_thread_sibling(boot_cpuid) == first)
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first = boot_cpuid;
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2013-10-12 07:22:38 +07:00
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paca[cpu].tcd_ptr = &paca[first].tcd;
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/*
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* If we have threads, we need either tlbsrx.
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* or e6500 tablewalk mode, or else TLB handlers
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* will be racy and could produce duplicate entries.
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*/
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if (smt_enabled_at_boot >= 2 &&
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!mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
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book3e_htw_mode != PPC_HTW_E6500) {
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/* Should we panic instead? */
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WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
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__func__);
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}
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}
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}
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#else
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static void setup_tlb_core_data(void)
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{
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}
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#endif
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2005-10-10 19:50:37 +07:00
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#ifdef CONFIG_SMP
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2010-08-05 14:42:11 +07:00
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static char *smt_enabled_cmdline;
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2005-10-10 19:50:37 +07:00
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/* Look for ibm,smt-enabled OF option */
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static void check_smt_enabled(void)
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{
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struct device_node *dn;
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2006-07-12 12:35:54 +07:00
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const char *smt_option;
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2005-10-10 19:50:37 +07:00
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2010-08-05 14:42:11 +07:00
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/* Default to enabling all threads */
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smt_enabled_at_boot = threads_per_core;
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2005-10-10 19:50:37 +07:00
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2010-08-05 14:42:11 +07:00
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/* Allow the command line to overrule the OF option */
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if (smt_enabled_cmdline) {
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if (!strcmp(smt_enabled_cmdline, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_enabled_cmdline, "off"))
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smt_enabled_at_boot = 0;
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else {
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2014-08-09 04:24:01 +07:00
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int smt;
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2010-08-05 14:42:11 +07:00
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int rc;
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2014-08-09 04:24:01 +07:00
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rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
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2010-08-05 14:42:11 +07:00
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if (!rc)
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smt_enabled_at_boot =
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2014-08-09 04:24:01 +07:00
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min(threads_per_core, smt);
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2010-08-05 14:42:11 +07:00
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}
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} else {
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dn = of_find_node_by_path("/options");
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if (dn) {
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smt_option = of_get_property(dn, "ibm,smt-enabled",
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NULL);
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if (smt_option) {
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if (!strcmp(smt_option, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_option, "off"))
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smt_enabled_at_boot = 0;
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}
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of_node_put(dn);
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}
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}
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2005-10-10 19:50:37 +07:00
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}
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/* Look for smt-enabled= cmdline option */
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static int __init early_smt_enabled(char *p)
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{
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2010-08-05 14:42:11 +07:00
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smt_enabled_cmdline = p;
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2005-10-10 19:50:37 +07:00
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return 0;
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}
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early_param("smt-enabled", early_smt_enabled);
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2005-11-05 06:33:55 +07:00
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#else
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#define check_smt_enabled()
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2005-10-10 19:50:37 +07:00
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#endif /* CONFIG_SMP */
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2013-02-12 21:44:50 +07:00
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/** Fix up paca fields required for the boot cpu */
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static void fixup_boot_paca(void)
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{
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/* The boot cpu is started */
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get_paca()->cpu_start = 1;
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/* Allow percpu accesses to work until we setup percpu data */
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get_paca()->data_offset = 0;
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}
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|
2016-07-05 12:03:49 +07:00
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static void configure_exceptions(void)
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2014-03-28 09:36:30 +07:00
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{
|
2014-07-17 12:29:45 +07:00
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/*
|
2016-07-05 12:03:49 +07:00
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* Setup the trampolines from the lowmem exception vectors
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* to the kdump kernel when not using a relocatable kernel.
|
2014-07-17 12:29:45 +07:00
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*/
|
2016-07-05 12:03:49 +07:00
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setup_kdump_trampoline();
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/* Under a PAPR hypervisor, we need hypercalls */
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if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
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/* Enable AIL if possible */
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pseries_enable_reloc_on_exc();
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/*
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* Tell the hypervisor that we want our exceptions to
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* be taken in little endian mode.
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*
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* We don't call this for big endian as our calling convention
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* makes us always enter in BE, and the call may fail under
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* some circumstances with kdump.
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*/
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#ifdef __LITTLE_ENDIAN__
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pseries_little_endian_exceptions();
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#endif
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} else {
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/* Set endian mode using OPAL */
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if (firmware_has_feature(FW_FEATURE_OPAL))
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opal_configure_cores();
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/* Enable AIL if supported, and we are in hypervisor mode */
|
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if (cpu_has_feature(CPU_FTR_HVMODE) &&
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cpu_has_feature(CPU_FTR_ARCH_207S)) {
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|
unsigned long lpcr = mfspr(SPRN_LPCR);
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mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
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}
|
2014-03-28 09:36:30 +07:00
|
|
|
}
|
|
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}
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|
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|
|
2016-07-05 12:03:49 +07:00
|
|
|
static void cpu_ready_for_interrupts(void)
|
|
|
|
{
|
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|
|
/* Set IR and DR in PACA MSR */
|
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|
|
get_paca()->kernel_msr = MSR_KERNEL;
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|
}
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|
2005-10-10 19:50:37 +07:00
|
|
|
/*
|
|
|
|
* Early initialization entry point. This is called by head.S
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|
* with MMU translation disabled. We rely on the "feature" of
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|
* the CPU that ignores the top 2 bits of the address in real
|
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|
* mode so we can access kernel globals normally provided we
|
|
|
|
* only toy with things in the RMO region. From here, we do
|
2010-07-12 11:36:09 +07:00
|
|
|
* some early parsing of the device-tree to setup out MEMBLOCK
|
2005-10-10 19:50:37 +07:00
|
|
|
* data structures, and allocate & initialize the hash table
|
|
|
|
* and segment tables so we can start running with translation
|
|
|
|
* enabled.
|
|
|
|
*
|
|
|
|
* It is this function which will call the probe() callback of
|
|
|
|
* the various platform types and copy the matching one to the
|
|
|
|
* global ppc_md structure. Your platform can eventually do
|
|
|
|
* some very early initializations from the probe() routine, but
|
|
|
|
* this is not recommended, be very careful as, for example, the
|
|
|
|
* device-tree is not accessible via normal means at this point.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void __init early_setup(unsigned long dt_ptr)
|
|
|
|
{
|
2013-02-14 00:03:16 +07:00
|
|
|
static __initdata struct paca_struct boot_paca;
|
|
|
|
|
2008-05-07 07:00:56 +07:00
|
|
|
/* -------- printk is _NOT_ safe to use here ! ------- */
|
|
|
|
|
2006-10-24 13:42:40 +07:00
|
|
|
/* Identify CPU type */
|
2006-11-10 16:38:53 +07:00
|
|
|
identify_cpu(0, mfspr(SPRN_PVR));
|
2006-10-24 13:42:40 +07:00
|
|
|
|
2006-06-28 10:18:53 +07:00
|
|
|
/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
|
2010-01-28 20:23:22 +07:00
|
|
|
initialise_paca(&boot_paca, 0);
|
|
|
|
setup_paca(&boot_paca);
|
2013-02-12 21:44:50 +07:00
|
|
|
fixup_boot_paca();
|
2006-06-28 10:18:53 +07:00
|
|
|
|
2008-05-07 07:00:56 +07:00
|
|
|
/* -------- printk is now safe to use ------- */
|
|
|
|
|
2008-05-07 07:25:34 +07:00
|
|
|
/* Enable early debugging if any specified (see udbg.h) */
|
|
|
|
udbg_early_init();
|
|
|
|
|
2006-03-28 19:15:54 +07:00
|
|
|
DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
|
2005-10-10 19:50:37 +07:00
|
|
|
|
|
|
|
/*
|
2007-09-07 00:47:29 +07:00
|
|
|
* Do early initialization using the flattened device
|
|
|
|
* tree, such as retrieving the physical memory map or
|
|
|
|
* calculating/retrieving the hash table size.
|
2005-10-10 19:50:37 +07:00
|
|
|
*/
|
|
|
|
early_init_devtree(__va(dt_ptr));
|
|
|
|
|
2006-03-25 13:25:17 +07:00
|
|
|
/* Now we know the logical id of our boot cpu, setup the paca. */
|
2010-01-28 20:23:22 +07:00
|
|
|
setup_paca(&paca[boot_cpuid]);
|
2013-02-12 21:44:50 +07:00
|
|
|
fixup_boot_paca();
|
2006-03-25 13:25:17 +07:00
|
|
|
|
2016-07-05 12:03:46 +07:00
|
|
|
/*
|
2016-07-05 12:03:49 +07:00
|
|
|
* Configure exception handlers. This include setting up trampolines
|
|
|
|
* if needed, setting exception endian mode, etc...
|
2016-07-05 12:03:46 +07:00
|
|
|
*/
|
2016-07-05 12:03:49 +07:00
|
|
|
configure_exceptions();
|
2005-12-04 14:39:37 +07:00
|
|
|
|
2009-03-20 02:34:16 +07:00
|
|
|
/* Initialize the hash table or TLB handling */
|
|
|
|
early_init_mmu();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2016-07-05 12:03:42 +07:00
|
|
|
/* Apply all the dynamic patching */
|
|
|
|
apply_feature_fixups();
|
|
|
|
|
2014-03-28 09:36:29 +07:00
|
|
|
/*
|
|
|
|
* At this point, we can let interrupts switch to virtual mode
|
|
|
|
* (the MMU has been setup), so adjust the MSR in the PACA to
|
2014-03-28 09:36:30 +07:00
|
|
|
* have IR and DR set and enable AIL if it exists
|
2014-03-28 09:36:29 +07:00
|
|
|
*/
|
2014-03-28 09:36:30 +07:00
|
|
|
cpu_ready_for_interrupts();
|
2014-03-28 09:36:29 +07:00
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
DBG(" <- early_setup()\n");
|
2013-07-25 09:12:32 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
|
|
|
|
/*
|
|
|
|
* This needs to be done *last* (after the above DBG() even)
|
|
|
|
*
|
|
|
|
* Right after we return from this function, we turn on the MMU
|
|
|
|
* which means the real-mode access trick that btext does will
|
|
|
|
* no longer work, it needs to switch to using a real MMU
|
|
|
|
* mapping. This call will ensure that it does
|
|
|
|
*/
|
|
|
|
btext_map();
|
|
|
|
#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
|
2005-10-10 19:50:37 +07:00
|
|
|
}
|
|
|
|
|
2005-11-10 09:37:51 +07:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
void early_setup_secondary(void)
|
|
|
|
{
|
2016-03-04 12:01:48 +07:00
|
|
|
/* Mark interrupts disabled in PACA */
|
2009-03-20 02:34:16 +07:00
|
|
|
get_paca()->soft_enabled = 0;
|
2005-11-10 09:37:51 +07:00
|
|
|
|
2009-03-20 02:34:16 +07:00
|
|
|
/* Initialize the hash table or TLB handling */
|
|
|
|
early_init_mmu_secondary();
|
2014-03-28 09:36:29 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* At this point, we can let interrupts switch to virtual mode
|
|
|
|
* (the MMU has been setup), so adjust the MSR in the PACA to
|
|
|
|
* have IR and DR set.
|
|
|
|
*/
|
2014-03-28 09:36:30 +07:00
|
|
|
cpu_ready_for_interrupts();
|
2005-11-10 09:37:51 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_SMP */
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2005-11-04 08:09:42 +07:00
|
|
|
#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
|
2015-10-07 10:48:19 +07:00
|
|
|
static bool use_spinloop(void)
|
|
|
|
{
|
|
|
|
if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When book3e boots from kexec, the ePAPR spin table does
|
|
|
|
* not get used.
|
|
|
|
*/
|
|
|
|
return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
|
|
|
|
}
|
|
|
|
|
2005-11-04 08:09:42 +07:00
|
|
|
void smp_release_cpus(void)
|
|
|
|
{
|
2005-12-06 04:49:00 +07:00
|
|
|
unsigned long *ptr;
|
2011-03-16 10:54:35 +07:00
|
|
|
int i;
|
2005-11-04 08:09:42 +07:00
|
|
|
|
2015-10-07 10:48:19 +07:00
|
|
|
if (!use_spinloop())
|
|
|
|
return;
|
|
|
|
|
2005-11-04 08:09:42 +07:00
|
|
|
DBG(" -> smp_release_cpus()\n");
|
|
|
|
|
|
|
|
/* All secondary cpus are spinning on a common spinloop, release them
|
|
|
|
* all now so they can start to spin on their individual paca
|
|
|
|
* spinloops. For non SMP kernels, the secondary cpus never get out
|
|
|
|
* of the common spinloop.
|
2008-08-30 08:40:24 +07:00
|
|
|
*/
|
2005-11-04 08:09:42 +07:00
|
|
|
|
2005-12-06 04:49:00 +07:00
|
|
|
ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
|
|
|
|
- PHYSICAL_START);
|
2014-03-11 07:54:06 +07:00
|
|
|
*ptr = ppc_function_entry(generic_secondary_smp_init);
|
2011-03-16 10:54:35 +07:00
|
|
|
|
|
|
|
/* And wait a bit for them to catch up */
|
|
|
|
for (i = 0; i < 100000; i++) {
|
|
|
|
mb();
|
|
|
|
HMT_low();
|
2011-05-26 01:09:12 +07:00
|
|
|
if (spinning_secondaries == 0)
|
2011-03-16 10:54:35 +07:00
|
|
|
break;
|
|
|
|
udelay(1);
|
|
|
|
}
|
2011-05-26 01:09:12 +07:00
|
|
|
DBG("spinning_secondaries = %d\n", spinning_secondaries);
|
2005-11-04 08:09:42 +07:00
|
|
|
|
|
|
|
DBG(" <- smp_release_cpus()\n");
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_SMP || CONFIG_KEXEC */
|
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
/*
|
2005-11-10 09:37:51 +07:00
|
|
|
* Initialize some remaining members of the ppc64_caches and systemcfg
|
|
|
|
* structures
|
2005-10-10 19:50:37 +07:00
|
|
|
* (at least until we get rid of them completely). This is mostly some
|
|
|
|
* cache informations about the CPU that will be used by cache flush
|
|
|
|
* routines and/or provided to userland
|
|
|
|
*/
|
|
|
|
static void __init initialize_cache_info(void)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
unsigned long num_cpus = 0;
|
|
|
|
|
|
|
|
DBG(" -> initialize_cache_info()\n");
|
|
|
|
|
2011-08-11 03:44:22 +07:00
|
|
|
for_each_node_by_type(np, "cpu") {
|
2005-10-10 19:50:37 +07:00
|
|
|
num_cpus += 1;
|
|
|
|
|
2011-08-11 03:44:23 +07:00
|
|
|
/*
|
|
|
|
* We're assuming *all* of the CPUs have the same
|
2005-10-10 19:50:37 +07:00
|
|
|
* d-cache and i-cache sizes... -Peter
|
|
|
|
*/
|
2011-08-11 03:44:23 +07:00
|
|
|
if (num_cpus == 1) {
|
2013-08-06 23:01:30 +07:00
|
|
|
const __be32 *sizep, *lsizep;
|
2005-10-10 19:50:37 +07:00
|
|
|
u32 size, lsize;
|
|
|
|
|
|
|
|
size = 0;
|
|
|
|
lsize = cur_cpu_spec->dcache_bsize;
|
2007-04-03 19:26:41 +07:00
|
|
|
sizep = of_get_property(np, "d-cache-size", NULL);
|
2005-10-10 19:50:37 +07:00
|
|
|
if (sizep != NULL)
|
2013-08-06 23:01:30 +07:00
|
|
|
size = be32_to_cpu(*sizep);
|
2011-08-11 03:44:23 +07:00
|
|
|
lsizep = of_get_property(np, "d-cache-block-size",
|
|
|
|
NULL);
|
2007-10-28 04:49:28 +07:00
|
|
|
/* fallback if block size missing */
|
|
|
|
if (lsizep == NULL)
|
2011-08-11 03:44:23 +07:00
|
|
|
lsizep = of_get_property(np,
|
|
|
|
"d-cache-line-size",
|
|
|
|
NULL);
|
2005-10-10 19:50:37 +07:00
|
|
|
if (lsizep != NULL)
|
2013-08-06 23:01:30 +07:00
|
|
|
lsize = be32_to_cpu(*lsizep);
|
2013-08-06 23:01:24 +07:00
|
|
|
if (sizep == NULL || lsizep == NULL)
|
2005-10-10 19:50:37 +07:00
|
|
|
DBG("Argh, can't find dcache properties ! "
|
|
|
|
"sizep: %p, lsizep: %p\n", sizep, lsizep);
|
|
|
|
|
2005-11-11 17:15:21 +07:00
|
|
|
ppc64_caches.dsize = size;
|
|
|
|
ppc64_caches.dline_size = lsize;
|
2005-10-10 19:50:37 +07:00
|
|
|
ppc64_caches.log_dline_size = __ilog2(lsize);
|
|
|
|
ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
|
|
|
|
|
|
|
|
size = 0;
|
|
|
|
lsize = cur_cpu_spec->icache_bsize;
|
2007-04-03 19:26:41 +07:00
|
|
|
sizep = of_get_property(np, "i-cache-size", NULL);
|
2005-10-10 19:50:37 +07:00
|
|
|
if (sizep != NULL)
|
2013-08-06 23:01:30 +07:00
|
|
|
size = be32_to_cpu(*sizep);
|
2011-08-11 03:44:23 +07:00
|
|
|
lsizep = of_get_property(np, "i-cache-block-size",
|
|
|
|
NULL);
|
2007-10-28 04:49:28 +07:00
|
|
|
if (lsizep == NULL)
|
2011-08-11 03:44:23 +07:00
|
|
|
lsizep = of_get_property(np,
|
|
|
|
"i-cache-line-size",
|
|
|
|
NULL);
|
2005-10-10 19:50:37 +07:00
|
|
|
if (lsizep != NULL)
|
2013-08-06 23:01:30 +07:00
|
|
|
lsize = be32_to_cpu(*lsizep);
|
2013-08-06 23:01:24 +07:00
|
|
|
if (sizep == NULL || lsizep == NULL)
|
2005-10-10 19:50:37 +07:00
|
|
|
DBG("Argh, can't find icache properties ! "
|
|
|
|
"sizep: %p, lsizep: %p\n", sizep, lsizep);
|
|
|
|
|
2005-11-11 17:15:21 +07:00
|
|
|
ppc64_caches.isize = size;
|
|
|
|
ppc64_caches.iline_size = lsize;
|
2005-10-10 19:50:37 +07:00
|
|
|
ppc64_caches.log_iline_size = __ilog2(lsize);
|
|
|
|
ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG(" <- initialize_cache_info()\n");
|
|
|
|
}
|
|
|
|
|
2016-07-05 12:04:07 +07:00
|
|
|
static __init void print_system_info(void)
|
|
|
|
{
|
|
|
|
pr_info("-----------------------------------------------------\n");
|
|
|
|
pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
|
|
|
|
pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
|
|
|
|
|
|
|
|
if (ppc64_caches.dline_size != 0x80)
|
|
|
|
pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size);
|
|
|
|
if (ppc64_caches.iline_size != 0x80)
|
|
|
|
pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size);
|
|
|
|
|
|
|
|
pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features);
|
|
|
|
pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE);
|
|
|
|
pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS);
|
|
|
|
pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
|
|
|
|
cur_cpu_spec->cpu_user_features2);
|
|
|
|
pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features);
|
|
|
|
pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_STD_MMU_64
|
|
|
|
if (htab_address)
|
|
|
|
pr_info("htab_address = 0x%p\n", htab_address);
|
|
|
|
|
|
|
|
pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (PHYSICAL_START > 0)
|
|
|
|
pr_info("physical_start = 0x%llx\n",
|
|
|
|
(unsigned long long)PHYSICAL_START);
|
|
|
|
pr_info("-----------------------------------------------------\n");
|
|
|
|
}
|
2005-10-10 19:50:37 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Do some initial setup of the system. The parameters are those which
|
|
|
|
* were passed in from the bootloader.
|
|
|
|
*/
|
|
|
|
void __init setup_system(void)
|
|
|
|
{
|
|
|
|
DBG(" -> setup_system()\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unflatten the device-tree passed by prom_init or kexec
|
|
|
|
*/
|
|
|
|
unflatten_device_tree();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fill the ppc64_caches & systemcfg structures with informations
|
2006-07-03 18:36:01 +07:00
|
|
|
* retrieved from the device-tree.
|
2005-10-10 19:50:37 +07:00
|
|
|
*/
|
|
|
|
initialize_cache_info();
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
/*
|
|
|
|
* Initialize RTAS if available
|
|
|
|
*/
|
|
|
|
rtas_initialize();
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if we have an initrd provided via the device-tree
|
|
|
|
*/
|
|
|
|
check_for_initrd();
|
|
|
|
|
2016-07-05 12:04:00 +07:00
|
|
|
/* Probe the machine type */
|
|
|
|
probe_machine();
|
|
|
|
|
2005-11-23 13:56:06 +07:00
|
|
|
/*
|
|
|
|
* We can discover serial ports now since the above did setup the
|
|
|
|
* hash table management for us, thus ioremap works. We do that early
|
|
|
|
* so that further code can be debugged
|
|
|
|
*/
|
|
|
|
find_legacy_serial_ports();
|
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
/*
|
|
|
|
* Register early console
|
|
|
|
*/
|
|
|
|
register_early_udbg_console();
|
|
|
|
|
2006-10-03 11:12:08 +07:00
|
|
|
/*
|
|
|
|
* Initialize xmon
|
|
|
|
*/
|
|
|
|
xmon_setup();
|
2006-05-17 15:00:41 +07:00
|
|
|
|
2005-11-05 06:33:55 +07:00
|
|
|
smp_setup_cpu_maps();
|
2010-08-05 14:42:11 +07:00
|
|
|
check_smt_enabled();
|
2013-10-12 07:22:38 +07:00
|
|
|
setup_tlb_core_data();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2011-12-08 14:20:27 +07:00
|
|
|
/*
|
|
|
|
* Freescale Book3e parts spin in a loop provided by firmware,
|
|
|
|
* so smp_release_cpus() does nothing for them
|
|
|
|
*/
|
2015-10-07 10:48:19 +07:00
|
|
|
#if defined(CONFIG_SMP)
|
2005-10-10 19:50:37 +07:00
|
|
|
/* Release secondary cpus out of their spinloops at 0x60 now that
|
|
|
|
* we can map physical -> logical CPU ids
|
|
|
|
*/
|
|
|
|
smp_release_cpus();
|
2006-02-16 10:13:50 +07:00
|
|
|
#endif
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2016-07-05 12:04:07 +07:00
|
|
|
/* Print various info about the machine that has been gathered so far. */
|
|
|
|
print_system_info();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
|
|
|
DBG(" <- setup_system()\n");
|
|
|
|
}
|
|
|
|
|
2011-05-03 21:07:01 +07:00
|
|
|
/* This returns the limit below which memory accesses to the linear
|
|
|
|
* mapping are guarnateed not to cause a TLB or SLB miss. This is
|
|
|
|
* used to allocate interrupt or emergency stacks for which our
|
|
|
|
* exception entry path doesn't deal with being interrupted.
|
|
|
|
*/
|
|
|
|
static u64 safe_stack_limit(void)
|
2010-05-11 01:59:18 +07:00
|
|
|
{
|
2011-05-03 21:07:01 +07:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
/* Freescale BookE bolts the entire linear mapping */
|
|
|
|
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
|
|
|
|
return linear_map_top;
|
|
|
|
/* Other BookE, we assume the first GB is bolted */
|
|
|
|
return 1ul << 30;
|
|
|
|
#else
|
|
|
|
/* BookS, the first segment is bolted */
|
|
|
|
if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
|
2010-05-11 01:59:18 +07:00
|
|
|
return 1UL << SID_SHIFT_1T;
|
|
|
|
return 1UL << SID_SHIFT;
|
2011-05-03 21:07:01 +07:00
|
|
|
#endif
|
2010-05-11 01:59:18 +07:00
|
|
|
}
|
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
static void __init irqstack_early_init(void)
|
|
|
|
{
|
2011-05-03 21:07:01 +07:00
|
|
|
u64 limit = safe_stack_limit();
|
2005-10-10 19:50:37 +07:00
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/*
|
2010-12-08 07:55:03 +07:00
|
|
|
* Interrupt stacks must be in the first segment since we
|
|
|
|
* cannot afford to take SLB misses on them.
|
2005-10-10 19:50:37 +07:00
|
|
|
*/
|
2006-03-29 05:50:51 +07:00
|
|
|
for_each_possible_cpu(i) {
|
2005-11-07 07:06:55 +07:00
|
|
|
softirq_ctx[i] = (struct thread_info *)
|
2010-07-12 11:36:09 +07:00
|
|
|
__va(memblock_alloc_base(THREAD_SIZE,
|
2010-05-11 01:59:18 +07:00
|
|
|
THREAD_SIZE, limit));
|
2005-11-07 07:06:55 +07:00
|
|
|
hardirq_ctx[i] = (struct thread_info *)
|
2010-07-12 11:36:09 +07:00
|
|
|
__va(memblock_alloc_base(THREAD_SIZE,
|
2010-05-11 01:59:18 +07:00
|
|
|
THREAD_SIZE, limit));
|
2005-10-10 19:50:37 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-24 06:15:59 +07:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
static void __init exc_lvl_early_init(void)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
2013-10-23 16:31:21 +07:00
|
|
|
unsigned long sp;
|
2009-07-24 06:15:59 +07:00
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
2013-10-23 16:31:21 +07:00
|
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
|
|
critirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
|
|
paca[i].crit_kstack = __va(sp + THREAD_SIZE);
|
|
|
|
|
|
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
|
|
dbgirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
|
|
paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
|
|
|
|
|
|
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
|
|
mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
|
|
paca[i].mc_kstack = __va(sp + THREAD_SIZE);
|
2009-07-24 06:15:59 +07:00
|
|
|
}
|
2011-04-06 12:18:48 +07:00
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
|
2013-05-12 06:26:23 +07:00
|
|
|
patch_exception(0x040, exc_debug_debug_book3e);
|
2009-07-24 06:15:59 +07:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define exc_lvl_early_init()
|
|
|
|
#endif
|
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
/*
|
|
|
|
* Stack space used when we detect a bad kernel stack pointer, and
|
2013-10-30 21:34:00 +07:00
|
|
|
* early in SMP boots before relocation is enabled. Exclusive emergency
|
|
|
|
* stack for machine checks.
|
2005-10-10 19:50:37 +07:00
|
|
|
*/
|
|
|
|
static void __init emergency_stack_init(void)
|
|
|
|
{
|
2010-05-11 01:59:18 +07:00
|
|
|
u64 limit;
|
2005-10-10 19:50:37 +07:00
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Emergency stacks must be under 256MB, we cannot afford to take
|
|
|
|
* SLB misses on them. The ABI also requires them to be 128-byte
|
|
|
|
* aligned.
|
|
|
|
*
|
|
|
|
* Since we use these as temporary stacks during secondary CPU
|
|
|
|
* bringup, we need to get at them in real mode. This means they
|
|
|
|
* must also be within the RMO region.
|
|
|
|
*/
|
2011-05-03 21:07:01 +07:00
|
|
|
limit = min(safe_stack_limit(), ppc64_rma_size);
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2008-04-30 10:21:45 +07:00
|
|
|
for_each_possible_cpu(i) {
|
2016-03-24 18:04:04 +07:00
|
|
|
struct thread_info *ti;
|
|
|
|
ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
|
|
|
|
klp_init_thread_info(ti);
|
|
|
|
paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
|
2013-10-30 21:34:00 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
/* emergency stack for machine check exception handling. */
|
2016-03-24 18:04:04 +07:00
|
|
|
ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
|
|
|
|
klp_init_thread_info(ti);
|
|
|
|
paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
|
2013-10-30 21:34:00 +07:00
|
|
|
#endif
|
2008-04-30 10:21:45 +07:00
|
|
|
}
|
2005-10-10 19:50:37 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
powerpc: Remove more traces of bootmem
Although we are now selecting NO_BOOTMEM, we still have some traces of
bootmem lying around. That is because even with NO_BOOTMEM there is
still a shim that converts bootmem calls into memblock calls, but
ultimately we want to remove all traces of bootmem.
Most of the patch is conversions from alloc_bootmem() to
memblock_virt_alloc(). In general a call such as:
p = (struct foo *)alloc_bootmem(x);
Becomes:
p = memblock_virt_alloc(x, 0);
We don't need the cast because memblock_virt_alloc() returns a void *.
The alignment value of zero tells memblock to use the default alignment,
which is SMP_CACHE_BYTES, the same value alloc_bootmem() uses.
We remove a number of NULL checks on the result of
memblock_virt_alloc(). That is because memblock_virt_alloc() will panic
if it can't allocate, in exactly the same way as alloc_bootmem(), so the
NULL checks are and always have been redundant.
The memory returned by memblock_virt_alloc() is already zeroed, so we
remove several memsets of the result of memblock_virt_alloc().
Finally we convert a few uses of __alloc_bootmem(x, y, MAX_DMA_ADDRESS)
to just plain memblock_virt_alloc(). We don't use memblock_alloc_base()
because MAX_DMA_ADDRESS is ~0ul on powerpc, so limiting the allocation
to that is pointless, 16XB ought to be enough for anyone.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2014-11-18 12:47:35 +07:00
|
|
|
* Called into from start_kernel this initializes memblock, which is used
|
2010-11-16 14:55:16 +07:00
|
|
|
* to manage page allocation until mem_init is called.
|
2005-10-10 19:50:37 +07:00
|
|
|
*/
|
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
|
|
{
|
2014-09-17 11:39:36 +07:00
|
|
|
*cmdline_p = boot_command_line;
|
2005-10-10 19:50:37 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set cache line size based on type of cpu as a default.
|
|
|
|
* Systems with OF can look in the properties on the cpu node(s)
|
|
|
|
* for a possibly more accurate value.
|
|
|
|
*/
|
|
|
|
dcache_bsize = ppc64_caches.dline_size;
|
|
|
|
icache_bsize = ppc64_caches.iline_size;
|
|
|
|
|
2016-07-05 12:03:43 +07:00
|
|
|
|
|
|
|
/* Reserve large chunks of memory for use by CMA for KVM */
|
|
|
|
kvm_cma_reserve();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reserve any gigantic pages requested on the command line.
|
|
|
|
* memblock needs to have been initialized by the time this is
|
|
|
|
* called since this will reserve memory.
|
|
|
|
*/
|
|
|
|
reserve_hugetlb_gpages();
|
|
|
|
|
2005-10-10 19:50:37 +07:00
|
|
|
if (ppc_md.panic)
|
2006-05-05 12:02:08 +07:00
|
|
|
setup_panic();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2016-03-24 18:04:04 +07:00
|
|
|
klp_init_thread_info(&init_thread_info);
|
|
|
|
|
2008-04-16 02:52:26 +07:00
|
|
|
init_mm.start_code = (unsigned long)_stext;
|
2005-10-10 19:50:37 +07:00
|
|
|
init_mm.end_code = (unsigned long) _etext;
|
|
|
|
init_mm.end_data = (unsigned long) _edata;
|
|
|
|
init_mm.brk = klimit;
|
2013-04-28 16:37:33 +07:00
|
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
|
|
init_mm.context.pte_frag = NULL;
|
2015-06-05 13:35:24 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
|
|
|
mm_iommu_init(&init_mm.context);
|
2013-04-28 16:37:33 +07:00
|
|
|
#endif
|
2005-10-10 19:50:37 +07:00
|
|
|
irqstack_early_init();
|
2009-07-24 06:15:59 +07:00
|
|
|
exc_lvl_early_init();
|
2005-10-10 19:50:37 +07:00
|
|
|
emergency_stack_init();
|
|
|
|
|
2014-09-17 19:15:33 +07:00
|
|
|
initmem_init();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
2005-10-20 18:00:20 +07:00
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
|
|
conswitchp = &dummy_con;
|
|
|
|
#endif
|
2007-10-11 01:48:18 +07:00
|
|
|
if (ppc_md.setup_arch)
|
|
|
|
ppc_md.setup_arch();
|
2005-10-10 19:50:37 +07:00
|
|
|
|
|
|
|
paging_init();
|
2009-07-24 06:15:26 +07:00
|
|
|
|
|
|
|
/* Initialize the MMU context management stuff */
|
|
|
|
mmu_context_init();
|
|
|
|
|
2012-11-05 13:10:35 +07:00
|
|
|
/* Interrupt code needs to be 64K-aligned */
|
|
|
|
if ((unsigned long)_stext & 0xffff)
|
|
|
|
panic("Kernelbase not 64K-aligned (0x%lx)!\n",
|
|
|
|
(unsigned long)_stext);
|
2005-10-10 19:50:37 +07:00
|
|
|
}
|
|
|
|
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
|
|
|
#ifdef CONFIG_SMP
|
2009-08-14 13:00:53 +07:00
|
|
|
#define PCPU_DYN_SIZE ()
|
|
|
|
|
|
|
|
static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
|
|
|
{
|
2009-08-14 13:00:53 +07:00
|
|
|
return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
|
|
|
|
__pa(MAX_DMA_ADDRESS));
|
|
|
|
}
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
|
|
|
|
2009-08-14 13:00:53 +07:00
|
|
|
static void __init pcpu_fc_free(void *ptr, size_t size)
|
|
|
|
{
|
|
|
|
free_bootmem(__pa(ptr), size);
|
|
|
|
}
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
|
|
|
|
2009-08-14 13:00:53 +07:00
|
|
|
static int pcpu_cpu_distance(unsigned int from, unsigned int to)
|
|
|
|
{
|
|
|
|
if (cpu_to_node(from) == cpu_to_node(to))
|
|
|
|
return LOCAL_DISTANCE;
|
|
|
|
else
|
|
|
|
return REMOTE_DISTANCE;
|
|
|
|
}
|
|
|
|
|
powerpc: Optimise per cpu accesses on 64bit
Now we dynamically allocate the paca array, it takes an extra load
whenever we want to access another cpu's paca. One place we do that a lot
is per cpu variables. A simple example:
DEFINE_PER_CPU(unsigned long, vara);
unsigned long test4(int cpu)
{
return per_cpu(vara, cpu);
}
This takes 4 loads, 5 if you include the actual load of the per cpu variable:
ld r11,-32760(r30) # load address of paca pointer
ld r9,-32768(r30) # load link address of percpu variable
sldi r3,r29,9 # get offset into paca (each entry is 512 bytes)
ld r0,0(r11) # load paca pointer
add r3,r0,r3 # paca + offset
ld r11,64(r3) # load paca[cpu].data_offset
ldx r3,r9,r11 # load per cpu variable
If we remove the ppc64 specific per_cpu_offset(), we get the generic one
which indexes into a statically allocated array. This removes one load and
one add:
ld r11,-32760(r30) # load address of __per_cpu_offset
ld r9,-32768(r30) # load link address of percpu variable
sldi r3,r29,3 # get offset into __per_cpu_offset (each entry 8 bytes)
ldx r11,r11,r3 # load __per_cpu_offset[cpu]
ldx r3,r9,r11 # load per cpu variable
Having all the offsets in one array also helps when iterating over a per cpu
variable across a number of cpus, such as in the scheduler. Before we would
need to load one paca cacheline when calculating each per cpu offset. Now we
have 16 (128 / sizeof(long)) per cpu offsets in each cacheline.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-06-01 01:45:11 +07:00
|
|
|
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
|
|
|
|
EXPORT_SYMBOL(__per_cpu_offset);
|
|
|
|
|
2009-08-14 13:00:53 +07:00
|
|
|
void __init setup_per_cpu_areas(void)
|
|
|
|
{
|
|
|
|
const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
|
|
|
|
size_t atom_size;
|
|
|
|
unsigned long delta;
|
|
|
|
unsigned int cpu;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Linear mapping is one of 4K, 1M and 16M. For 4K, no need
|
|
|
|
* to group units. For larger mappings, use 1M atom which
|
|
|
|
* should be large enough to contain a number of units.
|
|
|
|
*/
|
|
|
|
if (mmu_linear_psize == MMU_PAGE_4K)
|
|
|
|
atom_size = PAGE_SIZE;
|
|
|
|
else
|
|
|
|
atom_size = 1 << 20;
|
|
|
|
|
|
|
|
rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
|
|
|
|
pcpu_fc_alloc, pcpu_fc_free);
|
|
|
|
if (rc < 0)
|
|
|
|
panic("cannot initialize percpu area (err=%d)", rc);
|
|
|
|
|
|
|
|
delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
|
powerpc: Optimise per cpu accesses on 64bit
Now we dynamically allocate the paca array, it takes an extra load
whenever we want to access another cpu's paca. One place we do that a lot
is per cpu variables. A simple example:
DEFINE_PER_CPU(unsigned long, vara);
unsigned long test4(int cpu)
{
return per_cpu(vara, cpu);
}
This takes 4 loads, 5 if you include the actual load of the per cpu variable:
ld r11,-32760(r30) # load address of paca pointer
ld r9,-32768(r30) # load link address of percpu variable
sldi r3,r29,9 # get offset into paca (each entry is 512 bytes)
ld r0,0(r11) # load paca pointer
add r3,r0,r3 # paca + offset
ld r11,64(r3) # load paca[cpu].data_offset
ldx r3,r9,r11 # load per cpu variable
If we remove the ppc64 specific per_cpu_offset(), we get the generic one
which indexes into a statically allocated array. This removes one load and
one add:
ld r11,-32760(r30) # load address of __per_cpu_offset
ld r9,-32768(r30) # load link address of percpu variable
sldi r3,r29,3 # get offset into __per_cpu_offset (each entry 8 bytes)
ldx r11,r11,r3 # load __per_cpu_offset[cpu]
ldx r3,r9,r11 # load per cpu variable
Having all the offsets in one array also helps when iterating over a per cpu
variable across a number of cpus, such as in the scheduler. Before we would
need to load one paca cacheline when calculating each per cpu offset. Now we
have 16 (128 / sizeof(long)) per cpu offsets in each cacheline.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-06-01 01:45:11 +07:00
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
|
|
|
|
paca[cpu].data_offset = __per_cpu_offset[cpu];
|
|
|
|
}
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 09:16:44 +07:00
|
|
|
}
|
|
|
|
#endif
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
|
2014-06-04 14:50:47 +07:00
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
|
|
|
|
unsigned long memory_block_size_bytes(void)
|
|
|
|
{
|
|
|
|
if (ppc_md.memory_block_size)
|
|
|
|
return ppc_md.memory_block_size();
|
|
|
|
|
|
|
|
return MIN_MEMORY_BLOCK_SIZE;
|
|
|
|
}
|
|
|
|
#endif
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
|
2013-07-15 10:03:08 +07:00
|
|
|
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
struct ppc_pci_io ppc_pci_io;
|
|
|
|
EXPORT_SYMBOL(ppc_pci_io);
|
2013-07-15 10:03:08 +07:00
|
|
|
#endif
|
2015-04-09 09:52:56 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_HARDLOCKUP_DETECTOR
|
|
|
|
u64 hw_nmi_get_sample_period(int watchdog_thresh)
|
|
|
|
{
|
|
|
|
return ppc_proc_freq * watchdog_thresh;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The hardlockup detector breaks PMU event based branches and is likely
|
|
|
|
* to get false positives in KVM guests, so disable it by default.
|
|
|
|
*/
|
|
|
|
static int __init disable_hardlockup_detector(void)
|
|
|
|
{
|
powerpc updates for 4.1
- Numerous minor fixes, cleanups etc.
- More EEH work from Gavin to remove its dependency on device_nodes.
- Memory hotplug implemented entirely in the kernel from Nathan Fontenot.
- Removal of redundant CONFIG_PPC_OF by Kevin Hao.
- Rewrite of VPHN parsing logic & tests from Greg Kurz.
- A fix from Nish Aravamudan to reduce memory usage by clamping
nodes_possible_map.
- Support for pstore on powernv from Hari Bathini.
- Removal of old powerpc specific byte swap routines by David Gibson.
- Fix from Vasant Hegde to prevent the flash driver telling you it was flashing
your firmware when it wasn't.
- Patch from Ben Herrenschmidt to add an OPAL heartbeat driver.
- Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan Stancek.
- Some fixes for migration from Tyrel Datwyler.
- A new syscall to switch the cpu endian by Michael Ellerman.
- Large series from Wei Yang to implement SRIOV, reviewed and acked by Bjorn.
- A fix for the OPAL sensor driver from Cédric Le Goater.
- Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman.
- Large series from Daniel Axtens to make our PCI hooks per PHB rather than per
machine.
- Small patch from Sam Bobroff to explicitly abort non-suspended transactions
on syscalls, plus a test to exercise it.
- Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu.
- Small patch to enable the hard lockup detector from Anton Blanchard.
- Fix from Dave Olson for missing L2 cache information on some CPUs.
- Some fixes from Michael Ellerman to get Cell machines booting again.
- Freescale updates from Scott: Highlights include BMan device tree nodes, an
MSI erratum workaround, a couple minor performance improvements, config
updates, and misc fixes/cleanup.
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Merge tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
Pull powerpc updates from Michael Ellerman:
- Numerous minor fixes, cleanups etc.
- More EEH work from Gavin to remove its dependency on device_nodes.
- Memory hotplug implemented entirely in the kernel from Nathan
Fontenot.
- Removal of redundant CONFIG_PPC_OF by Kevin Hao.
- Rewrite of VPHN parsing logic & tests from Greg Kurz.
- A fix from Nish Aravamudan to reduce memory usage by clamping
nodes_possible_map.
- Support for pstore on powernv from Hari Bathini.
- Removal of old powerpc specific byte swap routines by David Gibson.
- Fix from Vasant Hegde to prevent the flash driver telling you it was
flashing your firmware when it wasn't.
- Patch from Ben Herrenschmidt to add an OPAL heartbeat driver.
- Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan
Stancek.
- Some fixes for migration from Tyrel Datwyler.
- A new syscall to switch the cpu endian by Michael Ellerman.
- Large series from Wei Yang to implement SRIOV, reviewed and acked by
Bjorn.
- A fix for the OPAL sensor driver from Cédric Le Goater.
- Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman.
- Large series from Daniel Axtens to make our PCI hooks per PHB rather
than per machine.
- Small patch from Sam Bobroff to explicitly abort non-suspended
transactions on syscalls, plus a test to exercise it.
- Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu.
- Small patch to enable the hard lockup detector from Anton Blanchard.
- Fix from Dave Olson for missing L2 cache information on some CPUs.
- Some fixes from Michael Ellerman to get Cell machines booting again.
- Freescale updates from Scott: Highlights include BMan device tree
nodes, an MSI erratum workaround, a couple minor performance
improvements, config updates, and misc fixes/cleanup.
* tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (196 commits)
powerpc/powermac: Fix build error seen with powermac smp builds
powerpc/pseries: Fix compile of memory hotplug without CONFIG_MEMORY_HOTREMOVE
powerpc: Remove PPC32 code from pseries specific find_and_init_phbs()
powerpc/cell: Fix iommu breakage caused by controller_ops change
powerpc/eeh: Fix crash in eeh_add_device_early() on Cell
powerpc/perf: Cap 64bit userspace backtraces to PERF_MAX_STACK_DEPTH
powerpc/perf/hv-24x7: Fail 24x7 initcall if create_events_from_catalog() fails
powerpc/pseries: Correct memory hotplug locking
powerpc: Fix missing L2 cache size in /sys/devices/system/cpu
powerpc: Add ppc64 hard lockup detector support
oprofile: Disable oprofile NMI timer on ppc64
powerpc/perf/hv-24x7: Add missing put_cpu_var()
powerpc/perf/hv-24x7: Break up single_24x7_request
powerpc/perf/hv-24x7: Define update_event_count()
powerpc/perf/hv-24x7: Whitespace cleanup
powerpc/perf/hv-24x7: Define add_event_to_24x7_request()
powerpc/perf/hv-24x7: Rename hv_24x7_event_update
powerpc/perf/hv-24x7: Move debug prints to separate function
powerpc/perf/hv-24x7: Drop event_24x7_request()
powerpc/perf/hv-24x7: Use pr_devel() to log message
...
Conflicts:
tools/testing/selftests/powerpc/Makefile
tools/testing/selftests/powerpc/tm/Makefile
2015-04-17 01:53:32 +07:00
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hardlockup_detector_disable();
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2015-04-09 09:52:56 +07:00
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return 0;
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}
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early_initcall(disable_hardlockup_detector);
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#endif
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