2013-02-27 15:15:01 +07:00
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/*
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* Renesas IRQC Driver
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2015-04-01 19:00:06 +07:00
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#include <linux/clk.h>
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2013-02-27 15:15:01 +07:00
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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2015-03-19 01:55:56 +07:00
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#include <linux/pm_runtime.h>
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2013-02-27 15:15:01 +07:00
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2015-03-19 01:55:55 +07:00
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#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
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2013-02-27 15:15:01 +07:00
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2015-03-19 01:55:55 +07:00
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#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
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#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
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#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
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2013-02-27 15:15:01 +07:00
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#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
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2015-03-19 01:55:55 +07:00
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/* SYS-CPU vs. RT-CPU */
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#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
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#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
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#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
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#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
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#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
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#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
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#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
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#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
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#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
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2013-02-27 15:15:01 +07:00
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#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
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2015-03-19 01:55:55 +07:00
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/* IRQn Configuration Register */
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2013-02-27 15:15:01 +07:00
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struct irqc_irq {
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int hw_irq;
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int requested_irq;
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int domain_irq;
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struct irqc_priv *p;
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};
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struct irqc_priv {
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void __iomem *iomem;
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void __iomem *cpu_int_base;
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struct irqc_irq irq[IRQC_IRQ_MAX];
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unsigned int number_of_irqs;
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struct platform_device *pdev;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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2015-04-01 19:00:06 +07:00
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struct clk *clk;
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2013-02-27 15:15:01 +07:00
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};
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static void irqc_dbg(struct irqc_irq *i, char *str)
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{
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dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
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str, i->requested_irq, i->hw_irq, i->domain_irq);
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}
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static void irqc_irq_enable(struct irq_data *d)
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{
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struct irqc_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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irqc_dbg(&p->irq[hw_irq], "enable");
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iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
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}
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static void irqc_irq_disable(struct irq_data *d)
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{
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struct irqc_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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irqc_dbg(&p->irq[hw_irq], "disable");
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iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
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}
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static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
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2013-12-14 07:09:31 +07:00
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[IRQ_TYPE_LEVEL_LOW] = 0x01,
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[IRQ_TYPE_LEVEL_HIGH] = 0x02,
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[IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
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[IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
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[IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
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2013-02-27 15:15:01 +07:00
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};
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static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irqc_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
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2015-02-26 17:43:32 +07:00
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u32 tmp;
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2013-02-27 15:15:01 +07:00
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irqc_dbg(&p->irq[hw_irq], "sense");
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2013-12-14 07:09:31 +07:00
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if (!value)
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2013-02-27 15:15:01 +07:00
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return -EINVAL;
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tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
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tmp &= ~0x3f;
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2013-12-14 07:09:31 +07:00
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tmp |= value;
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2013-02-27 15:15:01 +07:00
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iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
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return 0;
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}
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2015-04-01 19:00:06 +07:00
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static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct irqc_priv *p = irq_data_get_irq_chip_data(d);
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if (!p->clk)
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return 0;
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if (on)
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clk_enable(p->clk);
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else
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clk_disable(p->clk);
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return 0;
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}
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2013-02-27 15:15:01 +07:00
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static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
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{
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struct irqc_irq *i = dev_id;
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struct irqc_priv *p = i->p;
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2015-02-26 17:43:32 +07:00
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u32 bit = BIT(i->hw_irq);
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2013-02-27 15:15:01 +07:00
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irqc_dbg(i, "demux1");
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if (ioread32(p->iomem + DETECT_STATUS) & bit) {
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iowrite32(bit, p->iomem + DETECT_STATUS);
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irqc_dbg(i, "demux2");
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generic_handle_irq(i->domain_irq);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct irqc_priv *p = h->host_data;
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p->irq[hw].domain_irq = virq;
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p->irq[hw].hw_irq = hw;
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irqc_dbg(&p->irq[hw], "map");
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID); /* kill me now */
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return 0;
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}
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2015-04-27 19:54:24 +07:00
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static const struct irq_domain_ops irqc_irq_domain_ops = {
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2013-02-27 15:15:01 +07:00
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.map = irqc_irq_domain_map,
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2013-03-06 13:23:39 +07:00
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.xlate = irq_domain_xlate_twocell,
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2013-02-27 15:15:01 +07:00
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};
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static int irqc_probe(struct platform_device *pdev)
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{
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struct irqc_priv *p;
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struct resource *io;
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struct resource *irq;
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struct irq_chip *irq_chip;
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const char *name = dev_name(&pdev->dev);
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int ret;
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int k;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p) {
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dev_err(&pdev->dev, "failed to allocate driver data\n");
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ret = -ENOMEM;
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goto err0;
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}
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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2015-04-01 19:00:06 +07:00
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p->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(p->clk)) {
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dev_warn(&pdev->dev, "unable to get clock\n");
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p->clk = NULL;
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}
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2015-03-19 01:55:56 +07:00
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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2013-02-27 15:15:01 +07:00
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/* get hold of manadatory IOMEM */
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!io) {
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dev_err(&pdev->dev, "not enough IOMEM resources\n");
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ret = -EINVAL;
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goto err1;
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}
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/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
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for (k = 0; k < IRQC_IRQ_MAX; k++) {
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
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if (!irq)
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break;
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p->irq[k].p = p;
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p->irq[k].requested_irq = irq->start;
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}
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p->number_of_irqs = k;
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if (p->number_of_irqs < 1) {
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dev_err(&pdev->dev, "not enough IRQ resources\n");
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ret = -EINVAL;
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goto err1;
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}
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/* ioremap IOMEM and setup read/write callbacks */
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p->iomem = ioremap_nocache(io->start, resource_size(io));
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if (!p->iomem) {
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dev_err(&pdev->dev, "failed to remap IOMEM\n");
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ret = -ENXIO;
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goto err2;
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}
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p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
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irq_chip = &p->irq_chip;
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irq_chip->name = name;
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irq_chip->irq_mask = irqc_irq_disable;
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irq_chip->irq_unmask = irqc_irq_enable;
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irq_chip->irq_set_type = irqc_irq_set_type;
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2015-04-01 19:00:06 +07:00
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irq_chip->irq_set_wake = irqc_irq_set_wake;
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irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
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2013-02-27 15:15:01 +07:00
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p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
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2015-04-28 17:17:50 +07:00
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p->number_of_irqs, 0,
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2013-02-27 15:15:01 +07:00
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&irqc_irq_domain_ops, p);
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if (!p->irq_domain) {
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ret = -ENXIO;
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dev_err(&pdev->dev, "cannot initialize irq domain\n");
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goto err2;
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}
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/* request interrupts one by one */
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for (k = 0; k < p->number_of_irqs; k++) {
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if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
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0, name, &p->irq[k])) {
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dev_err(&pdev->dev, "failed to request IRQ\n");
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ret = -ENOENT;
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goto err3;
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}
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}
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dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
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return 0;
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err3:
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2013-05-06 16:03:32 +07:00
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while (--k >= 0)
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free_irq(p->irq[k].requested_irq, &p->irq[k]);
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2013-02-27 15:15:01 +07:00
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irq_domain_remove(p->irq_domain);
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err2:
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iounmap(p->iomem);
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err1:
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2015-03-19 01:55:56 +07:00
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pm_runtime_put(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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2013-02-27 15:15:01 +07:00
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kfree(p);
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err0:
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return ret;
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}
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static int irqc_remove(struct platform_device *pdev)
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{
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struct irqc_priv *p = platform_get_drvdata(pdev);
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int k;
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for (k = 0; k < p->number_of_irqs; k++)
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free_irq(p->irq[k].requested_irq, &p->irq[k]);
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irq_domain_remove(p->irq_domain);
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iounmap(p->iomem);
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2015-03-19 01:55:56 +07:00
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pm_runtime_put(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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2013-02-27 15:15:01 +07:00
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kfree(p);
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return 0;
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}
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|
2013-03-06 13:23:39 +07:00
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static const struct of_device_id irqc_dt_ids[] = {
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{ .compatible = "renesas,irqc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, irqc_dt_ids);
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2013-02-27 15:15:01 +07:00
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static struct platform_driver irqc_device_driver = {
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.probe = irqc_probe,
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.remove = irqc_remove,
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.driver = {
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.name = "renesas_irqc",
|
2013-03-06 13:23:39 +07:00
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.of_match_table = irqc_dt_ids,
|
2013-02-27 15:15:01 +07:00
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}
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};
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static int __init irqc_init(void)
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{
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return platform_driver_register(&irqc_device_driver);
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}
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postcore_initcall(irqc_init);
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static void __exit irqc_exit(void)
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{
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platform_driver_unregister(&irqc_device_driver);
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}
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module_exit(irqc_exit);
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MODULE_AUTHOR("Magnus Damm");
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MODULE_DESCRIPTION("Renesas IRQC Driver");
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MODULE_LICENSE("GPL v2");
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