2018-06-12 12:58:38 +07:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// Helper routines for R-Car sound ADG.
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//
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// Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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2015-09-10 14:04:45 +07:00
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#include <linux/clk-provider.h>
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2013-07-22 11:36:46 +07:00
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#include "rsnd.h"
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#define CLKA 0
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#define CLKB 1
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#define CLKC 2
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#define CLKI 3
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#define CLKMAX 4
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2015-09-10 14:04:45 +07:00
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#define CLKOUT 0
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#define CLKOUT1 1
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#define CLKOUT2 2
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#define CLKOUT3 3
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#define CLKOUTMAX 4
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2015-09-10 14:03:48 +07:00
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#define BRRx_MASK(x) (0x3FF & x)
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2015-09-10 14:02:39 +07:00
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static struct rsnd_mod_ops adg_ops = {
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.name = "adg",
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};
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2013-07-22 11:36:46 +07:00
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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2015-09-10 14:04:45 +07:00
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struct clk *clkout[CLKOUTMAX];
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struct clk_onecell_data onecell;
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2015-09-10 14:02:39 +07:00
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struct rsnd_mod mod;
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2016-06-09 10:21:37 +07:00
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u32 flags;
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2016-12-07 07:28:11 +07:00
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u32 ckr;
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u32 rbga;
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u32 rbgb;
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2013-07-22 11:36:46 +07:00
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2015-09-10 14:03:48 +07:00
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int rbga_rate_for_441khz; /* RBGA */
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int rbgb_rate_for_48khz; /* RBGB */
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2013-07-22 11:36:46 +07:00
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};
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2016-06-09 10:21:37 +07:00
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#define LRCLK_ASYNC (1 << 0)
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2017-04-19 07:45:52 +07:00
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#define AUDIO_OUT_48 (1 << 1)
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2016-06-09 10:21:37 +07:00
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2013-07-22 11:36:46 +07:00
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#define for_each_rsnd_clk(pos, adg, i) \
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2014-02-12 08:15:51 +07:00
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for (i = 0; \
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(i < CLKMAX) && \
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((pos) = adg->clk[i]); \
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i++)
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2015-09-10 14:04:45 +07:00
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#define for_each_rsnd_clkout(pos, adg, i) \
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for (i = 0; \
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(i < CLKOUTMAX) && \
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((pos) = adg->clkout[i]); \
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i++)
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2013-07-22 11:36:46 +07:00
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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2017-10-13 13:03:06 +07:00
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static const char * const clk_name[] = {
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[CLKA] = "clk_a",
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[CLKB] = "clk_b",
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[CLKC] = "clk_c",
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[CLKI] = "clk_i",
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};
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2015-09-10 14:03:48 +07:00
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static u32 rsnd_adg_calculate_rbgx(unsigned long div)
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{
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int i, ratio;
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if (!div)
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return 0;
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for (i = 3; i >= 0; i--) {
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ratio = 2 << (i * 2);
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if (0 == (div % ratio))
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return (u32)((i << 8) | ((div / ratio) - 1));
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}
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return ~0;
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}
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2014-01-24 09:42:00 +07:00
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2014-03-03 14:43:33 +07:00
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static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
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2014-01-24 09:42:00 +07:00
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{
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2015-11-30 15:49:15 +07:00
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struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
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int id = rsnd_mod_id(ssi_mod);
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2014-01-24 09:42:00 +07:00
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int ws = id;
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2015-10-22 10:15:46 +07:00
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if (rsnd_ssi_is_pin_sharing(io)) {
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2014-01-24 09:42:00 +07:00
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switch (id) {
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case 1:
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case 2:
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ws = 0;
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break;
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case 4:
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ws = 3;
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break;
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case 8:
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ws = 7;
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break;
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}
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}
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return (0x6 + ws) << 8;
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}
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2016-03-07 12:09:14 +07:00
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static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int target_rate,
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unsigned int *target_val,
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unsigned int *target_en)
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, step;
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unsigned int val, en;
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unsigned int min, diff;
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unsigned int sel_rate[] = {
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clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
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adg->rbga_rate_for_441khz, /* 0011: RBGA */
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adg->rbgb_rate_for_48khz, /* 0100: RBGB */
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};
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min = ~0;
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val = 0;
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en = 0;
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
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idx = 0;
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step = 2;
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if (!sel_rate[sel])
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continue;
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for (div = 2; div <= 98304; div += step) {
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diff = abs(target_rate - sel_rate[sel] / div);
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if (min > diff) {
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val = (sel << 8) | idx;
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min = diff;
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en = 1 << (sel + 1); /* fixme */
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}
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/*
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* step of 0_0000 / 0_0001 / 0_1101
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* are out of order
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*/
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if ((idx > 2) && (idx % 2))
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step *= 2;
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if (idx == 0x1c) {
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div += step;
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step *= 2;
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}
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idx++;
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}
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}
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if (min == ~0) {
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dev_err(dev, "no Input clock\n");
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return;
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}
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*target_val = val;
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if (target_en)
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*target_en = en;
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}
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static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate,
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u32 *in, u32 *out, u32 *en)
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{
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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unsigned int target_rate;
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u32 *target_val;
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u32 _in;
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u32 _out;
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u32 _en;
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/* default = SSI WS */
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_in =
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_out = rsnd_adg_ssi_ws_timing_gen2(io);
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target_rate = 0;
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target_val = NULL;
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_en = 0;
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if (runtime->rate != in_rate) {
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target_rate = out_rate;
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target_val = &_out;
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} else if (runtime->rate != out_rate) {
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target_rate = in_rate;
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target_val = &_in;
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}
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if (target_rate)
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__rsnd_adg_get_timesel_ratio(priv, io,
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target_rate,
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target_val, &_en);
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if (in)
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*in = _in;
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if (out)
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*out = _out;
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if (en)
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*en = _en;
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}
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2015-11-30 15:49:15 +07:00
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
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2014-05-09 07:44:49 +07:00
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struct rsnd_dai_stream *io)
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{
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2015-11-30 15:49:15 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2015-11-30 15:49:15 +07:00
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int id = rsnd_mod_id(cmd_mod);
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2014-05-09 07:44:49 +07:00
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int shift = (id % 2) ? 16 : 0;
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u32 mask, val;
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2016-03-07 12:09:34 +07:00
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rsnd_adg_get_timesel_ratio(priv, io,
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rsnd_src_get_in_rate(priv, io),
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rsnd_src_get_out_rate(priv, io),
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NULL, &val, NULL);
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2014-05-09 07:44:49 +07:00
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val = val << shift;
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2017-12-20 13:11:59 +07:00
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mask = 0x0f1f << shift;
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2014-05-09 07:44:49 +07:00
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
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2014-05-09 07:44:49 +07:00
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return 0;
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}
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2016-03-07 12:09:14 +07:00
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int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate)
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2014-01-24 09:42:00 +07:00
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{
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2015-09-10 14:03:08 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2016-03-07 12:09:14 +07:00
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u32 in, out;
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u32 mask, en;
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2015-09-10 14:03:08 +07:00
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int id = rsnd_mod_id(src_mod);
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2014-01-24 09:42:00 +07:00
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int shift = (id % 2) ? 16 : 0;
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2015-09-10 14:03:08 +07:00
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rsnd_mod_confirm_src(src_mod);
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2016-03-07 12:09:14 +07:00
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rsnd_adg_get_timesel_ratio(priv, io,
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in_rate, out_rate,
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&in, &out, &en);
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2014-01-24 09:42:00 +07:00
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in = in << shift;
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out = out << shift;
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2017-12-20 13:11:59 +07:00
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mask = 0x0f1f << shift;
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2014-01-24 09:42:00 +07:00
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2018-12-12 14:03:58 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
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2014-01-24 09:42:00 +07:00
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2016-03-07 12:09:14 +07:00
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if (en)
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rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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2015-03-19 11:14:45 +07:00
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2014-02-12 12:04:12 +07:00
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return 0;
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2014-01-24 09:42:00 +07:00
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}
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2015-09-10 14:03:08 +07:00
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static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
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2013-07-22 11:36:46 +07:00
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{
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2015-09-10 14:03:08 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2017-10-13 13:03:06 +07:00
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struct device *dev = rsnd_priv_to_dev(priv);
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2015-09-10 14:03:08 +07:00
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int id = rsnd_mod_id(ssi_mod);
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2013-12-20 10:26:31 +07:00
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int shift = (id % 4) * 8;
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u32 mask = 0xFF << shift;
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2015-09-10 14:03:08 +07:00
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rsnd_mod_confirm_ssi(ssi_mod);
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2013-12-20 10:26:31 +07:00
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val = val << shift;
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2013-07-22 11:36:46 +07:00
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/*
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* SSI 8 is not connected to ADG.
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* it works with SSI 7
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*/
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if (id == 8)
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2013-12-20 10:26:31 +07:00
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return;
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2018-12-12 14:03:58 +07:00
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
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2017-10-13 13:03:06 +07:00
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dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
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2013-07-22 11:36:46 +07:00
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}
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ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
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int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
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2013-07-22 11:36:46 +07:00
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct clk *clk;
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2013-12-20 10:26:31 +07:00
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int i;
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2013-07-22 11:36:46 +07:00
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int sel_table[] = {
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[CLKA] = 0x1,
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[CLKB] = 0x2,
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[CLKC] = 0x3,
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[CLKI] = 0x0,
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};
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/*
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* find suitable clock from
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* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
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*/
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for_each_rsnd_clk(clk, adg, i) {
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ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
|
|
|
if (rate == clk_get_rate(clk))
|
|
|
|
return sel_table[i];
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2015-09-10 14:03:48 +07:00
|
|
|
* find divided clock from BRGA/BRGB
|
2013-07-22 11:36:46 +07:00
|
|
|
*/
|
ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
|
|
|
if (rate == adg->rbga_rate_for_441khz)
|
|
|
|
return 0x10;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
|
|
|
if (rate == adg->rbgb_rate_for_48khz)
|
|
|
|
return 0x20;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
return -EIO;
|
ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
|
|
|
|
{
|
|
|
|
rsnd_adg_set_ssi_clk(ssi_mod, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
|
|
|
|
{
|
|
|
|
struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
|
|
|
|
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
|
|
|
|
int data;
|
|
|
|
u32 ckr = 0;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
ASoC: rsnd: add rsnd_adg_clk_query()
Current Renesas sound driver is assuming that all Sampling rate and
channles are possible to use, but these are depends on inputed clock
and SSI connection situation.
For example, if it is using 1 SSI, enabled TDM mode and has 12288000
input clock, 2ch output can support until 192000Hz, but 6ch output can
support until 64000Hz, 8ch can support 48000Hz.
To control these situation correctly, it needs to support
hw_constraints / refine feature.
To support such feature, it needs SSI clock query feature, and it needs
ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start()
and it is doing similar things, but it try to setup ADG register in
same time. This is not needed.
This patch adds new rsnd_adg_clk_query() and separates query feature
and register setting feature in adg.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-06-15 07:49:43 +07:00
|
|
|
data = rsnd_adg_clk_query(priv, rate);
|
|
|
|
if (data < 0)
|
|
|
|
return data;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
2015-11-30 15:49:15 +07:00
|
|
|
rsnd_adg_set_ssi_clk(ssi_mod, data);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
2017-10-02 06:48:12 +07:00
|
|
|
if (rsnd_flags_has(adg, LRCLK_ASYNC)) {
|
|
|
|
if (rsnd_flags_has(adg, AUDIO_OUT_48))
|
2017-04-19 07:45:52 +07:00
|
|
|
ckr = 0x80000000;
|
|
|
|
} else {
|
2016-06-09 10:21:37 +07:00
|
|
|
if (0 == (rate % 8000))
|
|
|
|
ckr = 0x80000000;
|
|
|
|
}
|
|
|
|
|
2017-12-20 13:11:59 +07:00
|
|
|
rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr);
|
2016-12-07 07:28:11 +07:00
|
|
|
rsnd_mod_write(adg_mod, BRRA, adg->rbga);
|
|
|
|
rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
|
|
|
|
|
2017-10-13 13:03:06 +07:00
|
|
|
dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
|
|
|
|
(ckr) ? 'B' : 'A',
|
|
|
|
(ckr) ? adg->rbgb_rate_for_48khz :
|
|
|
|
adg->rbga_rate_for_441khz);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-12-07 07:29:02 +07:00
|
|
|
void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
|
|
|
|
{
|
|
|
|
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct clk *clk;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
ret = 0;
|
|
|
|
if (enable)
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
|
|
else
|
|
|
|
clk_disable_unprepare(clk);
|
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
dev_warn(dev, "can't use clk %d\n", i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-10 14:04:24 +07:00
|
|
|
static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
|
|
|
|
struct rsnd_adg *adg)
|
|
|
|
{
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct clk *clk;
|
2016-12-07 07:29:02 +07:00
|
|
|
int i;
|
2015-09-10 14:04:24 +07:00
|
|
|
|
|
|
|
for (i = 0; i < CLKMAX; i++) {
|
|
|
|
clk = devm_clk_get(dev, clk_name[i]);
|
|
|
|
adg->clk[i] = IS_ERR(clk) ? NULL : clk;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-10 14:04:45 +07:00
|
|
|
static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
|
|
|
|
struct rsnd_adg *adg)
|
2013-07-22 11:36:46 +07:00
|
|
|
{
|
|
|
|
struct clk *clk;
|
2015-09-10 14:03:48 +07:00
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
2015-09-10 14:04:45 +07:00
|
|
|
struct device_node *np = dev->of_node;
|
2017-04-19 07:45:52 +07:00
|
|
|
struct property *prop;
|
2015-09-10 14:03:48 +07:00
|
|
|
u32 ckr, rbgx, rbga, rbgb;
|
2017-04-19 07:45:52 +07:00
|
|
|
u32 rate, div;
|
|
|
|
#define REQ_SIZE 2
|
|
|
|
u32 req_rate[REQ_SIZE] = {};
|
2015-09-10 14:04:45 +07:00
|
|
|
uint32_t count = 0;
|
|
|
|
unsigned long req_48kHz_rate, req_441kHz_rate;
|
2017-04-19 07:45:52 +07:00
|
|
|
int i, req_size;
|
2015-09-10 14:04:45 +07:00
|
|
|
const char *parent_clk_name = NULL;
|
|
|
|
static const char * const clkout_name[] = {
|
|
|
|
[CLKOUT] = "audio_clkout",
|
|
|
|
[CLKOUT1] = "audio_clkout1",
|
|
|
|
[CLKOUT2] = "audio_clkout2",
|
|
|
|
[CLKOUT3] = "audio_clkout3",
|
|
|
|
};
|
2013-07-22 11:36:46 +07:00
|
|
|
int brg_table[] = {
|
|
|
|
[CLKA] = 0x0,
|
|
|
|
[CLKB] = 0x1,
|
|
|
|
[CLKC] = 0x4,
|
|
|
|
[CLKI] = 0x2,
|
|
|
|
};
|
|
|
|
|
2017-04-21 07:41:20 +07:00
|
|
|
ckr = 0;
|
|
|
|
rbga = 2; /* default 1/6 */
|
|
|
|
rbgb = 2; /* default 1/6 */
|
2015-09-10 14:04:45 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* ADG supports BRRA/BRRB output only
|
|
|
|
* this means all clkout0/1/2/3 will be same rate
|
|
|
|
*/
|
2017-04-21 12:02:57 +07:00
|
|
|
prop = of_find_property(np, "clock-frequency", NULL);
|
2017-04-21 07:41:20 +07:00
|
|
|
if (!prop)
|
|
|
|
goto rsnd_adg_get_clkout_end;
|
|
|
|
|
2017-04-19 07:45:52 +07:00
|
|
|
req_size = prop->length / sizeof(u32);
|
2018-09-06 10:21:33 +07:00
|
|
|
if (req_size > REQ_SIZE) {
|
|
|
|
dev_err(dev,
|
|
|
|
"too many clock-frequency, use top %d\n", REQ_SIZE);
|
|
|
|
req_size = REQ_SIZE;
|
|
|
|
}
|
2017-04-19 07:45:52 +07:00
|
|
|
|
|
|
|
of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
|
2015-09-10 14:04:45 +07:00
|
|
|
req_48kHz_rate = 0;
|
|
|
|
req_441kHz_rate = 0;
|
2017-04-19 07:45:52 +07:00
|
|
|
for (i = 0; i < req_size; i++) {
|
|
|
|
if (0 == (req_rate[i] % 44100))
|
|
|
|
req_441kHz_rate = req_rate[i];
|
|
|
|
if (0 == (req_rate[i] % 48000))
|
|
|
|
req_48kHz_rate = req_rate[i];
|
|
|
|
}
|
2015-09-10 14:04:45 +07:00
|
|
|
|
2017-04-21 07:41:20 +07:00
|
|
|
if (req_rate[0] % 48000 == 0)
|
2017-10-02 06:48:12 +07:00
|
|
|
rsnd_flags_set(adg, AUDIO_OUT_48);
|
2017-04-21 07:41:20 +07:00
|
|
|
|
2017-05-15 08:58:56 +07:00
|
|
|
if (of_get_property(np, "clkout-lr-asynchronous", NULL))
|
2017-10-02 06:48:12 +07:00
|
|
|
rsnd_flags_set(adg, LRCLK_ASYNC);
|
2017-05-15 08:58:56 +07:00
|
|
|
|
2013-07-22 11:36:46 +07:00
|
|
|
/*
|
|
|
|
* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
|
|
|
|
* have 44.1kHz or 48kHz base clocks for now.
|
|
|
|
*
|
|
|
|
* SSI itself can divide parent clock by 1/1 - 1/16
|
|
|
|
* see
|
|
|
|
* rsnd_adg_ssi_clk_try_start()
|
2015-09-10 14:03:25 +07:00
|
|
|
* rsnd_ssi_master_clk_start()
|
2013-07-22 11:36:46 +07:00
|
|
|
*/
|
2015-09-10 14:03:48 +07:00
|
|
|
adg->rbga_rate_for_441khz = 0;
|
|
|
|
adg->rbgb_rate_for_48khz = 0;
|
2013-07-22 11:36:46 +07:00
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
rate = clk_get_rate(clk);
|
|
|
|
|
|
|
|
if (0 == rate) /* not used */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* RBGA */
|
2015-09-10 14:03:48 +07:00
|
|
|
if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
|
|
|
|
div = 6;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_441kHz_rate)
|
|
|
|
div = rate / req_441kHz_rate;
|
2015-09-10 14:03:48 +07:00
|
|
|
rbgx = rsnd_adg_calculate_rbgx(div);
|
|
|
|
if (BRRx_MASK(rbgx) == rbgx) {
|
|
|
|
rbga = rbgx;
|
|
|
|
adg->rbga_rate_for_441khz = rate / div;
|
|
|
|
ckr |= brg_table[i] << 20;
|
2017-05-26 08:44:19 +07:00
|
|
|
if (req_441kHz_rate &&
|
2017-10-02 06:48:12 +07:00
|
|
|
!rsnd_flags_has(adg, AUDIO_OUT_48))
|
2015-09-10 14:04:45 +07:00
|
|
|
parent_clk_name = __clk_get_name(clk);
|
2015-09-10 14:03:48 +07:00
|
|
|
}
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* RBGB */
|
2015-09-10 14:03:48 +07:00
|
|
|
if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
|
|
|
|
div = 6;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_48kHz_rate)
|
|
|
|
div = rate / req_48kHz_rate;
|
2015-09-10 14:03:48 +07:00
|
|
|
rbgx = rsnd_adg_calculate_rbgx(div);
|
|
|
|
if (BRRx_MASK(rbgx) == rbgx) {
|
|
|
|
rbgb = rbgx;
|
|
|
|
adg->rbgb_rate_for_48khz = rate / div;
|
|
|
|
ckr |= brg_table[i] << 16;
|
2017-05-26 08:44:19 +07:00
|
|
|
if (req_48kHz_rate &&
|
2017-10-02 06:48:12 +07:00
|
|
|
rsnd_flags_has(adg, AUDIO_OUT_48))
|
2015-09-10 14:04:45 +07:00
|
|
|
parent_clk_name = __clk_get_name(clk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ADG supports BRRA/BRRB output only.
|
|
|
|
* this means all clkout0/1/2/3 will be * same rate
|
|
|
|
*/
|
|
|
|
|
2017-04-21 07:41:20 +07:00
|
|
|
of_property_read_u32(np, "#clock-cells", &count);
|
2015-09-10 14:04:45 +07:00
|
|
|
/*
|
|
|
|
* for clkout
|
|
|
|
*/
|
|
|
|
if (!count) {
|
2015-09-15 09:44:37 +07:00
|
|
|
clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
|
2017-04-19 07:45:52 +07:00
|
|
|
parent_clk_name, 0, req_rate[0]);
|
2015-09-10 14:04:45 +07:00
|
|
|
if (!IS_ERR(clk)) {
|
|
|
|
adg->clkout[CLKOUT] = clk;
|
|
|
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* for clkout0/1/2/3
|
|
|
|
*/
|
|
|
|
else {
|
|
|
|
for (i = 0; i < CLKOUTMAX; i++) {
|
|
|
|
clk = clk_register_fixed_rate(dev, clkout_name[i],
|
2016-04-20 08:08:00 +07:00
|
|
|
parent_clk_name, 0,
|
2017-04-19 07:45:52 +07:00
|
|
|
req_rate[0]);
|
2017-03-30 08:49:06 +07:00
|
|
|
if (!IS_ERR(clk))
|
2015-09-10 14:04:45 +07:00
|
|
|
adg->clkout[i] = clk;
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
2017-03-30 08:49:06 +07:00
|
|
|
adg->onecell.clks = adg->clkout;
|
|
|
|
adg->onecell.clk_num = CLKOUTMAX;
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get,
|
|
|
|
&adg->onecell);
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
|
2017-04-21 07:41:20 +07:00
|
|
|
rsnd_adg_get_clkout_end:
|
2016-12-07 07:28:11 +07:00
|
|
|
adg->ckr = ckr;
|
|
|
|
adg->rbga = rbga;
|
|
|
|
adg->rbgb = rbgb;
|
2017-10-13 13:03:06 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg)
|
|
|
|
{
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct clk *clk;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_rsnd_clk(clk, adg, i)
|
2018-09-06 10:22:01 +07:00
|
|
|
dev_dbg(dev, "%s : %pa : %ld\n",
|
2017-10-13 13:03:06 +07:00
|
|
|
clk_name[i], clk, clk_get_rate(clk));
|
2015-09-10 14:03:48 +07:00
|
|
|
|
2016-10-28 11:12:40 +07:00
|
|
|
dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
|
2017-10-13 13:03:06 +07:00
|
|
|
adg->ckr, adg->rbga, adg->rbgb);
|
|
|
|
dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
|
|
|
|
dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()
|
|
|
|
* by BRGCKR::BRGCKR_31
|
|
|
|
*/
|
|
|
|
for_each_rsnd_clkout(clk, adg, i)
|
2018-09-06 10:22:01 +07:00
|
|
|
dev_dbg(dev, "clkout %d : %pa : %ld\n", i,
|
2017-10-13 13:03:06 +07:00
|
|
|
clk, clk_get_rate(clk));
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
2017-10-13 13:03:06 +07:00
|
|
|
#else
|
|
|
|
#define rsnd_adg_clk_dbg_info(priv, adg)
|
|
|
|
#endif
|
2013-07-22 11:36:46 +07:00
|
|
|
|
2015-11-10 12:14:12 +07:00
|
|
|
int rsnd_adg_probe(struct rsnd_priv *priv)
|
2013-07-22 11:36:46 +07:00
|
|
|
{
|
|
|
|
struct rsnd_adg *adg;
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
2017-02-21 04:05:07 +07:00
|
|
|
int ret;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
|
2017-08-10 22:13:19 +07:00
|
|
|
if (!adg)
|
2013-07-22 11:36:46 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-02-21 04:05:07 +07:00
|
|
|
ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
|
2018-10-30 14:46:05 +07:00
|
|
|
NULL, 0, 0);
|
2017-02-21 04:05:07 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2015-09-10 14:02:39 +07:00
|
|
|
|
2015-09-10 14:04:24 +07:00
|
|
|
rsnd_adg_get_clkin(priv, adg);
|
2015-09-10 14:04:45 +07:00
|
|
|
rsnd_adg_get_clkout(priv, adg);
|
2017-10-13 13:03:06 +07:00
|
|
|
rsnd_adg_clk_dbg_info(priv, adg);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
priv->adg = adg;
|
|
|
|
|
2016-12-07 07:29:02 +07:00
|
|
|
rsnd_adg_clk_enable(priv);
|
|
|
|
|
2013-07-22 11:36:46 +07:00
|
|
|
return 0;
|
|
|
|
}
|
2015-11-05 15:51:15 +07:00
|
|
|
|
2015-11-10 12:14:12 +07:00
|
|
|
void rsnd_adg_remove(struct rsnd_priv *priv)
|
2015-11-05 15:51:15 +07:00
|
|
|
{
|
2017-03-30 08:49:27 +07:00
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct device_node *np = dev->of_node;
|
2017-08-02 17:26:09 +07:00
|
|
|
struct rsnd_adg *adg = priv->adg;
|
|
|
|
struct clk *clk;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_rsnd_clkout(clk, adg, i)
|
|
|
|
if (adg->clkout[i])
|
|
|
|
clk_unregister_fixed_rate(adg->clkout[i]);
|
2017-03-30 08:49:27 +07:00
|
|
|
|
|
|
|
of_clk_del_provider(np);
|
|
|
|
|
2016-12-07 07:29:02 +07:00
|
|
|
rsnd_adg_clk_disable(priv);
|
2015-11-05 15:51:15 +07:00
|
|
|
}
|