2013-07-22 11:36:46 +07:00
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/*
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* Helper routines for R-Car sound ADG.
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*
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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2015-09-10 14:04:45 +07:00
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#include <linux/clk-provider.h>
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2013-07-22 11:36:46 +07:00
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#include "rsnd.h"
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#define CLKA 0
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#define CLKB 1
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#define CLKC 2
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#define CLKI 3
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#define CLKMAX 4
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2015-09-10 14:04:45 +07:00
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#define CLKOUT 0
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#define CLKOUT1 1
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#define CLKOUT2 2
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#define CLKOUT3 3
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#define CLKOUTMAX 4
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2015-09-10 14:03:48 +07:00
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#define BRRx_MASK(x) (0x3FF & x)
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2015-09-10 14:02:39 +07:00
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static struct rsnd_mod_ops adg_ops = {
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.name = "adg",
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};
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2013-07-22 11:36:46 +07:00
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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2015-09-10 14:04:45 +07:00
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struct clk *clkout[CLKOUTMAX];
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struct clk_onecell_data onecell;
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2015-09-10 14:02:39 +07:00
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struct rsnd_mod mod;
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2016-06-09 10:21:37 +07:00
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u32 flags;
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2013-07-22 11:36:46 +07:00
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2015-09-10 14:03:48 +07:00
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int rbga_rate_for_441khz; /* RBGA */
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int rbgb_rate_for_48khz; /* RBGB */
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2013-07-22 11:36:46 +07:00
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};
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2016-06-09 10:21:37 +07:00
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#define LRCLK_ASYNC (1 << 0)
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#define adg_mode_flags(adg) (adg->flags)
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2013-07-22 11:36:46 +07:00
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#define for_each_rsnd_clk(pos, adg, i) \
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2014-02-12 08:15:51 +07:00
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for (i = 0; \
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(i < CLKMAX) && \
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((pos) = adg->clk[i]); \
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i++)
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2015-09-10 14:04:45 +07:00
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#define for_each_rsnd_clkout(pos, adg, i) \
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for (i = 0; \
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(i < CLKOUTMAX) && \
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((pos) = adg->clkout[i]); \
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i++)
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2013-07-22 11:36:46 +07:00
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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2015-09-10 14:03:48 +07:00
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static u32 rsnd_adg_calculate_rbgx(unsigned long div)
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{
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int i, ratio;
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if (!div)
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return 0;
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for (i = 3; i >= 0; i--) {
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ratio = 2 << (i * 2);
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if (0 == (div % ratio))
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return (u32)((i << 8) | ((div / ratio) - 1));
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}
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return ~0;
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}
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2014-01-24 09:42:00 +07:00
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2014-03-03 14:43:33 +07:00
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static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
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2014-01-24 09:42:00 +07:00
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{
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2015-11-30 15:49:15 +07:00
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struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
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int id = rsnd_mod_id(ssi_mod);
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2014-01-24 09:42:00 +07:00
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int ws = id;
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2015-10-22 10:15:46 +07:00
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if (rsnd_ssi_is_pin_sharing(io)) {
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2014-01-24 09:42:00 +07:00
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switch (id) {
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case 1:
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case 2:
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ws = 0;
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break;
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case 4:
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ws = 3;
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break;
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case 8:
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ws = 7;
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break;
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}
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}
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return (0x6 + ws) << 8;
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}
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2016-03-07 12:09:14 +07:00
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static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int target_rate,
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unsigned int *target_val,
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unsigned int *target_en)
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, step;
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unsigned int val, en;
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unsigned int min, diff;
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unsigned int sel_rate[] = {
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clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
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adg->rbga_rate_for_441khz, /* 0011: RBGA */
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adg->rbgb_rate_for_48khz, /* 0100: RBGB */
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};
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min = ~0;
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val = 0;
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en = 0;
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
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idx = 0;
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step = 2;
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if (!sel_rate[sel])
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continue;
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for (div = 2; div <= 98304; div += step) {
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diff = abs(target_rate - sel_rate[sel] / div);
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if (min > diff) {
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val = (sel << 8) | idx;
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min = diff;
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en = 1 << (sel + 1); /* fixme */
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}
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/*
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* step of 0_0000 / 0_0001 / 0_1101
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* are out of order
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*/
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if ((idx > 2) && (idx % 2))
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step *= 2;
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if (idx == 0x1c) {
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div += step;
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step *= 2;
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}
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idx++;
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}
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}
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if (min == ~0) {
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dev_err(dev, "no Input clock\n");
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return;
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}
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*target_val = val;
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if (target_en)
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*target_en = en;
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}
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static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate,
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u32 *in, u32 *out, u32 *en)
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{
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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unsigned int target_rate;
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u32 *target_val;
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u32 _in;
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u32 _out;
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u32 _en;
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/* default = SSI WS */
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_in =
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_out = rsnd_adg_ssi_ws_timing_gen2(io);
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target_rate = 0;
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target_val = NULL;
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_en = 0;
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if (runtime->rate != in_rate) {
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target_rate = out_rate;
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target_val = &_out;
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} else if (runtime->rate != out_rate) {
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target_rate = in_rate;
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target_val = &_in;
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}
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if (target_rate)
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__rsnd_adg_get_timesel_ratio(priv, io,
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target_rate,
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target_val, &_en);
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if (in)
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*in = _in;
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if (out)
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*out = _out;
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if (en)
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*en = _en;
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}
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2015-11-30 15:49:15 +07:00
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
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2014-05-09 07:44:49 +07:00
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struct rsnd_dai_stream *io)
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{
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2015-11-30 15:49:15 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2015-11-30 15:49:15 +07:00
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int id = rsnd_mod_id(cmd_mod);
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2014-05-09 07:44:49 +07:00
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int shift = (id % 2) ? 16 : 0;
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u32 mask, val;
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2016-03-07 12:09:34 +07:00
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rsnd_adg_get_timesel_ratio(priv, io,
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rsnd_src_get_in_rate(priv, io),
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rsnd_src_get_out_rate(priv, io),
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NULL, &val, NULL);
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2014-05-09 07:44:49 +07:00
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val = val << shift;
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mask = 0xffff << shift;
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
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2014-05-09 07:44:49 +07:00
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return 0;
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}
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2016-03-07 12:09:14 +07:00
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int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate)
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2014-01-24 09:42:00 +07:00
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{
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2015-09-10 14:03:08 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2016-03-07 12:09:14 +07:00
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u32 in, out;
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u32 mask, en;
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2015-09-10 14:03:08 +07:00
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int id = rsnd_mod_id(src_mod);
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2014-01-24 09:42:00 +07:00
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int shift = (id % 2) ? 16 : 0;
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2015-09-10 14:03:08 +07:00
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rsnd_mod_confirm_src(src_mod);
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2016-03-07 12:09:14 +07:00
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rsnd_adg_get_timesel_ratio(priv, io,
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in_rate, out_rate,
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&in, &out, &en);
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2014-01-24 09:42:00 +07:00
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in = in << shift;
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out = out << shift;
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mask = 0xffff << shift;
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switch (id / 2) {
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case 0:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
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2014-01-24 09:42:00 +07:00
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break;
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case 1:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
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2014-01-24 09:42:00 +07:00
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break;
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case 2:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
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2014-01-24 09:42:00 +07:00
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break;
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case 3:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
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2014-01-24 09:42:00 +07:00
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break;
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case 4:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
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2014-01-24 09:42:00 +07:00
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break;
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}
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2016-03-07 12:09:14 +07:00
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if (en)
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rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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2015-03-19 11:14:45 +07:00
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2014-02-12 12:04:12 +07:00
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return 0;
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2014-01-24 09:42:00 +07:00
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}
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2015-09-10 14:03:08 +07:00
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static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
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2013-07-22 11:36:46 +07:00
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{
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2015-09-10 14:03:08 +07:00
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
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2015-09-10 14:02:39 +07:00
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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2015-09-10 14:03:08 +07:00
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int id = rsnd_mod_id(ssi_mod);
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2013-12-20 10:26:31 +07:00
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int shift = (id % 4) * 8;
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u32 mask = 0xFF << shift;
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2015-09-10 14:03:08 +07:00
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rsnd_mod_confirm_ssi(ssi_mod);
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2013-12-20 10:26:31 +07:00
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val = val << shift;
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2013-07-22 11:36:46 +07:00
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/*
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* SSI 8 is not connected to ADG.
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* it works with SSI 7
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*/
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if (id == 8)
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2013-12-20 10:26:31 +07:00
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return;
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switch (id / 4) {
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case 0:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
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2013-12-20 10:26:31 +07:00
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break;
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case 1:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
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2013-12-20 10:26:31 +07:00
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break;
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case 2:
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2015-09-10 14:02:39 +07:00
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
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2013-12-20 10:26:31 +07:00
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break;
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}
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2013-07-22 11:36:46 +07:00
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}
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2015-11-30 15:49:15 +07:00
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int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
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2013-07-22 11:36:46 +07:00
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{
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2015-11-30 15:49:15 +07:00
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rsnd_adg_set_ssi_clk(ssi_mod, 0);
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2013-07-22 11:36:46 +07:00
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return 0;
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}
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2015-11-30 15:49:15 +07:00
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
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2013-07-22 11:36:46 +07:00
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|
|
{
|
2015-11-30 15:49:15 +07:00
|
|
|
struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
|
2013-07-22 11:36:46 +07:00
|
|
|
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct clk *clk;
|
2013-12-20 10:26:31 +07:00
|
|
|
int i;
|
2013-07-22 11:36:46 +07:00
|
|
|
u32 data;
|
|
|
|
int sel_table[] = {
|
|
|
|
[CLKA] = 0x1,
|
|
|
|
[CLKB] = 0x2,
|
|
|
|
[CLKC] = 0x3,
|
|
|
|
[CLKI] = 0x0,
|
|
|
|
};
|
|
|
|
|
|
|
|
dev_dbg(dev, "request clock = %d\n", rate);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* find suitable clock from
|
|
|
|
* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
|
|
|
|
*/
|
|
|
|
data = 0;
|
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
if (rate == clk_get_rate(clk)) {
|
|
|
|
data = sel_table[i];
|
|
|
|
goto found_clock;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2015-09-10 14:03:48 +07:00
|
|
|
* find divided clock from BRGA/BRGB
|
2013-07-22 11:36:46 +07:00
|
|
|
*/
|
2015-09-10 14:03:48 +07:00
|
|
|
if (rate == adg->rbga_rate_for_441khz) {
|
2013-07-22 11:36:46 +07:00
|
|
|
data = 0x10;
|
|
|
|
goto found_clock;
|
|
|
|
}
|
|
|
|
|
2015-09-10 14:03:48 +07:00
|
|
|
if (rate == adg->rbgb_rate_for_48khz) {
|
2013-07-22 11:36:46 +07:00
|
|
|
data = 0x20;
|
|
|
|
goto found_clock;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
found_clock:
|
|
|
|
|
2015-11-30 15:49:15 +07:00
|
|
|
rsnd_adg_set_ssi_clk(ssi_mod, data);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
2016-06-09 10:21:37 +07:00
|
|
|
if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
|
|
|
|
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
|
|
|
|
u32 ckr = 0;
|
|
|
|
|
|
|
|
if (0 == (rate % 8000))
|
|
|
|
ckr = 0x80000000;
|
|
|
|
|
2016-10-28 11:12:40 +07:00
|
|
|
rsnd_mod_bset(adg_mod, BRGCKR, 0x80000000, ckr);
|
2016-06-09 10:21:37 +07:00
|
|
|
}
|
|
|
|
|
2015-09-10 14:04:06 +07:00
|
|
|
dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
|
2015-11-30 15:49:15 +07:00
|
|
|
rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
|
2015-09-10 14:04:06 +07:00
|
|
|
data, rate);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-09-10 14:04:24 +07:00
|
|
|
static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
|
|
|
|
struct rsnd_adg *adg)
|
|
|
|
{
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
|
|
|
struct clk *clk;
|
|
|
|
static const char * const clk_name[] = {
|
|
|
|
[CLKA] = "clk_a",
|
|
|
|
[CLKB] = "clk_b",
|
|
|
|
[CLKC] = "clk_c",
|
|
|
|
[CLKI] = "clk_i",
|
|
|
|
};
|
2015-11-05 15:51:15 +07:00
|
|
|
int i, ret;
|
2015-09-10 14:04:24 +07:00
|
|
|
|
|
|
|
for (i = 0; i < CLKMAX; i++) {
|
|
|
|
clk = devm_clk_get(dev, clk_name[i]);
|
|
|
|
adg->clk[i] = IS_ERR(clk) ? NULL : clk;
|
|
|
|
}
|
|
|
|
|
2015-11-05 15:51:15 +07:00
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_warn(dev, "can't use clk %d\n", i);
|
|
|
|
|
2015-09-10 14:04:24 +07:00
|
|
|
dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
|
2015-11-05 15:51:15 +07:00
|
|
|
}
|
2015-09-10 14:04:24 +07:00
|
|
|
}
|
|
|
|
|
2015-09-10 14:04:45 +07:00
|
|
|
static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
|
|
|
|
struct rsnd_adg *adg)
|
2013-07-22 11:36:46 +07:00
|
|
|
{
|
|
|
|
struct clk *clk;
|
2015-09-10 14:03:25 +07:00
|
|
|
struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
|
2015-09-10 14:03:48 +07:00
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
2015-09-10 14:04:45 +07:00
|
|
|
struct device_node *np = dev->of_node;
|
2015-09-10 14:03:48 +07:00
|
|
|
u32 ckr, rbgx, rbga, rbgb;
|
2015-10-28 22:03:48 +07:00
|
|
|
u32 rate, req_rate = 0, div;
|
2015-09-10 14:04:45 +07:00
|
|
|
uint32_t count = 0;
|
|
|
|
unsigned long req_48kHz_rate, req_441kHz_rate;
|
2013-07-22 11:36:46 +07:00
|
|
|
int i;
|
2015-09-10 14:04:45 +07:00
|
|
|
const char *parent_clk_name = NULL;
|
|
|
|
static const char * const clkout_name[] = {
|
|
|
|
[CLKOUT] = "audio_clkout",
|
|
|
|
[CLKOUT1] = "audio_clkout1",
|
|
|
|
[CLKOUT2] = "audio_clkout2",
|
|
|
|
[CLKOUT3] = "audio_clkout3",
|
|
|
|
};
|
2013-07-22 11:36:46 +07:00
|
|
|
int brg_table[] = {
|
|
|
|
[CLKA] = 0x0,
|
|
|
|
[CLKB] = 0x1,
|
|
|
|
[CLKC] = 0x4,
|
|
|
|
[CLKI] = 0x2,
|
|
|
|
};
|
|
|
|
|
2015-09-10 14:04:45 +07:00
|
|
|
of_property_read_u32(np, "#clock-cells", &count);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ADG supports BRRA/BRRB output only
|
|
|
|
* this means all clkout0/1/2/3 will be same rate
|
|
|
|
*/
|
|
|
|
of_property_read_u32(np, "clock-frequency", &req_rate);
|
|
|
|
req_48kHz_rate = 0;
|
|
|
|
req_441kHz_rate = 0;
|
|
|
|
if (0 == (req_rate % 44100))
|
|
|
|
req_441kHz_rate = req_rate;
|
|
|
|
if (0 == (req_rate % 48000))
|
|
|
|
req_48kHz_rate = req_rate;
|
|
|
|
|
2013-07-22 11:36:46 +07:00
|
|
|
/*
|
|
|
|
* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
|
|
|
|
* have 44.1kHz or 48kHz base clocks for now.
|
|
|
|
*
|
|
|
|
* SSI itself can divide parent clock by 1/1 - 1/16
|
|
|
|
* see
|
|
|
|
* rsnd_adg_ssi_clk_try_start()
|
2015-09-10 14:03:25 +07:00
|
|
|
* rsnd_ssi_master_clk_start()
|
2013-07-22 11:36:46 +07:00
|
|
|
*/
|
|
|
|
ckr = 0;
|
2015-09-10 14:03:48 +07:00
|
|
|
rbga = 2; /* default 1/6 */
|
|
|
|
rbgb = 2; /* default 1/6 */
|
|
|
|
adg->rbga_rate_for_441khz = 0;
|
|
|
|
adg->rbgb_rate_for_48khz = 0;
|
2013-07-22 11:36:46 +07:00
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
rate = clk_get_rate(clk);
|
|
|
|
|
|
|
|
if (0 == rate) /* not used */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* RBGA */
|
2015-09-10 14:03:48 +07:00
|
|
|
if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
|
|
|
|
div = 6;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_441kHz_rate)
|
|
|
|
div = rate / req_441kHz_rate;
|
2015-09-10 14:03:48 +07:00
|
|
|
rbgx = rsnd_adg_calculate_rbgx(div);
|
|
|
|
if (BRRx_MASK(rbgx) == rbgx) {
|
|
|
|
rbga = rbgx;
|
|
|
|
adg->rbga_rate_for_441khz = rate / div;
|
|
|
|
ckr |= brg_table[i] << 20;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_441kHz_rate)
|
|
|
|
parent_clk_name = __clk_get_name(clk);
|
2015-09-10 14:03:48 +07:00
|
|
|
}
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* RBGB */
|
2015-09-10 14:03:48 +07:00
|
|
|
if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
|
|
|
|
div = 6;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_48kHz_rate)
|
|
|
|
div = rate / req_48kHz_rate;
|
2015-09-10 14:03:48 +07:00
|
|
|
rbgx = rsnd_adg_calculate_rbgx(div);
|
|
|
|
if (BRRx_MASK(rbgx) == rbgx) {
|
|
|
|
rbgb = rbgx;
|
|
|
|
adg->rbgb_rate_for_48khz = rate / div;
|
|
|
|
ckr |= brg_table[i] << 16;
|
2015-09-10 14:04:45 +07:00
|
|
|
if (req_48kHz_rate) {
|
|
|
|
parent_clk_name = __clk_get_name(clk);
|
|
|
|
ckr |= 0x80000000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ADG supports BRRA/BRRB output only.
|
|
|
|
* this means all clkout0/1/2/3 will be * same rate
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* for clkout
|
|
|
|
*/
|
|
|
|
if (!count) {
|
2015-09-15 09:44:37 +07:00
|
|
|
clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
|
2016-04-20 08:08:00 +07:00
|
|
|
parent_clk_name, 0, req_rate);
|
2015-09-10 14:04:45 +07:00
|
|
|
if (!IS_ERR(clk)) {
|
|
|
|
adg->clkout[CLKOUT] = clk;
|
|
|
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* for clkout0/1/2/3
|
|
|
|
*/
|
|
|
|
else {
|
|
|
|
for (i = 0; i < CLKOUTMAX; i++) {
|
|
|
|
clk = clk_register_fixed_rate(dev, clkout_name[i],
|
2016-04-20 08:08:00 +07:00
|
|
|
parent_clk_name, 0,
|
2015-09-10 14:04:45 +07:00
|
|
|
req_rate);
|
|
|
|
if (!IS_ERR(clk)) {
|
|
|
|
adg->onecell.clks = adg->clkout;
|
|
|
|
adg->onecell.clk_num = CLKOUTMAX;
|
|
|
|
|
|
|
|
adg->clkout[i] = clk;
|
|
|
|
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get,
|
|
|
|
&adg->onecell);
|
2015-09-10 14:03:48 +07:00
|
|
|
}
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-28 11:12:40 +07:00
|
|
|
rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, ckr);
|
2015-09-10 14:03:48 +07:00
|
|
|
rsnd_mod_write(adg_mod, BRRA, rbga);
|
|
|
|
rsnd_mod_write(adg_mod, BRRB, rbgb);
|
|
|
|
|
2015-09-10 14:04:45 +07:00
|
|
|
for_each_rsnd_clkout(clk, adg, i)
|
|
|
|
dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
|
2016-10-28 11:12:40 +07:00
|
|
|
dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
|
2015-09-10 14:03:48 +07:00
|
|
|
ckr, rbga, rbgb);
|
2013-07-22 11:36:46 +07:00
|
|
|
}
|
|
|
|
|
2015-11-10 12:14:12 +07:00
|
|
|
int rsnd_adg_probe(struct rsnd_priv *priv)
|
2013-07-22 11:36:46 +07:00
|
|
|
{
|
|
|
|
struct rsnd_adg *adg;
|
|
|
|
struct device *dev = rsnd_priv_to_dev(priv);
|
2016-06-09 10:21:37 +07:00
|
|
|
struct device_node *np = dev->of_node;
|
2013-07-22 11:36:46 +07:00
|
|
|
|
|
|
|
adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
|
|
|
|
if (!adg) {
|
|
|
|
dev_err(dev, "ADG allocate failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-01-21 08:55:39 +07:00
|
|
|
rsnd_mod_init(priv, &adg->mod, &adg_ops,
|
2016-01-21 08:58:07 +07:00
|
|
|
NULL, NULL, 0, 0);
|
2015-09-10 14:02:39 +07:00
|
|
|
|
2015-09-10 14:04:24 +07:00
|
|
|
rsnd_adg_get_clkin(priv, adg);
|
2015-09-10 14:04:45 +07:00
|
|
|
rsnd_adg_get_clkout(priv, adg);
|
2013-07-22 11:36:46 +07:00
|
|
|
|
2016-06-09 10:21:37 +07:00
|
|
|
if (of_get_property(np, "clkout-lr-asynchronous", NULL))
|
|
|
|
adg->flags = LRCLK_ASYNC;
|
|
|
|
|
2013-07-22 11:36:46 +07:00
|
|
|
priv->adg = adg;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-11-05 15:51:15 +07:00
|
|
|
|
2015-11-10 12:14:12 +07:00
|
|
|
void rsnd_adg_remove(struct rsnd_priv *priv)
|
2015-11-05 15:51:15 +07:00
|
|
|
{
|
|
|
|
struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
|
|
|
|
struct clk *clk;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_rsnd_clk(clk, adg, i) {
|
|
|
|
clk_disable_unprepare(clk);
|
|
|
|
}
|
|
|
|
}
|