License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2015-02-07 13:57:52 +07:00
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/*
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* dts file for Hisilicon Hi6220 SoC
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*
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* Copyright (C) 2015, Hisilicon Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2016-06-20 10:50:05 +07:00
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#include <dt-bindings/reset/hisi,hi6220-resets.h>
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2015-10-01 08:19:48 +07:00
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#include <dt-bindings/clock/hi6220-clock.h>
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2016-04-13 06:55:41 +07:00
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#include <dt-bindings/pinctrl/hisi.h>
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2016-03-29 18:27:15 +07:00
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#include <dt-bindings/thermal/thermal.h>
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2015-02-07 13:57:52 +07:00
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/ {
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compatible = "hisilicon,hi6220";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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2016-04-13 06:55:39 +07:00
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <700>;
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exit-latency-us = <250>;
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min-residency-us = <1000>;
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};
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CLUSTER_SLEEP: cluster-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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};
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2015-02-07 13:57:52 +07:00
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER0_L2>;
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2016-04-13 06:55:47 +07:00
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clocks = <&stub_clock 0>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2016-03-29 18:27:15 +07:00
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dynamic-power-coefficient = <311>;
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2015-02-07 13:57:52 +07:00
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER0_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER0_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER0_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x100>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER1_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x101>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER1_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x102>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER1_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x103>;
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enable-method = "psci";
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2016-02-26 12:28:34 +07:00
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next-level-cache = <&CLUSTER1_L2>;
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2016-04-13 06:55:47 +07:00
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operating-points-v2 = <&cpu_opp_table>;
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2016-04-13 06:55:39 +07:00
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cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
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2015-02-07 13:57:52 +07:00
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};
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2016-02-26 12:28:34 +07:00
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CLUSTER0_L2: l2-cache0 {
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compatible = "cache";
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};
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CLUSTER1_L2: l2-cache1 {
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compatible = "cache";
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};
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2015-02-07 13:57:52 +07:00
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};
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2016-04-13 06:55:47 +07:00
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cpu_opp_table: cpu_opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <208000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <500000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <432000000>;
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opp-microvolt = <1040000>;
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clock-latency-ns = <500000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <729000000>;
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opp-microvolt = <1090000>;
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clock-latency-ns = <500000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <960000000>;
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opp-microvolt = <1180000>;
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clock-latency-ns = <500000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1330000>;
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clock-latency-ns = <500000>;
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};
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};
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2015-02-07 13:57:52 +07:00
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gic: interrupt-controller@f6801000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
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<0x0 0xf6802000 0 0x2000>, /* GICC */
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<0x0 0xf6804000 0 0x2000>, /* GICH */
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<0x0 0xf6806000 0 0x2000>; /* GICV */
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
2016-04-13 06:55:47 +07:00
|
|
|
sram: sram@fff80000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-sramctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xfff80000 0x0 0x12000>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-02-07 13:57:52 +07:00
|
|
|
ao_ctrl: ao_ctrl@f7800000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-aoctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xf7800000 0x0 0x2000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sys_ctrl: sys_ctrl@f7030000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-sysctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xf7030000 0x0 0x2000>;
|
|
|
|
|
#clock-cells = <1>;
|
2015-11-20 09:10:06 +07:00
|
|
|
#reset-cells = <1>;
|
2015-02-07 13:57:52 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
media_ctrl: media_ctrl@f4410000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-mediactrl", "syscon";
|
|
|
|
|
reg = <0x0 0xf4410000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
2016-06-20 10:50:05 +07:00
|
|
|
#reset-cells = <1>;
|
2015-02-07 13:57:52 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pm_ctrl: pm_ctrl@f7032000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-pmctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xf7032000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-08-16 14:26:35 +07:00
|
|
|
acpu_sctrl: acpu_sctrl@f6504000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
|
|
|
|
|
reg = <0x0 0xf6504000 0x0 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-08-23 05:48:02 +07:00
|
|
|
medianoc_ade: medianoc_ade@f4520000 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x0 0xf4520000 0x0 0x4000>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-13 06:55:47 +07:00
|
|
|
stub_clock: stub_clock {
|
|
|
|
|
compatible = "hisilicon,hi6220-stub-clk";
|
|
|
|
|
hisilicon,hi6220-clk-sram = <&sram>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
mbox-names = "mbox-tx";
|
|
|
|
|
mboxes = <&mailbox 1 0 11>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-02-07 13:57:52 +07:00
|
|
|
uart0: uart@f8015000 { /* console */
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8015000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
2015-10-01 08:19:48 +07:00
|
|
|
clocks = <&ao_ctrl HI6220_UART0_PCLK>,
|
|
|
|
|
<&ao_ctrl HI6220_UART0_PCLK>;
|
2015-02-07 13:57:52 +07:00
|
|
|
clock-names = "uartclk", "apb_pclk";
|
|
|
|
|
};
|
2015-10-01 08:19:48 +07:00
|
|
|
|
|
|
|
|
uart1: uart@f7111000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7111000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_UART1_PCLK>,
|
|
|
|
|
<&sys_ctrl HI6220_UART1_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
2016-04-13 06:55:48 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
|
2015-10-01 08:19:48 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: uart@f7112000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7112000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_UART2_PCLK>,
|
|
|
|
|
<&sys_ctrl HI6220_UART2_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
2016-04-13 06:55:48 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
|
2015-10-01 08:19:48 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: uart@f7113000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7113000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_UART3_PCLK>,
|
|
|
|
|
<&sys_ctrl HI6220_UART3_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
2016-04-13 06:55:48 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
|
|
|
|
|
status = "disabled";
|
2015-10-01 08:19:48 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: uart@f7114000 {
|
|
|
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7114000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_UART4_PCLK>,
|
|
|
|
|
<&sys_ctrl HI6220_UART4_PCLK>;
|
|
|
|
|
clock-names = "uartclk", "apb_pclk";
|
2016-04-13 06:55:48 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
|
2015-10-01 08:19:48 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2016-04-13 06:55:38 +07:00
|
|
|
|
2017-06-15 01:25:17 +07:00
|
|
|
dma0: dma@f7370000 {
|
|
|
|
|
compatible = "hisilicon,k3-dma-1.0";
|
|
|
|
|
reg = <0x0 0xf7370000 0x0 0x1000>;
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <15>;
|
|
|
|
|
dma-requests = <32>;
|
|
|
|
|
interrupts = <0 84 4>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
|
|
|
|
|
dma-no-cci;
|
|
|
|
|
dma-type = "hi6220_dma";
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-13 06:55:38 +07:00
|
|
|
dual_timer0: timer@f8008000 {
|
|
|
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8008000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
|
|
|
|
|
<&ao_ctrl HI6220_TIMER0_PCLK>,
|
|
|
|
|
<&ao_ctrl HI6220_TIMER0_PCLK>;
|
|
|
|
|
clock-names = "timer1", "timer2", "apb_pclk";
|
|
|
|
|
};
|
2016-04-13 06:55:40 +07:00
|
|
|
|
2016-06-30 07:48:45 +07:00
|
|
|
rtc0: rtc@f8003000 {
|
|
|
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8003000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 12 4>;
|
|
|
|
|
clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtc1: rtc@f8004000 {
|
|
|
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8004000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 8 4>;
|
|
|
|
|
clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-13 06:55:41 +07:00
|
|
|
pmx0: pinmux@f7010000 {
|
|
|
|
|
compatible = "pinctrl-single";
|
|
|
|
|
reg = <0x0 0xf7010000 0x0 0x27c>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2016-11-07 22:27:49 +07:00
|
|
|
#pinctrl-cells = <1>;
|
2016-04-13 06:55:41 +07:00
|
|
|
#gpio-range-cells = <3>;
|
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
pinctrl-single,function-mask = <7>;
|
|
|
|
|
pinctrl-single,gpio-range = <
|
|
|
|
|
&range 80 8 MUX_M0 /* gpio 3: [0..7] */
|
|
|
|
|
&range 88 8 MUX_M0 /* gpio 4: [0..7] */
|
|
|
|
|
&range 96 8 MUX_M0 /* gpio 5: [0..7] */
|
|
|
|
|
&range 104 8 MUX_M0 /* gpio 6: [0..7] */
|
|
|
|
|
&range 112 8 MUX_M0 /* gpio 7: [0..7] */
|
|
|
|
|
&range 120 2 MUX_M0 /* gpio 8: [0..1] */
|
|
|
|
|
&range 2 6 MUX_M1 /* gpio 8: [2..7] */
|
|
|
|
|
&range 8 8 MUX_M1 /* gpio 9: [0..7] */
|
|
|
|
|
&range 0 1 MUX_M1 /* gpio 10: [0] */
|
|
|
|
|
&range 16 7 MUX_M1 /* gpio 10: [1..7] */
|
|
|
|
|
&range 23 3 MUX_M1 /* gpio 11: [0..2] */
|
|
|
|
|
&range 28 5 MUX_M1 /* gpio 11: [3..7] */
|
|
|
|
|
&range 33 3 MUX_M1 /* gpio 12: [0..2] */
|
|
|
|
|
&range 43 5 MUX_M1 /* gpio 12: [3..7] */
|
|
|
|
|
&range 48 8 MUX_M1 /* gpio 13: [0..7] */
|
|
|
|
|
&range 56 8 MUX_M1 /* gpio 14: [0..7] */
|
|
|
|
|
&range 74 6 MUX_M1 /* gpio 15: [0..5] */
|
|
|
|
|
&range 122 1 MUX_M1 /* gpio 15: [6] */
|
|
|
|
|
&range 126 1 MUX_M1 /* gpio 15: [7] */
|
|
|
|
|
&range 127 8 MUX_M1 /* gpio 16: [0..7] */
|
|
|
|
|
&range 135 8 MUX_M1 /* gpio 17: [0..7] */
|
|
|
|
|
&range 143 8 MUX_M1 /* gpio 18: [0..7] */
|
|
|
|
|
&range 151 8 MUX_M1 /* gpio 19: [0..7] */
|
|
|
|
|
>;
|
|
|
|
|
range: gpio-range {
|
|
|
|
|
#pinctrl-single,gpio-range-cells = <3>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx1: pinmux@f7010800 {
|
|
|
|
|
compatible = "pinconf-single";
|
|
|
|
|
reg = <0x0 0xf7010800 0x0 0x28c>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2016-11-07 22:27:49 +07:00
|
|
|
#pinctrl-cells = <1>;
|
2016-04-13 06:55:41 +07:00
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmx2: pinmux@f8001800 {
|
|
|
|
|
compatible = "pinconf-single";
|
|
|
|
|
reg = <0x0 0xf8001800 0x0 0x78>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2016-11-07 22:27:49 +07:00
|
|
|
#pinctrl-cells = <1>;
|
2016-04-13 06:55:41 +07:00
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-04-13 06:55:40 +07:00
|
|
|
gpio0: gpio@f8011000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8011000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 52 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1: gpio@f8012000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8012000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 53 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@f8013000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8013000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 54 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@f8014000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8014000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 55 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 80 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio4: gpio@f7020000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7020000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 56 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 88 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5: gpio@f7021000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7021000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 57 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 96 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio6: gpio@f7022000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7022000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 58 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 104 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio7: gpio@f7023000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7023000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 59 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 112 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio8: gpio@f7024000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7024000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 60 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio9: gpio@f7025000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7025000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 61 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 8 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio10: gpio@f7026000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7026000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 62 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio11: gpio@f7027000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7027000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 63 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio12: gpio@f7028000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7028000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 64 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio13: gpio@f7029000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7029000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 65 0x4>;
|
|
|
|
|
gpio-controller;
|
2016-04-13 06:55:41 +07:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-ranges = <&pmx0 0 48 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio14: gpio@f702a000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702a000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 66 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 56 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio15: gpio@f702b000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702b000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 67 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <
|
|
|
|
|
&pmx0 0 74 6
|
|
|
|
|
&pmx0 6 122 1
|
|
|
|
|
&pmx0 7 126 1
|
|
|
|
|
>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio16: gpio@f702c000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702c000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 68 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 127 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio17: gpio@f702d000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702d000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 69 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 135 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio18: gpio@f702e000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702e000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 70 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 143 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio19: gpio@f702f000 {
|
|
|
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf702f000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 71 0x4>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2016-04-13 06:55:41 +07:00
|
|
|
gpio-ranges = <&pmx0 0 151 8>;
|
2016-04-13 06:55:40 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
clocks = <&ao_ctrl 2>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
2016-04-13 06:55:42 +07:00
|
|
|
|
|
|
|
|
spi0: spi@f7106000 {
|
|
|
|
|
compatible = "arm,pl022", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf7106000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 50 4>;
|
|
|
|
|
bus-id = <0>;
|
|
|
|
|
enable-dma = <0>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_SPI_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
|
|
|
|
|
num-cs = <1>;
|
|
|
|
|
cs-gpios = <&gpio6 2 0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2016-04-13 06:55:43 +07:00
|
|
|
|
|
|
|
|
i2c0: i2c@f7100000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xf7100000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0 44 4>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_I2C0_CLK>;
|
|
|
|
|
i2c-sda-hold-time-ns = <300>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@f7101000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xf7101000 0x0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_I2C1_CLK>;
|
|
|
|
|
interrupts = <0 45 4>;
|
|
|
|
|
i2c-sda-hold-time-ns = <300>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@f7102000 {
|
|
|
|
|
compatible = "snps,designware-i2c";
|
|
|
|
|
reg = <0x0 0xf7102000 0x0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_I2C2_CLK>;
|
|
|
|
|
interrupts = <0 46 4>;
|
|
|
|
|
i2c-sda-hold-time-ns = <300>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2016-04-13 06:55:45 +07:00
|
|
|
|
|
|
|
|
usb_phy: usbphy {
|
|
|
|
|
compatible = "hisilicon,hi6220-usb-phy";
|
|
|
|
|
#phy-cells = <0>;
|
2017-05-03 17:46:55 +07:00
|
|
|
phy-supply = <®_5v_hub>;
|
2016-04-13 06:55:45 +07:00
|
|
|
hisilicon,peripheral-syscon = <&sys_ctrl>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb: usb@f72c0000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-usb";
|
|
|
|
|
reg = <0x0 0xf72c0000 0x0 0x40000>;
|
|
|
|
|
phys = <&usb_phy>;
|
|
|
|
|
phy-names = "usb2-phy";
|
|
|
|
|
clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
|
|
|
|
|
clock-names = "otg";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
g-rx-fifo-size = <512>;
|
|
|
|
|
g-np-tx-fifo-size = <128>;
|
arm64: dts: hi6220: improve g-tx-fifo-size setting for usb device
The current usb device g-tx-fifo-size setting in DT causes two problems
for kernel driver.
1. On hi6220, there are 15 tx_fifo dedicated for all EPs except EP0,
while DT only provides tx_fifo settings for 6 EPs. It results in the
following annoying complaints from kernel.
[ 4.451623] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[7]=0
[ 4.461303] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[8]=0
[ 4.470969] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[9]=0
[ 4.480632] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[10]=0
[ 4.490385] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[11]=0
[ 4.500140] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[12]=0
[ 4.509892] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[13]=0
[ 4.519646] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[14]=0
[ 4.529399] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[15]=0
[ 4.539244] dwc2 f72c0000.usb: EPs: 16, dedicated fifos, 1920 entries in SPRAM
Besides of that, the total 1920 fifo entries isn't fully utilized.
Endpoint Info Control block consumes 128 entries, g-rx-fifo-size
is 512, and g-np-tx-fifo-size is 128. So the fifi entries available
for tx_fifo is: 1920 - 128 - 512 - 128 = 1152. Considering that
the minimal valid tx_fifo size for each EP is 16, it should be
reasonable to allocate 1152 entries as: 128 x 8 + 16 x 7 = 1136 (only
16 entries unused). With this new setting, we can get more EPs to
use while removing the above warning messages in the meantime.
2. Another consequence of above invalid g_tx_fifo_size parameter is that
kernel driver will use values read from hardware register as the
fall-back. The value is 2048 for each EP fifo. That's obviously
invalid either, because even fifo entries for one EP exceeds the
total entries 1920. That's why we see the following fat warning from
function dwc2_hsotg_init_fifo(). The new g-tx-fifo-size settings
help to remove the warning as well.
[ 65.431634] dwc2 f72c0000.usb: Do port resume before switching to device mode
[ 65.624176] insufficient fifo memory
[ 65.624369] ------------[ cut here ]------------
[ 65.633633] WARNING: CPU: 0 PID: 5 at drivers/usb/dwc2/gadget.c:330 dwc2_hsotg_init_fifo+0x164/0x1ac
[ 65.643808] CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.13.0-rc1-00022-g50861cf9dc1b-dirty #81
[ 65.653769] Hardware name: HiKey Development Board (DT)
[ 65.659624] Workqueue: dwc2 dwc2_conn_id_status_change
[ 65.665377] task: ffffffc005f73400 task.stack: ffffffc005f98000
[ 65.671987] PC is at dwc2_hsotg_init_fifo+0x164/0x1ac
[ 65.677633] LR is at dwc2_hsotg_init_fifo+0x164/0x1ac
[ 65.683275] pc : [<ffffff8008638044>] lr : [<ffffff8008638044>] pstate: 600001c5
[ 65.691504] sp : ffffffc005f9bce0
[ 65.695218] x29: ffffffc005f9bce0 x28: ffffffc005f6ac00
[ 65.701172] x27: ffffffc005f73400 x26: 0000000008000580
[ 65.707124] x25: ffffff8008bb4af0 x24: ffffff8008d02b70
[ 65.713074] x23: 0000003fcc831084 x22: ffffffc0337cf0bc
[ 65.719024] x21: 0000000000000580 x20: ffffffc0337cf018
[ 65.724976] x19: ffffffc0337cf098 x18: 0000000000000000
[ 65.730926] x17: 0000000000000000 x16: 0000000000000000
[ 65.736873] x15: 0000000000000000 x14: ffffff8008ca8900
[ 65.742825] x13: 0000004035299000 x12: 0000000034d5d91d
[ 65.748775] x11: 0000000000000000 x10: 00000000000008d0
[ 65.754726] x9 : ffffffc005f9bce0 x8 : 00000000000001b5
[ 65.760674] x7 : 66696620746e6569 x6 : ffffff8008d60050
[ 65.766623] x5 : 0000000000000000 x4 : 0000000000000000
[ 65.772573] x3 : 0000000000000002 x2 : 0000000000000002
[ 65.778521] x1 : 0000000000000001 x0 : 0000000000000018
[ 65.784469] Call trace:
[ 65.787236] Exception stack(0xffffffc005f9bb10 to 0xffffffc005f9bc40)
[ 65.794420] bb00: ffffffc0337cf098 0000008000000000
[ 65.803145] bb20: ffffffc005f9bce0 ffffff8008638044 ffffff8008bb4af0 0000000008000580
[ 65.811870] bb40: ffffffc005f73400 ffffffc005f6ac00 0000000000000000 ffffff8008da2998
[ 65.820595] bb60: ffffffc005f9bce0 ffffffc005f9bce0 ffffffc005f9bca0 00000000ffffffc8
[ 65.829315] bb80: ffffffc005f9bbb0 ffffff80081046a0 ffffffc005f9bce0 ffffffc005f9bce0
[ 65.838038] bba0: ffffffc005f9bca0 00000000ffffffc8 0000000000000018 0000000000000001
[ 65.846761] bbc0: 0000000000000002 0000000000000002 0000000000000000 0000000000000000
[ 65.855485] bbe0: ffffff8008d60050 66696620746e6569 00000000000001b5 ffffffc005f9bce0
[ 65.864207] bc00: 00000000000008d0 0000000000000000 0000000034d5d91d 0000004035299000
[ 65.872928] bc20: ffffff8008ca8900 0000000000000000 0000000000000000 0000000000000000
[ 65.900856] [<ffffff8008638044>] dwc2_hsotg_init_fifo+0x164/0x1ac
[ 65.927195] [<ffffff800863b390>] dwc2_hsotg_core_init_disconnected+0x80/0x3c0
[ 65.954736] [<ffffff800862fef0>] dwc2_conn_id_status_change+0xfc/0x21c
[ 65.981561] [<ffffff80080d1ca8>] process_one_work+0x124/0x294
[ 66.007419] [<ffffff80080d1e70>] worker_thread+0x58/0x3c8
[ 66.023243] [<ffffff80080d79a0>] kthread+0x100/0x12c
[ 66.032455] [<ffffff8008082ec0>] ret_from_fork+0x10/0x50
[ 66.041987] ---[ end trace 7079dcaa2d9e46fa ]---
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-08-07 12:01:29 +07:00
|
|
|
g-tx-fifo-size = <128 128 128 128 128 128 128 128
|
|
|
|
|
16 16 16 16 16 16 16>;
|
2016-04-13 06:55:45 +07:00
|
|
|
interrupts = <0 77 0x4>;
|
|
|
|
|
};
|
2016-04-13 06:55:46 +07:00
|
|
|
|
|
|
|
|
mailbox: mailbox@f7510000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-mbox";
|
|
|
|
|
reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
|
|
|
|
|
<0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
|
|
|
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#mbox-cells = <3>;
|
|
|
|
|
};
|
2016-04-13 06:55:51 +07:00
|
|
|
|
|
|
|
|
dwmmc_0: dwmmc0@f723d000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-dw-mshc";
|
|
|
|
|
reg = <0x0 0xf723d000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0x0 0x48 0x4>;
|
|
|
|
|
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
|
|
|
|
|
clock-names = "ciu", "biu";
|
2016-08-25 10:00:41 +07:00
|
|
|
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
|
2017-03-16 21:03:24 +07:00
|
|
|
reset-names = "reset";
|
2016-04-13 06:55:51 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
|
|
|
|
|
&emmc_cfg_func &emmc_rst_cfg_func>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dwmmc_1: dwmmc1@f723e000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-dw-mshc";
|
|
|
|
|
hisilicon,peripheral-syscon = <&ao_ctrl>;
|
|
|
|
|
reg = <0x0 0xf723e000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0x0 0x49 0x4>;
|
|
|
|
|
#address-cells = <0x1>;
|
|
|
|
|
#size-cells = <0x0>;
|
|
|
|
|
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
|
|
|
|
|
clock-names = "ciu", "biu";
|
2016-08-25 10:00:41 +07:00
|
|
|
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
|
2017-03-16 21:03:24 +07:00
|
|
|
reset-names = "reset";
|
2016-04-13 06:55:51 +07:00
|
|
|
pinctrl-names = "default", "idle";
|
|
|
|
|
pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
|
|
|
|
|
pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dwmmc_2: dwmmc2@f723f000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-dw-mshc";
|
|
|
|
|
reg = <0x0 0xf723f000 0x0 0x1000>;
|
|
|
|
|
interrupts = <0x0 0x4a 0x4>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
|
|
|
|
|
clock-names = "ciu", "biu";
|
2016-08-25 10:00:41 +07:00
|
|
|
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
|
2017-03-16 21:03:24 +07:00
|
|
|
reset-names = "reset";
|
2016-04-13 06:55:51 +07:00
|
|
|
pinctrl-names = "default", "idle";
|
|
|
|
|
pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
|
|
|
|
|
pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
|
|
|
|
|
};
|
2016-03-29 18:27:14 +07:00
|
|
|
|
2018-03-01 19:18:47 +07:00
|
|
|
watchdog0: watchdog@f8005000 {
|
|
|
|
|
compatible = "arm,sp805-wdt", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xf8005000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
2016-03-29 18:27:14 +07:00
|
|
|
tsensor: tsensor@0,f7030700 {
|
|
|
|
|
compatible = "hisilicon,tsensor";
|
|
|
|
|
reg = <0x0 0xf7030700 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&sys_ctrl 22>;
|
|
|
|
|
clock-names = "thermal_clk";
|
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
|
|
|
};
|
2016-03-29 18:27:15 +07:00
|
|
|
|
2017-06-15 01:25:17 +07:00
|
|
|
i2s0: i2s@f7118000{
|
|
|
|
|
compatible = "hisilicon,hi6210-i2s";
|
|
|
|
|
reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
|
|
|
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
|
|
|
|
|
<&sys_ctrl HI6220_BBPPLL0_DIV>;
|
|
|
|
|
clock-names = "dacodec", "i2s-base";
|
|
|
|
|
dmas = <&dma0 15 &dma0 14>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
hisilicon,sysctrl-syscon = <&sys_ctrl>;
|
|
|
|
|
#sound-dai-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-03-29 18:27:15 +07:00
|
|
|
thermal-zones {
|
|
|
|
|
|
|
|
|
|
cls0: cls0 {
|
|
|
|
|
polling-delay = <1000>;
|
|
|
|
|
polling-delay-passive = <100>;
|
|
|
|
|
sustainable-power = <3326>;
|
|
|
|
|
|
|
|
|
|
/* sensor ID */
|
|
|
|
|
thermal-sensors = <&tsensor 2>;
|
|
|
|
|
|
|
|
|
|
trips {
|
|
|
|
|
threshold: trip-point@0 {
|
|
|
|
|
temperature = <65000>;
|
|
|
|
|
hysteresis = <0>;
|
|
|
|
|
type = "passive";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
target: trip-point@1 {
|
|
|
|
|
temperature = <75000>;
|
|
|
|
|
hysteresis = <0>;
|
|
|
|
|
type = "passive";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cooling-maps {
|
|
|
|
|
map0 {
|
|
|
|
|
trip = <&target>;
|
|
|
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2016-08-23 05:48:02 +07:00
|
|
|
|
|
|
|
|
ade: ade@f4100000 {
|
|
|
|
|
compatible = "hisilicon,hi6220-ade";
|
|
|
|
|
reg = <0x0 0xf4100000 0x0 0x7800>;
|
|
|
|
|
reg-names = "ade_base";
|
|
|
|
|
hisilicon,noc-syscon = <&medianoc_ade>;
|
|
|
|
|
resets = <&media_ctrl MEDIA_ADE>;
|
|
|
|
|
interrupts = <0 115 4>; /* ldi interrupt */
|
|
|
|
|
|
|
|
|
|
clocks = <&media_ctrl HI6220_ADE_CORE>,
|
|
|
|
|
<&media_ctrl HI6220_CODEC_JPEG>,
|
|
|
|
|
<&media_ctrl HI6220_ADE_PIX_SRC>;
|
|
|
|
|
/*clock name*/
|
|
|
|
|
clock-names = "clk_ade_core",
|
|
|
|
|
"clk_codec_jpeg",
|
|
|
|
|
"clk_ade_pix";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
|
|
|
|
|
<&media_ctrl HI6220_CODEC_JPEG>;
|
|
|
|
|
assigned-clock-rates = <360000000>, <288000000>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
ade_out: endpoint {
|
|
|
|
|
remote-endpoint = <&dsi_in>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dsi: dsi@f4107800 {
|
|
|
|
|
compatible = "hisilicon,hi6220-dsi";
|
|
|
|
|
reg = <0x0 0xf4107800 0x0 0x100>;
|
|
|
|
|
clocks = <&media_ctrl HI6220_DSI_PCLK>;
|
|
|
|
|
clock-names = "pclk";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
/* 0 for input port */
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
dsi_in: endpoint {
|
|
|
|
|
remote-endpoint = <&ade_out>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2017-06-06 03:15:17 +07:00
|
|
|
|
|
|
|
|
debug@f6590000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf6590000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f6592000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf6592000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f6594000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf6594000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f6596000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf6596000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu3>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f65d0000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf65d0000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f65d2000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf65d2000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu5>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f65d4000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf65d4000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu6>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
debug@f65d6000 {
|
|
|
|
|
compatible = "arm,coresight-cpu-debug","arm,primecell";
|
|
|
|
|
reg = <0 0xf65d6000 0 0x1000>;
|
|
|
|
|
clocks = <&sys_ctrl HI6220_DAPB_CLK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
cpu = <&cpu7>;
|
|
|
|
|
};
|
2015-02-07 13:57:52 +07:00
|
|
|
};
|
|
|
|
|
};
|
2017-09-01 07:47:15 +07:00
|
|
|
|
|
|
|
|
#include "hi6220-coresight.dtsi"
|