2011-10-25 09:01:28 +07:00
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/dts-v1/;
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2013-12-02 20:09:57 +07:00
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#include <dt-bindings/input/input.h>
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2012-10-18 05:38:21 +07:00
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#include "tegra20.dtsi"
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2011-10-25 09:01:28 +07:00
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/ {
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model = "Compulab TrimSlice board";
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compatible = "compulab,trimslice", "nvidia,tegra20";
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2012-05-12 05:17:47 +07:00
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memory {
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2012-05-12 05:11:38 +07:00
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reg = <0x00000000 0x40000000>;
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2011-10-25 09:01:28 +07:00
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};
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2013-11-26 07:53:16 +07:00
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host1x@50000000 {
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hdmi@54280000 {
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2012-09-20 15:39:20 +07:00
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status = "okay";
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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2013-02-13 07:25:15 +07:00
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
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GPIO_ACTIVE_HIGH>;
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2012-09-20 15:39:20 +07:00
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};
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};
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2013-11-26 07:53:16 +07:00
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pinmux@70000014 {
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2012-03-16 05:27:36 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ata {
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nvidia,pins = "ata";
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nvidia,function = "ide";
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};
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atb {
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nvidia,pins = "atb", "gma";
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nvidia,function = "sdio4";
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};
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atc {
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nvidia,pins = "atc", "gmb";
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nvidia,function = "nand";
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};
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atd {
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nvidia,pins = "atd", "ate", "gme", "pta";
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nvidia,function = "gmi";
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};
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cdev1 {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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};
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cdev2 {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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};
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crtp {
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nvidia,pins = "crtp";
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nvidia,function = "crt";
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};
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csus {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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};
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dap1 {
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nvidia,pins = "dap1";
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nvidia,function = "dap1";
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};
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dap2 {
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nvidia,pins = "dap2";
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nvidia,function = "dap2";
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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};
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dap4 {
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nvidia,pins = "dap4";
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nvidia,function = "dap4";
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};
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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};
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dta {
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nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
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nvidia,function = "vi";
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};
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dtf {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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};
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gmc {
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nvidia,pins = "gmc", "gmd";
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nvidia,function = "sflash";
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};
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gpu {
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nvidia,pins = "gpu";
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nvidia,function = "uarta";
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};
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gpu7 {
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nvidia,pins = "gpu7";
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nvidia,function = "rtck";
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};
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gpv {
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nvidia,pins = "gpv", "slxa", "slxk";
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nvidia,function = "pcie";
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};
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hdint {
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nvidia,pins = "hdint";
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nvidia,function = "hdmi";
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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};
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irrx {
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nvidia,pins = "irrx", "irtx";
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nvidia,function = "uartb";
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};
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kbca {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "kbc";
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};
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lcsn {
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nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
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"ld3", "ld4", "ld5", "ld6", "ld7",
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"ld8", "ld9", "ld10", "ld11", "ld12",
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"ld13", "ld14", "ld15", "ld16", "ld17",
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"ldc", "ldi", "lhp0", "lhp1", "lhp2",
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"lhs", "lm0", "lm1", "lpp", "lpw0",
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"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
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"lsda", "lsdi", "lspi", "lvp0", "lvp1",
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"lvs";
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nvidia,function = "displaya";
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};
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owc {
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nvidia,pins = "owc", "uac";
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nvidia,function = "rsvd2";
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};
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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};
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rm {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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};
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sdb {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "pwm";
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};
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sdio1 {
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nvidia,pins = "sdio1";
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nvidia,function = "sdio1";
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};
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slxc {
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nvidia,pins = "slxc", "slxd";
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nvidia,function = "sdio3";
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};
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spdi {
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nvidia,pins = "spdi", "spdo";
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nvidia,function = "spdif";
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};
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spia {
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nvidia,pins = "spia", "spib", "spic";
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nvidia,function = "spi2";
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};
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spid {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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};
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spig {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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};
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uaa {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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};
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uad {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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};
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uca {
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nvidia,pins = "uca", "ucb";
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nvidia,function = "uartc";
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};
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conf_ata {
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nvidia,pins = "ata", "atc", "atd", "ate",
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"crtp", "dap2", "dap3", "dap4", "dta",
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"dtb", "dtc", "dtd", "dte", "gmb",
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"gme", "i2cp", "pta", "slxc", "slxd",
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"spdi", "spdo", "uda";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_atb {
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2012-04-14 05:35:20 +07:00
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nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
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"gma", "gmc", "gmd", "gpu", "gpu7",
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"gpv", "sdio1", "slxa", "slxk", "uac";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ck32 {
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nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
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"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2012-03-16 05:27:36 +07:00
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};
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2012-04-14 05:35:20 +07:00
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conf_csus {
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nvidia,pins = "csus", "spia", "spib",
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"spid", "spif";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-04-14 05:35:20 +07:00
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};
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2012-03-16 05:27:36 +07:00
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conf_ddc {
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nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_hdint {
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nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
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"lpw1", "lsc1", "lsck", "lsda", "lsdi",
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"lvp0", "pmc";
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2013-12-05 17:44:08 +07:00
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_irrx {
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nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
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"kbcc", "kbcd", "kbce", "kbcf", "owc",
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"spic", "spie", "spig", "spih", "uaa",
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"uab", "uad", "uca", "ucb";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_lc {
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nvidia,pins = "lc", "ls";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ld0 {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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"ld5", "ld6", "ld7", "ld8", "ld9",
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"ld10", "ld11", "ld12", "ld13", "ld14",
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"ld15", "ld16", "ld17", "ldi", "lhp0",
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"lhp1", "lhp2", "lhs", "lm0", "lpp",
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"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
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"lvs", "sdb";
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2013-12-05 17:44:08 +07:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ld17_0 {
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nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
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"ld23_22";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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2012-03-16 05:27:36 +07:00
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};
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2012-12-07 04:23:52 +07:00
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conf_spif {
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nvidia,pins = "spif";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-12-07 04:23:52 +07:00
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};
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2012-03-16 05:27:36 +07:00
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};
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};
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2012-05-12 06:32:56 +07:00
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i2s@70002800 {
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status = "okay";
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2012-05-12 06:03:26 +07:00
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};
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serial@70006000 {
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2012-05-12 06:32:56 +07:00
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status = "okay";
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2012-05-12 06:03:26 +07:00
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};
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2012-09-20 15:39:20 +07:00
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dvi_ddc: i2c@7000c000 {
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2012-05-12 06:32:56 +07:00
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status = "okay";
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2012-09-20 15:39:20 +07:00
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clock-frequency = <100000>;
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2011-10-25 09:01:28 +07:00
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};
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2012-11-13 02:51:22 +07:00
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spi@7000c380 {
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status = "okay";
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spi-max-frequency = <48000000>;
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spi-flash@0 {
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compatible = "winbond,w25q80bl";
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reg = <0>;
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spi-max-frequency = <48000000>;
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};
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};
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2012-09-20 15:39:20 +07:00
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hdmi_ddc: i2c@7000c400 {
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2012-05-12 06:32:56 +07:00
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status = "okay";
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2012-09-20 15:39:20 +07:00
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clock-frequency = <100000>;
|
2011-10-25 09:01:28 +07:00
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};
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i2c@7000c500 {
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2012-05-12 06:32:56 +07:00
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status = "okay";
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2011-10-25 09:01:28 +07:00
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clock-frequency = <400000>;
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2012-04-28 02:24:03 +07:00
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codec: codec@1a {
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compatible = "ti,tlv320aic23";
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|
|
reg = <0x1a>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-27 22:22:44 +07:00
|
|
|
rtc@56 {
|
|
|
|
|
compatible = "emmicro,em3027";
|
|
|
|
|
reg = <0x56>;
|
|
|
|
|
};
|
2011-11-22 04:44:09 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pmc@7000e400 {
|
2013-08-12 16:40:07 +07:00
|
|
|
nvidia,suspend-mode = <1>;
|
2013-04-03 18:31:52 +07:00
|
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
|
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <3875>;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pcie-controller@80003000 {
|
2013-08-09 21:49:23 +07:00
|
|
|
status = "okay";
|
|
|
|
|
pex-clk-supply = <&pci_clk_reg>;
|
|
|
|
|
vdd-supply = <&pci_vdd_reg>;
|
|
|
|
|
|
|
|
|
|
pci@1,0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
usb@c5000000 {
|
|
|
|
|
status = "okay";
|
2012-01-12 06:09:57 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
usb-phy@c5000000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vbus_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
usb@c5004000 {
|
2012-07-26 03:02:43 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
2011-11-22 04:44:10 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:56 +07:00
|
|
|
usb-phy@c5004000 {
|
2013-05-16 21:12:57 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
2011-11-22 04:44:11 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:56 +07:00
|
|
|
usb@c5008000 {
|
|
|
|
|
status = "okay";
|
2013-01-24 17:16:46 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
usb-phy@c5008000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
sdhci@c8000000 {
|
|
|
|
|
status = "okay";
|
2012-05-15 03:35:04 +07:00
|
|
|
bus-width = <4>;
|
2011-11-22 04:44:11 +07:00
|
|
|
};
|
|
|
|
|
|
2011-10-25 09:01:28 +07:00
|
|
|
sdhci@c8000600 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
|
|
|
|
|
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
|
2012-05-15 03:35:04 +07:00
|
|
|
bus-width = <4>;
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|
2012-04-13 04:46:49 +07:00
|
|
|
|
2013-04-03 18:31:27 +07:00
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
clk32k_in: clock@0 {
|
2013-04-03 18:31:27 +07:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
reg=<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-04-03 18:31:48 +07:00
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "Power";
|
2013-02-13 07:25:15 +07:00
|
|
|
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
|
2013-12-02 20:09:57 +07:00
|
|
|
linux,code = <KEY_POWER>;
|
2013-04-03 18:31:48 +07:00
|
|
|
gpio-key,wakeup;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-07 04:23:52 +07:00
|
|
|
poweroff {
|
|
|
|
|
compatible = "gpio-poweroff";
|
2013-02-13 07:25:15 +07:00
|
|
|
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
|
2012-12-07 04:23:52 +07:00
|
|
|
};
|
|
|
|
|
|
2012-09-20 15:39:20 +07:00
|
|
|
regulators {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
hdmi_vdd_reg: regulator@0 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
regulator-name = "avdd_hdmi";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi_pll_reg: regulator@1 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
regulator-name = "avdd_hdmi_pll";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
2013-05-16 21:12:57 +07:00
|
|
|
|
|
|
|
|
vbus_reg: regulator@2 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
regulator-name = "usb1_vbus";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
2013-07-02 04:07:05 +07:00
|
|
|
enable-active-high;
|
2013-08-02 01:26:01 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
|
ARM: tegra: always enable USB VBUS regulators
This fixes a regression exposed during the merge window by commit
9f310de "ARM: tegra: fix VBUS regulator GPIO polarity in DT"; namely that
USB VBUS doesn't get turned on, so USB devices are not detected. This
affects the internal USB port on TrimSlice (i.e. the USB->SATA bridge, to
which the SSD is connected) and the external port(s) on Seaboard/
Springbank and Whistler.
The Tegra DT as written in v3.11 allows two paths to enable USB VBUS:
1) Via the legacy DT binding for the USB controller; it can directly
acquire a VBUS GPIO and activate it.
2) Via a regulator for VBUS, which is referenced by the new DT binding
for the USB controller.
Those two methods both use the same GPIO, and hence whichever of the
USB controller and regulator gets probed first ends up owning the GPIO.
In practice, the USB driver only supports path (1) above, since the
patches to support the new USB binding are not present until v3.12:-(
In practice, the regulator ends up being probed first and owning the
GPIO. Since nothing enables the regulator (the USB driver code is not
yet present), the regulator ends up being turned off. This originally
caused no problem, because the polarity in the regulator definition was
incorrect, so attempting to turn off the regulator actually turned it
on, and everything worked:-(
However, when testing the new USB driver code in v3.12, I noticed the
incorrect polarity and fixed it in commit 9f310de "ARM: tegra: fix VBUS
regulator GPIO polarity in DT". In the context of v3.11, this patch then
caused the USB VBUS to actually turn off, which broke USB ports with VBUS
control. I got this patch included in v3.11-rc1 since it fixed a bug in
device tree (incorrect polarity specification), and hence was suitable to
be included early in the rc series. I evidently did not test the patch at
all, or correctly, in the context of v3.11, and hence did not notice the
issue that I have explained above:-(
Fix this by making the USB VBUS regulators always enabled. This way, if
the regulator owns the GPIO, it will always be turned on, even if there
is no USB driver code to request the regulator be turned on. Even
ignoring this bug, this is a reasonable way to configure the HW anyway.
If this patch is applied to v3.11, it will cause a couple pretty trivial
conflicts in tegra20-{trimslice,seaboard}.dts when creating v3.12, since
the context right above the added lines changed in patches destined for
v3.12.
Reported-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-21 03:00:13 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2013-05-16 21:12:57 +07:00
|
|
|
};
|
2013-08-09 21:49:23 +07:00
|
|
|
|
|
|
|
|
pci_clk_reg: regulator@3 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <3>;
|
|
|
|
|
regulator-name = "pci_clk";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pci_vdd_reg: regulator@4 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <4>;
|
|
|
|
|
regulator-name = "pci_vdd";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
2012-09-20 15:39:20 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-trimslice";
|
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&codec>;
|
2013-03-27 05:45:52 +07:00
|
|
|
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CDEV1>;
|
2013-03-27 05:45:52 +07:00
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
2012-04-13 04:46:49 +07:00
|
|
|
};
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|