2011-10-25 09:01:28 +07:00
|
|
|
/dts-v1/;
|
|
|
|
|
|
2013-12-02 20:09:57 +07:00
|
|
|
#include <dt-bindings/input/input.h>
|
2012-10-18 05:38:21 +07:00
|
|
|
#include "tegra20.dtsi"
|
2011-10-25 09:01:28 +07:00
|
|
|
|
|
|
|
|
/ {
|
|
|
|
|
model = "Compulab TrimSlice board";
|
|
|
|
|
compatible = "compulab,trimslice", "nvidia,tegra20";
|
|
|
|
|
|
2012-05-12 05:17:47 +07:00
|
|
|
memory {
|
2012-05-12 05:11:38 +07:00
|
|
|
reg = <0x00000000 0x40000000>;
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
host1x@50000000 {
|
|
|
|
|
hdmi@54280000 {
|
2012-09-20 15:39:20 +07:00
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
vdd-supply = <&hdmi_vdd_reg>;
|
|
|
|
|
pll-supply = <&hdmi_pll_reg>;
|
|
|
|
|
|
|
|
|
|
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
|
|
|
|
|
GPIO_ACTIVE_HIGH>;
|
2012-09-20 15:39:20 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pinmux@70000014 {
|
2012-03-16 05:27:36 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&state_default>;
|
|
|
|
|
|
|
|
|
|
state_default: pinmux {
|
|
|
|
|
ata {
|
|
|
|
|
nvidia,pins = "ata";
|
|
|
|
|
nvidia,function = "ide";
|
|
|
|
|
};
|
|
|
|
|
atb {
|
|
|
|
|
nvidia,pins = "atb", "gma";
|
|
|
|
|
nvidia,function = "sdio4";
|
|
|
|
|
};
|
|
|
|
|
atc {
|
|
|
|
|
nvidia,pins = "atc", "gmb";
|
|
|
|
|
nvidia,function = "nand";
|
|
|
|
|
};
|
|
|
|
|
atd {
|
|
|
|
|
nvidia,pins = "atd", "ate", "gme", "pta";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
};
|
|
|
|
|
cdev1 {
|
|
|
|
|
nvidia,pins = "cdev1";
|
|
|
|
|
nvidia,function = "plla_out";
|
|
|
|
|
};
|
|
|
|
|
cdev2 {
|
|
|
|
|
nvidia,pins = "cdev2";
|
|
|
|
|
nvidia,function = "pllp_out4";
|
|
|
|
|
};
|
|
|
|
|
crtp {
|
|
|
|
|
nvidia,pins = "crtp";
|
|
|
|
|
nvidia,function = "crt";
|
|
|
|
|
};
|
|
|
|
|
csus {
|
|
|
|
|
nvidia,pins = "csus";
|
|
|
|
|
nvidia,function = "vi_sensor_clk";
|
|
|
|
|
};
|
|
|
|
|
dap1 {
|
|
|
|
|
nvidia,pins = "dap1";
|
|
|
|
|
nvidia,function = "dap1";
|
|
|
|
|
};
|
|
|
|
|
dap2 {
|
|
|
|
|
nvidia,pins = "dap2";
|
|
|
|
|
nvidia,function = "dap2";
|
|
|
|
|
};
|
|
|
|
|
dap3 {
|
|
|
|
|
nvidia,pins = "dap3";
|
|
|
|
|
nvidia,function = "dap3";
|
|
|
|
|
};
|
|
|
|
|
dap4 {
|
|
|
|
|
nvidia,pins = "dap4";
|
|
|
|
|
nvidia,function = "dap4";
|
|
|
|
|
};
|
|
|
|
|
ddc {
|
|
|
|
|
nvidia,pins = "ddc";
|
|
|
|
|
nvidia,function = "i2c2";
|
|
|
|
|
};
|
|
|
|
|
dta {
|
|
|
|
|
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
|
|
|
|
nvidia,function = "vi";
|
|
|
|
|
};
|
|
|
|
|
dtf {
|
|
|
|
|
nvidia,pins = "dtf";
|
|
|
|
|
nvidia,function = "i2c3";
|
|
|
|
|
};
|
|
|
|
|
gmc {
|
|
|
|
|
nvidia,pins = "gmc", "gmd";
|
|
|
|
|
nvidia,function = "sflash";
|
|
|
|
|
};
|
|
|
|
|
gpu {
|
|
|
|
|
nvidia,pins = "gpu";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
};
|
|
|
|
|
gpu7 {
|
|
|
|
|
nvidia,pins = "gpu7";
|
|
|
|
|
nvidia,function = "rtck";
|
|
|
|
|
};
|
|
|
|
|
gpv {
|
|
|
|
|
nvidia,pins = "gpv", "slxa", "slxk";
|
|
|
|
|
nvidia,function = "pcie";
|
|
|
|
|
};
|
|
|
|
|
hdint {
|
|
|
|
|
nvidia,pins = "hdint";
|
|
|
|
|
nvidia,function = "hdmi";
|
|
|
|
|
};
|
|
|
|
|
i2cp {
|
|
|
|
|
nvidia,pins = "i2cp";
|
|
|
|
|
nvidia,function = "i2cp";
|
|
|
|
|
};
|
|
|
|
|
irrx {
|
|
|
|
|
nvidia,pins = "irrx", "irtx";
|
|
|
|
|
nvidia,function = "uartb";
|
|
|
|
|
};
|
|
|
|
|
kbca {
|
|
|
|
|
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
|
|
|
|
"kbce", "kbcf";
|
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
|
};
|
|
|
|
|
lcsn {
|
|
|
|
|
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
|
|
|
|
"ld3", "ld4", "ld5", "ld6", "ld7",
|
|
|
|
|
"ld8", "ld9", "ld10", "ld11", "ld12",
|
|
|
|
|
"ld13", "ld14", "ld15", "ld16", "ld17",
|
|
|
|
|
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
|
|
|
|
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
|
|
|
|
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
|
|
|
|
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
|
|
|
|
"lvs";
|
|
|
|
|
nvidia,function = "displaya";
|
|
|
|
|
};
|
|
|
|
|
owc {
|
|
|
|
|
nvidia,pins = "owc", "uac";
|
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
|
};
|
|
|
|
|
pmc {
|
|
|
|
|
nvidia,pins = "pmc";
|
|
|
|
|
nvidia,function = "pwr_on";
|
|
|
|
|
};
|
|
|
|
|
rm {
|
|
|
|
|
nvidia,pins = "rm";
|
|
|
|
|
nvidia,function = "i2c1";
|
|
|
|
|
};
|
|
|
|
|
sdb {
|
|
|
|
|
nvidia,pins = "sdb", "sdc", "sdd";
|
|
|
|
|
nvidia,function = "pwm";
|
|
|
|
|
};
|
|
|
|
|
sdio1 {
|
|
|
|
|
nvidia,pins = "sdio1";
|
|
|
|
|
nvidia,function = "sdio1";
|
|
|
|
|
};
|
|
|
|
|
slxc {
|
|
|
|
|
nvidia,pins = "slxc", "slxd";
|
|
|
|
|
nvidia,function = "sdio3";
|
|
|
|
|
};
|
|
|
|
|
spdi {
|
|
|
|
|
nvidia,pins = "spdi", "spdo";
|
|
|
|
|
nvidia,function = "spdif";
|
|
|
|
|
};
|
|
|
|
|
spia {
|
|
|
|
|
nvidia,pins = "spia", "spib", "spic";
|
|
|
|
|
nvidia,function = "spi2";
|
|
|
|
|
};
|
|
|
|
|
spid {
|
|
|
|
|
nvidia,pins = "spid", "spie", "spif";
|
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
|
};
|
|
|
|
|
spig {
|
|
|
|
|
nvidia,pins = "spig", "spih";
|
|
|
|
|
nvidia,function = "spi2_alt";
|
|
|
|
|
};
|
|
|
|
|
uaa {
|
|
|
|
|
nvidia,pins = "uaa", "uab", "uda";
|
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
|
};
|
|
|
|
|
uad {
|
|
|
|
|
nvidia,pins = "uad";
|
|
|
|
|
nvidia,function = "irda";
|
|
|
|
|
};
|
|
|
|
|
uca {
|
|
|
|
|
nvidia,pins = "uca", "ucb";
|
|
|
|
|
nvidia,function = "uartc";
|
|
|
|
|
};
|
|
|
|
|
conf_ata {
|
|
|
|
|
nvidia,pins = "ata", "atc", "atd", "ate",
|
|
|
|
|
"crtp", "dap2", "dap3", "dap4", "dta",
|
|
|
|
|
"dtb", "dtc", "dtd", "dte", "gmb",
|
|
|
|
|
"gme", "i2cp", "pta", "slxc", "slxd",
|
|
|
|
|
"spdi", "spdo", "uda";
|
|
|
|
|
nvidia,pull = <0>;
|
|
|
|
|
nvidia,tristate = <1>;
|
|
|
|
|
};
|
|
|
|
|
conf_atb {
|
2012-04-14 05:35:20 +07:00
|
|
|
nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
|
|
|
|
|
"gma", "gmc", "gmd", "gpu", "gpu7",
|
|
|
|
|
"gpv", "sdio1", "slxa", "slxk", "uac";
|
2012-03-16 05:27:36 +07:00
|
|
|
nvidia,pull = <0>;
|
|
|
|
|
nvidia,tristate = <0>;
|
|
|
|
|
};
|
|
|
|
|
conf_ck32 {
|
|
|
|
|
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
|
|
|
|
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
|
|
|
|
nvidia,pull = <0>;
|
|
|
|
|
};
|
2012-04-14 05:35:20 +07:00
|
|
|
conf_csus {
|
|
|
|
|
nvidia,pins = "csus", "spia", "spib",
|
|
|
|
|
"spid", "spif";
|
|
|
|
|
nvidia,pull = <1>;
|
|
|
|
|
nvidia,tristate = <1>;
|
|
|
|
|
};
|
2012-03-16 05:27:36 +07:00
|
|
|
conf_ddc {
|
|
|
|
|
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
|
|
|
|
|
nvidia,pull = <2>;
|
|
|
|
|
nvidia,tristate = <0>;
|
|
|
|
|
};
|
|
|
|
|
conf_hdint {
|
|
|
|
|
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
|
|
|
|
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
|
|
|
|
"lvp0", "pmc";
|
|
|
|
|
nvidia,tristate = <1>;
|
|
|
|
|
};
|
|
|
|
|
conf_irrx {
|
|
|
|
|
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
|
|
|
|
|
"kbcc", "kbcd", "kbce", "kbcf", "owc",
|
|
|
|
|
"spic", "spie", "spig", "spih", "uaa",
|
|
|
|
|
"uab", "uad", "uca", "ucb";
|
|
|
|
|
nvidia,pull = <2>;
|
|
|
|
|
nvidia,tristate = <1>;
|
|
|
|
|
};
|
|
|
|
|
conf_lc {
|
|
|
|
|
nvidia,pins = "lc", "ls";
|
|
|
|
|
nvidia,pull = <2>;
|
|
|
|
|
};
|
|
|
|
|
conf_ld0 {
|
|
|
|
|
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
|
|
|
|
"ld5", "ld6", "ld7", "ld8", "ld9",
|
|
|
|
|
"ld10", "ld11", "ld12", "ld13", "ld14",
|
|
|
|
|
"ld15", "ld16", "ld17", "ldi", "lhp0",
|
|
|
|
|
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
|
|
|
|
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
|
|
|
|
"lvs", "sdb";
|
|
|
|
|
nvidia,tristate = <0>;
|
|
|
|
|
};
|
|
|
|
|
conf_ld17_0 {
|
|
|
|
|
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
|
|
|
|
"ld23_22";
|
|
|
|
|
nvidia,pull = <1>;
|
|
|
|
|
};
|
2012-12-07 04:23:52 +07:00
|
|
|
conf_spif {
|
|
|
|
|
nvidia,pins = "spif";
|
|
|
|
|
nvidia,pull = <1>;
|
|
|
|
|
nvidia,tristate = <0>;
|
|
|
|
|
};
|
2012-03-16 05:27:36 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
i2s@70002800 {
|
|
|
|
|
status = "okay";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@70006000 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2012-09-20 15:39:20 +07:00
|
|
|
dvi_ddc: i2c@7000c000 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2012-09-20 15:39:20 +07:00
|
|
|
clock-frequency = <100000>;
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-13 02:51:22 +07:00
|
|
|
spi@7000c380 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
spi-max-frequency = <48000000>;
|
|
|
|
|
spi-flash@0 {
|
|
|
|
|
compatible = "winbond,w25q80bl";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
spi-max-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-20 15:39:20 +07:00
|
|
|
hdmi_ddc: i2c@7000c400 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2012-09-20 15:39:20 +07:00
|
|
|
clock-frequency = <100000>;
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c500 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2011-10-25 09:01:28 +07:00
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
|
2012-04-28 02:24:03 +07:00
|
|
|
codec: codec@1a {
|
|
|
|
|
compatible = "ti,tlv320aic23";
|
|
|
|
|
reg = <0x1a>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-27 22:22:44 +07:00
|
|
|
rtc@56 {
|
|
|
|
|
compatible = "emmicro,em3027";
|
|
|
|
|
reg = <0x56>;
|
|
|
|
|
};
|
2011-11-22 04:44:09 +07:00
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pmc@7000e400 {
|
2013-08-12 16:40:07 +07:00
|
|
|
nvidia,suspend-mode = <1>;
|
2013-04-03 18:31:52 +07:00
|
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
|
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <3875>;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
|
|
|
|
};
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
pcie-controller@80003000 {
|
2013-08-09 21:49:23 +07:00
|
|
|
status = "okay";
|
|
|
|
|
pex-clk-supply = <&pci_clk_reg>;
|
|
|
|
|
vdd-supply = <&pci_vdd_reg>;
|
|
|
|
|
|
|
|
|
|
pci@1,0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
usb@c5000000 {
|
|
|
|
|
status = "okay";
|
2012-01-12 06:09:57 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
usb-phy@c5000000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vbus_reg>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
usb@c5004000 {
|
2012-07-26 03:02:43 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
2011-11-22 04:44:10 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:56 +07:00
|
|
|
usb-phy@c5004000 {
|
2013-05-16 21:12:57 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
2011-11-22 04:44:11 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:56 +07:00
|
|
|
usb@c5008000 {
|
|
|
|
|
status = "okay";
|
2013-01-24 17:16:46 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-16 21:12:57 +07:00
|
|
|
usb-phy@c5008000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
sdhci@c8000000 {
|
|
|
|
|
status = "okay";
|
2012-05-15 03:35:04 +07:00
|
|
|
bus-width = <4>;
|
2011-11-22 04:44:11 +07:00
|
|
|
};
|
|
|
|
|
|
2011-10-25 09:01:28 +07:00
|
|
|
sdhci@c8000600 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2013-02-13 07:25:15 +07:00
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
|
|
|
|
|
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
|
2012-05-15 03:35:04 +07:00
|
|
|
bus-width = <4>;
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|
2012-04-13 04:46:49 +07:00
|
|
|
|
2013-04-03 18:31:27 +07:00
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
clk32k_in: clock@0 {
|
2013-04-03 18:31:27 +07:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
reg=<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-04-03 18:31:48 +07:00
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "Power";
|
2013-02-13 07:25:15 +07:00
|
|
|
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
|
2013-12-02 20:09:57 +07:00
|
|
|
linux,code = <KEY_POWER>;
|
2013-04-03 18:31:48 +07:00
|
|
|
gpio-key,wakeup;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-07 04:23:52 +07:00
|
|
|
poweroff {
|
|
|
|
|
compatible = "gpio-poweroff";
|
2013-02-13 07:25:15 +07:00
|
|
|
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
|
2012-12-07 04:23:52 +07:00
|
|
|
};
|
|
|
|
|
|
2012-09-20 15:39:20 +07:00
|
|
|
regulators {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
hdmi_vdd_reg: regulator@0 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
regulator-name = "avdd_hdmi";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi_pll_reg: regulator@1 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
regulator-name = "avdd_hdmi_pll";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
2013-05-16 21:12:57 +07:00
|
|
|
|
|
|
|
|
vbus_reg: regulator@2 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
regulator-name = "usb1_vbus";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
2013-07-02 04:07:05 +07:00
|
|
|
enable-active-high;
|
2013-08-02 01:26:01 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
|
ARM: tegra: always enable USB VBUS regulators
This fixes a regression exposed during the merge window by commit
9f310de "ARM: tegra: fix VBUS regulator GPIO polarity in DT"; namely that
USB VBUS doesn't get turned on, so USB devices are not detected. This
affects the internal USB port on TrimSlice (i.e. the USB->SATA bridge, to
which the SSD is connected) and the external port(s) on Seaboard/
Springbank and Whistler.
The Tegra DT as written in v3.11 allows two paths to enable USB VBUS:
1) Via the legacy DT binding for the USB controller; it can directly
acquire a VBUS GPIO and activate it.
2) Via a regulator for VBUS, which is referenced by the new DT binding
for the USB controller.
Those two methods both use the same GPIO, and hence whichever of the
USB controller and regulator gets probed first ends up owning the GPIO.
In practice, the USB driver only supports path (1) above, since the
patches to support the new USB binding are not present until v3.12:-(
In practice, the regulator ends up being probed first and owning the
GPIO. Since nothing enables the regulator (the USB driver code is not
yet present), the regulator ends up being turned off. This originally
caused no problem, because the polarity in the regulator definition was
incorrect, so attempting to turn off the regulator actually turned it
on, and everything worked:-(
However, when testing the new USB driver code in v3.12, I noticed the
incorrect polarity and fixed it in commit 9f310de "ARM: tegra: fix VBUS
regulator GPIO polarity in DT". In the context of v3.11, this patch then
caused the USB VBUS to actually turn off, which broke USB ports with VBUS
control. I got this patch included in v3.11-rc1 since it fixed a bug in
device tree (incorrect polarity specification), and hence was suitable to
be included early in the rc series. I evidently did not test the patch at
all, or correctly, in the context of v3.11, and hence did not notice the
issue that I have explained above:-(
Fix this by making the USB VBUS regulators always enabled. This way, if
the regulator owns the GPIO, it will always be turned on, even if there
is no USB driver code to request the regulator be turned on. Even
ignoring this bug, this is a reasonable way to configure the HW anyway.
If this patch is applied to v3.11, it will cause a couple pretty trivial
conflicts in tegra20-{trimslice,seaboard}.dts when creating v3.12, since
the context right above the added lines changed in patches destined for
v3.12.
Reported-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-21 03:00:13 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2013-05-16 21:12:57 +07:00
|
|
|
};
|
2013-08-09 21:49:23 +07:00
|
|
|
|
|
|
|
|
pci_clk_reg: regulator@3 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <3>;
|
|
|
|
|
regulator-name = "pci_clk";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pci_vdd_reg: regulator@4 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <4>;
|
|
|
|
|
regulator-name = "pci_vdd";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
2012-09-20 15:39:20 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-trimslice";
|
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&codec>;
|
2013-03-27 05:45:52 +07:00
|
|
|
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CDEV1>;
|
2013-03-27 05:45:52 +07:00
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
2012-04-13 04:46:49 +07:00
|
|
|
};
|
2011-10-25 09:01:28 +07:00
|
|
|
};
|