2011-07-20 06:26:54 +07:00
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/dts-v1/;
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2013-12-02 20:09:57 +07:00
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#include <dt-bindings/input/input.h>
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2012-10-18 05:38:21 +07:00
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#include "tegra20.dtsi"
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2011-07-20 06:26:54 +07:00
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/ {
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model = "NVIDIA Seaboard";
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compatible = "nvidia,seaboard", "nvidia,tegra20";
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memory {
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2012-05-12 05:11:38 +07:00
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reg = <0x00000000 0x40000000>;
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2011-07-20 06:26:54 +07:00
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};
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2013-11-26 07:53:16 +07:00
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host1x@50000000 {
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hdmi@54280000 {
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2013-01-03 04:53:20 +07:00
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status = "okay";
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vdd-supply = <&hdmi_vdd_reg>;
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pll-supply = <&hdmi_pll_reg>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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2013-02-13 07:25:15 +07:00
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
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GPIO_ACTIVE_HIGH>;
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2013-01-03 04:53:20 +07:00
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};
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};
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2013-11-26 07:53:16 +07:00
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pinmux@70000014 {
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2012-03-16 05:27:36 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ata {
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nvidia,pins = "ata";
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nvidia,function = "ide";
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};
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atb {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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};
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atc {
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nvidia,pins = "atc";
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nvidia,function = "nand";
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};
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atd {
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nvidia,pins = "atd", "ate", "gmb", "spia",
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"spib", "spic";
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nvidia,function = "gmi";
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};
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cdev1 {
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nvidia,pins = "cdev1";
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nvidia,function = "plla_out";
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};
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cdev2 {
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nvidia,pins = "cdev2";
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nvidia,function = "pllp_out4";
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};
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crtp {
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nvidia,pins = "crtp", "lm1";
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nvidia,function = "crt";
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};
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csus {
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nvidia,pins = "csus";
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nvidia,function = "vi_sensor_clk";
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};
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dap1 {
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nvidia,pins = "dap1";
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nvidia,function = "dap1";
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};
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dap2 {
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nvidia,pins = "dap2";
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nvidia,function = "dap2";
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};
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dap3 {
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nvidia,pins = "dap3";
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nvidia,function = "dap3";
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};
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dap4 {
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nvidia,pins = "dap4";
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nvidia,function = "dap4";
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};
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dta {
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nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
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nvidia,function = "vi";
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};
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dtf {
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nvidia,pins = "dtf";
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nvidia,function = "i2c3";
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};
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gmc {
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nvidia,pins = "gmc";
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nvidia,function = "uartd";
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};
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gmd {
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nvidia,pins = "gmd";
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nvidia,function = "sflash";
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};
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gpu {
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nvidia,pins = "gpu";
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nvidia,function = "pwm";
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};
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gpu7 {
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nvidia,pins = "gpu7";
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nvidia,function = "rtck";
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};
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gpv {
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nvidia,pins = "gpv", "slxa", "slxk";
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nvidia,function = "pcie";
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};
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hdint {
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nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
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2012-04-27 00:21:54 +07:00
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"lsck", "lsda";
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2012-03-16 05:27:36 +07:00
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nvidia,function = "hdmi";
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};
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i2cp {
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nvidia,pins = "i2cp";
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nvidia,function = "i2cp";
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};
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irrx {
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nvidia,pins = "irrx", "irtx";
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nvidia,function = "uartb";
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};
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kbca {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf";
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nvidia,function = "kbc";
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};
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lcsn {
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nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
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"lsdi", "lvp0";
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nvidia,function = "rsvd4";
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};
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ld0 {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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"ld5", "ld6", "ld7", "ld8", "ld9",
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"ld10", "ld11", "ld12", "ld13", "ld14",
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"ld15", "ld16", "ld17", "ldi", "lhp0",
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"lhp1", "lhp2", "lhs", "lpp", "lsc0",
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"lspi", "lvp1", "lvs";
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nvidia,function = "displaya";
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};
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2012-04-17 06:41:17 +07:00
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owc {
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nvidia,pins = "owc", "spdi", "spdo", "uac";
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nvidia,function = "rsvd2";
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};
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2012-03-16 05:27:36 +07:00
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pmc {
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nvidia,pins = "pmc";
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nvidia,function = "pwr_on";
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};
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rm {
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nvidia,pins = "rm";
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nvidia,function = "i2c1";
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};
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sdb {
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nvidia,pins = "sdb", "sdc", "sdd";
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nvidia,function = "sdio3";
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};
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sdio1 {
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nvidia,pins = "sdio1";
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nvidia,function = "sdio1";
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};
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slxc {
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nvidia,pins = "slxc", "slxd";
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nvidia,function = "spdif";
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};
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spid {
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nvidia,pins = "spid", "spie", "spif";
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nvidia,function = "spi1";
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};
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spig {
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nvidia,pins = "spig", "spih";
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nvidia,function = "spi2_alt";
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};
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uaa {
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nvidia,pins = "uaa", "uab", "uda";
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nvidia,function = "ulpi";
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};
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uad {
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nvidia,pins = "uad";
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nvidia,function = "irda";
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};
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uca {
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nvidia,pins = "uca", "ucb";
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nvidia,function = "uartc";
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};
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conf_ata {
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nvidia,pins = "ata", "atb", "atc", "atd",
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"cdev1", "cdev2", "dap1", "dap2",
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2012-04-17 06:41:17 +07:00
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"dap4", "ddc", "dtf", "gma", "gmc", "gmd",
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2012-03-16 05:27:36 +07:00
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"gme", "gpu", "gpu7", "i2cp", "irrx",
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"irtx", "pta", "rm", "sdc", "sdd",
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"slxd", "slxk", "spdi", "spdo", "uac",
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"uad", "uca", "ucb", "uda";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ate {
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2012-04-17 06:41:17 +07:00
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nvidia,pins = "ate", "csus", "dap3",
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2012-03-16 05:27:36 +07:00
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"gpv", "owc", "slxc", "spib", "spid",
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"spie";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ck32 {
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nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
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"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_crtp {
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nvidia,pins = "crtp", "gmb", "slxa", "spia",
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"spig", "spih";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_dta {
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nvidia,pins = "dta", "dtb", "dtc", "dtd";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_dte {
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nvidia,pins = "dte", "spif";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_hdint {
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nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
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"lpw1", "lsc1", "lsck", "lsda", "lsdi",
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"lvp0";
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2013-12-05 17:44:08 +07:00
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_kbca {
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nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
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"kbce", "kbcf", "sdio1", "spic", "uaa",
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"uab";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_lc {
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nvidia,pins = "lc", "ls";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ld0 {
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nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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"ld5", "ld6", "ld7", "ld8", "ld9",
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"ld10", "ld11", "ld12", "ld13", "ld14",
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"ld15", "ld16", "ld17", "ldi", "lhp0",
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"lhp1", "lhp2", "lhs", "lm0", "lpp",
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"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
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"lvs", "pmc", "sdb";
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2013-12-05 17:44:08 +07:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2012-03-16 05:27:36 +07:00
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};
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conf_ld17_0 {
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nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
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"ld23_22";
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2013-12-05 17:44:08 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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2012-03-16 05:27:36 +07:00
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};
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drive_sdio1 {
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nvidia,pins = "drive_sdio1";
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2013-12-05 17:44:08 +07:00
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nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
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2012-03-16 05:27:36 +07:00
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nvidia,pull-down-strength = <31>;
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nvidia,pull-up-strength = <31>;
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2013-12-05 17:44:08 +07:00
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nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
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nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
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2012-03-16 05:27:36 +07:00
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};
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};
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2012-04-17 06:41:17 +07:00
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state_i2cmux_ddc: pinmux_i2cmux_ddc {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "i2c2";
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};
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pta {
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nvidia,pins = "pta";
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nvidia,function = "rsvd4";
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};
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};
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state_i2cmux_pta: pinmux_i2cmux_pta {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "rsvd4";
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};
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pta {
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nvidia,pins = "pta";
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nvidia,function = "i2c2";
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};
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};
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state_i2cmux_idle: pinmux_i2cmux_idle {
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ddc {
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nvidia,pins = "ddc";
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nvidia,function = "rsvd4";
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};
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pta {
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|
|
|
|
nvidia,pins = "pta";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
};
|
|
|
|
|
};
|
2012-03-16 05:27:36 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:32:56 +07:00
|
|
|
i2s@70002800 {
|
|
|
|
|
status = "okay";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@70006300 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2012-05-12 06:03:26 +07:00
|
|
|
};
|
|
|
|
|
|
2011-11-22 04:44:09 +07:00
|
|
|
i2c@7000c000 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2011-11-22 04:44:09 +07:00
|
|
|
clock-frequency = <400000>;
|
2012-01-12 06:09:57 +07:00
|
|
|
|
|
|
|
|
wm8903: wm8903@1a {
|
|
|
|
|
compatible = "wlf,wm8903";
|
|
|
|
|
reg = <0x1a>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
|
2012-01-12 06:09:57 +07:00
|
|
|
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
|
|
|
|
|
micdet-cfg = <0>;
|
|
|
|
|
micdet-delay = <100>;
|
2012-05-12 05:11:38 +07:00
|
|
|
gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
|
2012-01-12 06:09:57 +07:00
|
|
|
};
|
2012-04-23 19:11:36 +07:00
|
|
|
|
|
|
|
|
/* ALS and proximity sensor */
|
|
|
|
|
isl29018@44 {
|
|
|
|
|
compatible = "isil,isl29018";
|
|
|
|
|
reg = <0x44>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
|
2012-04-23 19:11:36 +07:00
|
|
|
};
|
2011-12-22 23:33:13 +07:00
|
|
|
|
|
|
|
|
gyrometer@68 {
|
|
|
|
|
compatible = "invn,mpu3050";
|
|
|
|
|
reg = <0x68>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
|
2011-12-22 23:33:13 +07:00
|
|
|
};
|
2011-11-22 04:44:09 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c400 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2012-04-27 00:19:03 +07:00
|
|
|
clock-frequency = <100000>;
|
2011-11-22 04:44:09 +07:00
|
|
|
};
|
|
|
|
|
|
2012-04-17 06:41:17 +07:00
|
|
|
i2cmux {
|
|
|
|
|
compatible = "i2c-mux-pinctrl";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
i2c-parent = <&{/i2c@7000c400}>;
|
|
|
|
|
|
|
|
|
|
pinctrl-names = "ddc", "pta", "idle";
|
|
|
|
|
pinctrl-0 = <&state_i2cmux_ddc>;
|
|
|
|
|
pinctrl-1 = <&state_i2cmux_pta>;
|
|
|
|
|
pinctrl-2 = <&state_i2cmux_idle>;
|
|
|
|
|
|
2013-01-03 04:53:20 +07:00
|
|
|
hdmi_ddc: i2c@0 {
|
2012-04-17 06:41:17 +07:00
|
|
|
reg = <0>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2012-04-26 05:57:28 +07:00
|
|
|
|
|
|
|
|
smart-battery@b {
|
|
|
|
|
compatible = "ti,bq20z75", "smart-battery-1.1";
|
|
|
|
|
reg = <0xb>;
|
|
|
|
|
ti,i2c-retry-count = <2>;
|
|
|
|
|
ti,poll-retry-count = <10>;
|
|
|
|
|
};
|
2012-04-17 06:41:17 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2011-11-22 04:44:09 +07:00
|
|
|
i2c@7000c500 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2011-11-22 04:44:09 +07:00
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000d000 {
|
2012-05-12 06:32:56 +07:00
|
|
|
status = "okay";
|
2011-11-22 04:44:09 +07:00
|
|
|
clock-frequency = <400000>;
|
2011-12-18 13:29:32 +07:00
|
|
|
|
2013-11-27 04:43:45 +07:00
|
|
|
magnetometer@c {
|
|
|
|
|
compatible = "ak,ak8975";
|
|
|
|
|
reg = <0xc>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-06-21 04:58:34 +07:00
|
|
|
pmic: tps6586x@34 {
|
|
|
|
|
compatible = "ti,tps6586x";
|
|
|
|
|
reg = <0x34>;
|
2013-02-14 02:51:51 +07:00
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
2012-06-21 04:58:34 +07:00
|
|
|
|
2012-09-12 00:42:26 +07:00
|
|
|
ti,system-power-controller;
|
|
|
|
|
|
2012-06-21 04:58:34 +07:00
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
|
|
|
|
|
sys-supply = <&vdd_5v0_reg>;
|
|
|
|
|
vin-sm0-supply = <&sys_reg>;
|
|
|
|
|
vin-sm1-supply = <&sys_reg>;
|
|
|
|
|
vin-sm2-supply = <&sys_reg>;
|
|
|
|
|
vinldo01-supply = <&sm2_reg>;
|
|
|
|
|
vinldo23-supply = <&sm2_reg>;
|
|
|
|
|
vinldo4-supply = <&sm2_reg>;
|
|
|
|
|
vinldo678-supply = <&sm2_reg>;
|
|
|
|
|
vinldo9-supply = <&sm2_reg>;
|
|
|
|
|
|
|
|
|
|
regulators {
|
2012-09-21 06:04:06 +07:00
|
|
|
sys_reg: sys {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_sys";
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
sm0 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_sm0,vdd_core";
|
|
|
|
|
regulator-min-microvolt = <1300000>;
|
|
|
|
|
regulator-max-microvolt = <1300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
sm1 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_sm1,vdd_cpu";
|
|
|
|
|
regulator-min-microvolt = <1125000>;
|
|
|
|
|
regulator-max-microvolt = <1125000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
sm2_reg: sm2 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_sm2,vin_ldo*";
|
|
|
|
|
regulator-min-microvolt = <3700000>;
|
|
|
|
|
regulator-max-microvolt = <3700000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* LDO0 is not connected to anything */
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo1 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo1,avdd_pll*";
|
|
|
|
|
regulator-min-microvolt = <1100000>;
|
|
|
|
|
regulator-max-microvolt = <1100000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo2 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo2,vdd_rtc";
|
|
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo3 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo3,avdd_usb*";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo4 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo5 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo5,vcore_mmc";
|
|
|
|
|
regulator-min-microvolt = <2850000>;
|
|
|
|
|
regulator-max-microvolt = <2850000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo6 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-03 04:53:20 +07:00
|
|
|
hdmi_vdd_reg: ldo7 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-03 04:53:20 +07:00
|
|
|
hdmi_pll_reg: ldo8 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo9 {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
|
|
|
|
regulator-min-microvolt = <2850000>;
|
|
|
|
|
regulator-max-microvolt = <2850000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 06:04:06 +07:00
|
|
|
ldo_rtc {
|
2012-06-21 04:58:34 +07:00
|
|
|
regulator-name = "vdd_rtc_out,vdd_cell";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2011-12-22 23:33:13 +07:00
|
|
|
temperature-sensor@4c {
|
2012-11-20 05:34:44 +07:00
|
|
|
compatible = "onnn,nct1008";
|
2011-12-18 13:29:32 +07:00
|
|
|
reg = <0x4c>;
|
|
|
|
|
};
|
2011-12-18 12:18:23 +07:00
|
|
|
};
|
2011-10-19 01:06:06 +07:00
|
|
|
|
2013-11-26 07:53:16 +07:00
|
|
|
kbc@7000e200 {
|
2013-01-15 14:24:49 +07:00
|
|
|
status = "okay";
|
|
|
|
|
nvidia,debounce-delay-ms = <32>;
|
|
|
|
|
nvidia,repeat-delay-ms = <160>;
|
|
|
|
|
nvidia,ghost-filter;
|
|
|
|
|
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
|
|
|
|
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
2013-12-02 20:09:57 +07:00
|
|
|
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
|
|
|
|
|
MATRIX_KEY(0x00, 0x03, KEY_S)
|
|
|
|
|
MATRIX_KEY(0x00, 0x04, KEY_A)
|
|
|
|
|
MATRIX_KEY(0x00, 0x05, KEY_Z)
|
|
|
|
|
MATRIX_KEY(0x00, 0x07, KEY_FN)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
|
|
|
|
|
MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
|
|
|
|
|
MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x03, 0x00, KEY_5)
|
|
|
|
|
MATRIX_KEY(0x03, 0x01, KEY_4)
|
|
|
|
|
MATRIX_KEY(0x03, 0x02, KEY_R)
|
|
|
|
|
MATRIX_KEY(0x03, 0x03, KEY_E)
|
|
|
|
|
MATRIX_KEY(0x03, 0x04, KEY_F)
|
|
|
|
|
MATRIX_KEY(0x03, 0x05, KEY_D)
|
|
|
|
|
MATRIX_KEY(0x03, 0x06, KEY_X)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x04, 0x00, KEY_7)
|
|
|
|
|
MATRIX_KEY(0x04, 0x01, KEY_6)
|
|
|
|
|
MATRIX_KEY(0x04, 0x02, KEY_T)
|
|
|
|
|
MATRIX_KEY(0x04, 0x03, KEY_H)
|
|
|
|
|
MATRIX_KEY(0x04, 0x04, KEY_G)
|
|
|
|
|
MATRIX_KEY(0x04, 0x05, KEY_V)
|
|
|
|
|
MATRIX_KEY(0x04, 0x06, KEY_C)
|
|
|
|
|
MATRIX_KEY(0x04, 0x07, KEY_SPACE)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x05, 0x00, KEY_9)
|
|
|
|
|
MATRIX_KEY(0x05, 0x01, KEY_8)
|
|
|
|
|
MATRIX_KEY(0x05, 0x02, KEY_U)
|
|
|
|
|
MATRIX_KEY(0x05, 0x03, KEY_Y)
|
|
|
|
|
MATRIX_KEY(0x05, 0x04, KEY_J)
|
|
|
|
|
MATRIX_KEY(0x05, 0x05, KEY_N)
|
|
|
|
|
MATRIX_KEY(0x05, 0x06, KEY_B)
|
|
|
|
|
MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x06, 0x00, KEY_MINUS)
|
|
|
|
|
MATRIX_KEY(0x06, 0x01, KEY_0)
|
|
|
|
|
MATRIX_KEY(0x06, 0x02, KEY_O)
|
|
|
|
|
MATRIX_KEY(0x06, 0x03, KEY_I)
|
|
|
|
|
MATRIX_KEY(0x06, 0x04, KEY_L)
|
|
|
|
|
MATRIX_KEY(0x06, 0x05, KEY_K)
|
|
|
|
|
MATRIX_KEY(0x06, 0x06, KEY_COMMA)
|
|
|
|
|
MATRIX_KEY(0x06, 0x07, KEY_M)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
|
|
|
|
|
MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
|
|
|
|
|
MATRIX_KEY(0x07, 0x03, KEY_ENTER)
|
|
|
|
|
MATRIX_KEY(0x07, 0x07, KEY_MENU)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
|
|
|
|
|
MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
|
|
|
|
|
MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
|
|
|
|
|
MATRIX_KEY(0x0B, 0x01, KEY_P)
|
|
|
|
|
MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
|
|
|
|
|
MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
|
|
|
|
|
MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
|
|
|
|
|
MATRIX_KEY(0x0B, 0x05, KEY_DOT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x0C, 0x00, KEY_F10)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x01, KEY_F9)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x03, KEY_3)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x04, KEY_2)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x05, KEY_UP)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
|
|
|
|
|
MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
|
|
|
|
|
MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
|
|
|
|
|
MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
|
|
|
|
|
MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
|
|
|
|
|
MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
|
|
|
|
|
MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
|
|
|
|
|
MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x0E, 0x00, KEY_F11)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x01, KEY_F12)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x02, KEY_F8)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x03, KEY_Q)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x04, KEY_F4)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x05, KEY_F3)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x06, KEY_1)
|
|
|
|
|
MATRIX_KEY(0x0E, 0x07, KEY_F7)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x0F, 0x00, KEY_ESC)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x02, KEY_F5)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x03, KEY_TAB)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x04, KEY_F1)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x05, KEY_F2)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
|
|
|
|
|
MATRIX_KEY(0x0F, 0x07, KEY_F6)
|
2013-01-15 14:24:49 +07:00
|
|
|
|
|
|
|
|
/* Software Handled Function Keys */
|
2013-12-02 20:09:57 +07:00
|
|
|
MATRIX_KEY(0x14, 0x00, KEY_KP7)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x15, 0x00, KEY_KP9)
|
|
|
|
|
MATRIX_KEY(0x15, 0x01, KEY_KP8)
|
|
|
|
|
MATRIX_KEY(0x15, 0x02, KEY_KP4)
|
|
|
|
|
MATRIX_KEY(0x15, 0x04, KEY_KP1)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
|
|
|
|
|
MATRIX_KEY(0x16, 0x02, KEY_KP6)
|
|
|
|
|
MATRIX_KEY(0x16, 0x03, KEY_KP5)
|
|
|
|
|
MATRIX_KEY(0x16, 0x04, KEY_KP3)
|
|
|
|
|
MATRIX_KEY(0x16, 0x05, KEY_KP2)
|
|
|
|
|
MATRIX_KEY(0x16, 0x07, KEY_KP0)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
|
|
|
|
|
MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
|
|
|
|
|
MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
|
|
|
|
|
MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x1D, 0x03, KEY_HOME)
|
|
|
|
|
MATRIX_KEY(0x1D, 0x04, KEY_END)
|
|
|
|
|
MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
|
|
|
|
|
MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
|
|
|
|
|
MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
|
|
|
|
|
MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
|
|
|
|
|
MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
|
|
|
|
|
|
|
|
|
|
MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
|
2013-01-15 14:24:49 +07:00
|
|
|
};
|
2013-11-27 04:43:45 +07:00
|
|
|
|
|
|
|
|
pmc@7000e400 {
|
|
|
|
|
nvidia,invert-interrupt;
|
|
|
|
|
nvidia,suspend-mode = <1>;
|
|
|
|
|
nvidia,cpu-pwr-good-time = <5000>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <5000>;
|
|
|
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <3875>;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
memory-controller@7000f400 {
|
|
|
|
|
emc-table@190000 {
|
|
|
|
|
reg = <190000>;
|
|
|
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
|
|
|
clock-frequency = <190000>;
|
|
|
|
|
nvidia,emc-registers = <0x0000000c 0x00000026
|
|
|
|
|
0x00000009 0x00000003 0x00000004 0x00000004
|
|
|
|
|
0x00000002 0x0000000c 0x00000003 0x00000003
|
|
|
|
|
0x00000002 0x00000001 0x00000004 0x00000005
|
|
|
|
|
0x00000004 0x00000009 0x0000000d 0x0000059f
|
|
|
|
|
0x00000000 0x00000003 0x00000003 0x00000003
|
|
|
|
|
0x00000003 0x00000001 0x0000000b 0x000000c8
|
|
|
|
|
0x00000003 0x00000007 0x00000004 0x0000000f
|
|
|
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
|
|
|
0x00000000 0x00000000 0x00000083 0xa06204ae
|
|
|
|
|
0x007dc010 0x00000000 0x00000000 0x00000000
|
|
|
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emc-table@380000 {
|
|
|
|
|
reg = <380000>;
|
|
|
|
|
compatible = "nvidia,tegra20-emc-table";
|
|
|
|
|
clock-frequency = <380000>;
|
|
|
|
|
nvidia,emc-registers = <0x00000017 0x0000004b
|
|
|
|
|
0x00000012 0x00000006 0x00000004 0x00000005
|
|
|
|
|
0x00000003 0x0000000c 0x00000006 0x00000006
|
|
|
|
|
0x00000003 0x00000001 0x00000004 0x00000005
|
|
|
|
|
0x00000004 0x00000009 0x0000000d 0x00000b5f
|
|
|
|
|
0x00000000 0x00000003 0x00000003 0x00000006
|
|
|
|
|
0x00000006 0x00000001 0x00000011 0x000000c8
|
|
|
|
|
0x00000003 0x0000000e 0x00000007 0x0000000f
|
|
|
|
|
0x00000002 0x00000000 0x00000000 0x00000002
|
|
|
|
|
0x00000000 0x00000000 0x00000083 0xe044048b
|
|
|
|
|
0x007d8010 0x00000000 0x00000000 0x00000000
|
|
|
|
|
0x00000000 0x00000000 0x00000000 0x00000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@c5000000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-phy@c5000000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vbus_reg>;
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@c5004000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-phy@c5004000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
|
|
|
|
|
GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@c5008000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-phy@c5008000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci@c8000000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
keep-power-in-suspend;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci@c8000400 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
|
|
|
|
|
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdhci@c8000600 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
non-removable;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
clk32k_in: clock@0 {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
reg=<0>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "Power";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
2013-12-02 20:09:57 +07:00
|
|
|
linux,code = <KEY_POWER>;
|
2013-11-27 04:43:45 +07:00
|
|
|
gpio-key,wakeup;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lid {
|
|
|
|
|
label = "Lid";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
linux,input-type = <5>; /* EV_SW */
|
|
|
|
|
linux,code = <0>; /* SW_LID */
|
|
|
|
|
debounce-interval = <1>;
|
|
|
|
|
gpio-key,wakeup;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-06-21 04:58:34 +07:00
|
|
|
regulators {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
vdd_5v0_reg: regulator@0 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
regulator-name = "vdd_5v0";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
regulator@1 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
regulator-name = "vdd_1v5";
|
|
|
|
|
regulator-min-microvolt = <1500000>;
|
|
|
|
|
regulator-max-microvolt = <1500000>;
|
2013-02-13 07:25:15 +07:00
|
|
|
gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
|
2012-06-21 04:58:34 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
regulator@2 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
regulator-name = "vdd_1v2";
|
|
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
2013-02-13 07:25:15 +07:00
|
|
|
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
|
2012-06-21 04:58:34 +07:00
|
|
|
enable-active-high;
|
|
|
|
|
};
|
2013-05-16 21:12:57 +07:00
|
|
|
|
|
|
|
|
vbus_reg: regulator@3 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <3>;
|
|
|
|
|
regulator-name = "vdd_vbus_wup1";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
2013-07-02 04:07:05 +07:00
|
|
|
enable-active-high;
|
2013-08-02 01:26:01 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
|
ARM: tegra: always enable USB VBUS regulators
This fixes a regression exposed during the merge window by commit
9f310de "ARM: tegra: fix VBUS regulator GPIO polarity in DT"; namely that
USB VBUS doesn't get turned on, so USB devices are not detected. This
affects the internal USB port on TrimSlice (i.e. the USB->SATA bridge, to
which the SSD is connected) and the external port(s) on Seaboard/
Springbank and Whistler.
The Tegra DT as written in v3.11 allows two paths to enable USB VBUS:
1) Via the legacy DT binding for the USB controller; it can directly
acquire a VBUS GPIO and activate it.
2) Via a regulator for VBUS, which is referenced by the new DT binding
for the USB controller.
Those two methods both use the same GPIO, and hence whichever of the
USB controller and regulator gets probed first ends up owning the GPIO.
In practice, the USB driver only supports path (1) above, since the
patches to support the new USB binding are not present until v3.12:-(
In practice, the regulator ends up being probed first and owning the
GPIO. Since nothing enables the regulator (the USB driver code is not
yet present), the regulator ends up being turned off. This originally
caused no problem, because the polarity in the regulator definition was
incorrect, so attempting to turn off the regulator actually turned it
on, and everything worked:-(
However, when testing the new USB driver code in v3.12, I noticed the
incorrect polarity and fixed it in commit 9f310de "ARM: tegra: fix VBUS
regulator GPIO polarity in DT". In the context of v3.11, this patch then
caused the USB VBUS to actually turn off, which broke USB ports with VBUS
control. I got this patch included in v3.11-rc1 since it fixed a bug in
device tree (incorrect polarity specification), and hence was suitable to
be included early in the rc series. I evidently did not test the patch at
all, or correctly, in the context of v3.11, and hence did not notice the
issue that I have explained above:-(
Fix this by making the USB VBUS regulators always enabled. This way, if
the regulator owns the GPIO, it will always be turned on, even if there
is no USB driver code to request the regulator be turned on. Even
ignoring this bug, this is a reasonable way to configure the HW anyway.
If this patch is applied to v3.11, it will cause a couple pretty trivial
conflicts in tegra20-{trimslice,seaboard}.dts when creating v3.12, since
the context right above the added lines changed in patches destined for
v3.12.
Reported-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-21 03:00:13 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2013-05-16 21:12:57 +07:00
|
|
|
};
|
2012-06-21 04:58:34 +07:00
|
|
|
};
|
|
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-wm8903-seaboard",
|
|
|
|
|
"nvidia,tegra-audio-wm8903";
|
|
|
|
|
nvidia,model = "NVIDIA Tegra Seaboard";
|
2011-10-19 01:06:06 +07:00
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
nvidia,audio-routing =
|
|
|
|
|
"Headphone Jack", "HPOUTR",
|
|
|
|
|
"Headphone Jack", "HPOUTL",
|
|
|
|
|
"Int Spk", "ROP",
|
|
|
|
|
"Int Spk", "RON",
|
|
|
|
|
"Int Spk", "LOP",
|
|
|
|
|
"Int Spk", "LON",
|
|
|
|
|
"Mic Jack", "MICBIAS",
|
|
|
|
|
"IN1R", "Mic Jack";
|
2012-04-13 04:46:49 +07:00
|
|
|
|
2012-05-12 06:03:26 +07:00
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&wm8903>;
|
|
|
|
|
|
2013-02-13 07:25:15 +07:00
|
|
|
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
|
2013-03-27 05:45:52 +07:00
|
|
|
|
2013-05-22 23:45:32 +07:00
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA20_CLK_CDEV1>;
|
2013-03-27 05:45:52 +07:00
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
2012-04-13 04:46:49 +07:00
|
|
|
};
|
2011-07-20 06:26:54 +07:00
|
|
|
};
|