2015-07-09 16:50:08 +07:00
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/*
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* skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
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*
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* Copyright (C) 2014-2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*/
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "skl.h"
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2015-10-07 17:31:57 +07:00
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#include "skl-topology.h"
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2015-12-18 16:42:04 +07:00
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#include "skl-sst-dsp.h"
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#include "skl-sst-ipc.h"
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2015-07-09 16:50:08 +07:00
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#define HDA_MONO 1
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#define HDA_STEREO 2
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2015-11-28 16:31:46 +07:00
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#define HDA_QUAD 4
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2015-07-09 16:50:08 +07:00
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static struct snd_pcm_hardware azx_pcm_hw = {
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.info = (SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE |
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2015-12-18 16:42:09 +07:00
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SNDRV_PCM_INFO_RESUME |
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2015-07-09 16:50:08 +07:00
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SNDRV_PCM_INFO_SYNC_START |
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SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
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SNDRV_PCM_INFO_HAS_LINK_ATIME |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
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2015-11-23 23:56:26 +07:00
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE |
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SNDRV_PCM_FMTBIT_S24_LE,
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.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
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SNDRV_PCM_RATE_8000,
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.rate_min = 8000,
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2015-07-09 16:50:08 +07:00
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.rate_max = 48000,
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2015-11-28 16:31:46 +07:00
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.channels_min = 1,
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2016-04-14 11:37:35 +07:00
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.channels_max = 8,
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2015-07-09 16:50:08 +07:00
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.buffer_bytes_max = AZX_MAX_BUF_SIZE,
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.period_bytes_min = 128,
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.period_bytes_max = AZX_MAX_BUF_SIZE / 2,
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.periods_min = 2,
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.periods_max = AZX_MAX_FRAG,
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.fifo_size = 0,
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};
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static inline
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struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
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{
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return substream->runtime->private_data;
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}
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static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
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{
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struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
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struct hdac_stream *hstream = hdac_stream(stream);
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struct hdac_bus *bus = hstream->bus;
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return hbus_to_ebus(bus);
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}
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static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
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struct snd_pcm_substream *substream,
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size_t size)
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{
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struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
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hdac_stream(stream)->bufsize = 0;
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hdac_stream(stream)->period_bytes = 0;
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hdac_stream(stream)->format_val = 0;
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return snd_pcm_lib_malloc_pages(substream, size);
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}
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static int skl_substream_free_pages(struct hdac_bus *bus,
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struct snd_pcm_substream *substream)
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{
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return snd_pcm_lib_free_pages(substream);
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}
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static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
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struct snd_pcm_runtime *runtime)
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{
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snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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/* avoid wrap-around with wall-clock */
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snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
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20, 178000000);
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}
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2015-07-09 16:50:11 +07:00
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static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
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{
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if (ebus->ppcap)
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return HDAC_EXT_STREAM_TYPE_HOST;
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else
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return HDAC_EXT_STREAM_TYPE_COUPLED;
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}
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2015-12-04 01:00:00 +07:00
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/*
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* check if the stream opened is marked as ignore_suspend by machine, if so
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* then enable suspend_active refcount
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*
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* The count supend_active does not need lock as it is used in open/close
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* and suspend context
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*/
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static void skl_set_suspend_active(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai, bool enable)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
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struct snd_soc_dapm_widget *w;
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struct skl *skl = ebus_to_skl(ebus);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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w = dai->playback_widget;
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else
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w = dai->capture_widget;
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if (w->ignore_suspend && enable)
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skl->supend_active++;
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else if (w->ignore_suspend && !enable)
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skl->supend_active--;
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}
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2015-07-09 16:50:08 +07:00
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static int skl_pcm_open(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
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struct hdac_ext_stream *stream;
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct skl_dma_params *dma_params;
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dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
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stream = snd_hdac_ext_stream_assign(ebus, substream,
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2015-07-09 16:50:11 +07:00
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skl_get_host_stream_type(ebus));
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2015-07-09 16:50:08 +07:00
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if (stream == NULL)
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return -EBUSY;
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skl_set_pcm_constrains(ebus, runtime);
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/*
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* disable WALLCLOCK timestamps for capture streams
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* until we figure out how to handle digital inputs
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*/
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
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runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
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runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
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}
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runtime->private_data = stream;
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dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
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if (!dma_params)
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return -ENOMEM;
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dma_params->stream_tag = hdac_stream(stream)->stream_tag;
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snd_soc_dai_set_dma_data(dai, substream, dma_params);
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dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
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dma_params->stream_tag);
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2015-12-04 01:00:00 +07:00
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skl_set_suspend_active(substream, dai, true);
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2015-07-09 16:50:08 +07:00
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snd_pcm_set_sync(substream);
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return 0;
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}
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static int skl_get_format(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
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struct skl_dma_params *dma_params;
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2015-07-09 16:50:11 +07:00
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struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
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2015-07-09 16:50:08 +07:00
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int format_val = 0;
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2015-07-09 16:50:11 +07:00
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if (ebus->ppcap) {
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struct snd_pcm_runtime *runtime = substream->runtime;
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format_val = snd_hdac_calc_stream_format(runtime->rate,
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runtime->channels,
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runtime->format,
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32, 0);
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} else {
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struct snd_soc_dai *codec_dai = rtd->codec_dai;
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dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
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if (dma_params)
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format_val = dma_params->format;
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}
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2015-07-09 16:50:08 +07:00
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return format_val;
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}
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2016-02-05 13:49:07 +07:00
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static int skl_be_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct skl *skl = get_skl_ctx(dai->dev);
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struct skl_sst *ctx = skl->skl_sst;
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struct skl_module_cfg *mconfig;
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2016-04-28 20:15:27 +07:00
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if (dai->playback_widget->power || dai->capture_widget->power)
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2016-02-05 13:49:07 +07:00
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return 0;
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mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
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if (mconfig == NULL)
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return -EINVAL;
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return skl_dsp_set_dma_control(ctx, mconfig);
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}
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2015-07-09 16:50:08 +07:00
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static int skl_pcm_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
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2016-06-03 19:59:34 +07:00
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struct skl *skl = get_skl_ctx(dai->dev);
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2015-07-09 16:50:08 +07:00
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unsigned int format_val;
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int err;
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2016-06-03 19:59:34 +07:00
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struct skl_module_cfg *mconfig;
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2015-07-09 16:50:08 +07:00
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dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
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2016-06-03 19:59:34 +07:00
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mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
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2015-07-09 16:50:08 +07:00
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format_val = skl_get_format(substream, dai);
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dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
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hdac_stream(stream)->stream_tag, format_val);
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snd_hdac_stream_reset(hdac_stream(stream));
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2016-06-03 19:59:34 +07:00
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/* In case of XRUN recovery, reset the FW pipe to clean state */
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if (mconfig && (substream->runtime->status->state ==
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SNDRV_PCM_STATE_XRUN))
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skl_reset_pipe(skl->skl_sst, mconfig->pipe);
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2015-07-09 16:50:08 +07:00
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err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
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if (err < 0)
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return err;
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err = snd_hdac_stream_setup(hdac_stream(stream));
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if (err < 0)
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return err;
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hdac_stream(stream)->prepared = 1;
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return err;
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}
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static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
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2015-07-09 16:50:11 +07:00
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struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
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2015-07-09 16:50:08 +07:00
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struct snd_pcm_runtime *runtime = substream->runtime;
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2015-10-07 17:31:57 +07:00
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struct skl_pipe_params p_params = {0};
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struct skl_module_cfg *m_cfg;
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2015-07-09 16:50:11 +07:00
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int ret, dma_id;
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2015-07-09 16:50:08 +07:00
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dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
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ret = skl_substream_alloc_pages(ebus, substream,
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params_buffer_bytes(params));
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if (ret < 0)
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return ret;
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dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
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runtime->rate, runtime->channels, runtime->format);
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2015-07-09 16:50:11 +07:00
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dma_id = hdac_stream(stream)->stream_tag - 1;
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dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
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2015-10-07 17:31:57 +07:00
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p_params.s_fmt = snd_pcm_format_width(params_format(params));
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p_params.ch = params_channels(params);
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p_params.s_freq = params_rate(params);
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p_params.host_dma_id = dma_id;
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p_params.stream = substream->stream;
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m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
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if (m_cfg)
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skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
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2015-07-09 16:50:08 +07:00
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return 0;
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}
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static void skl_pcm_close(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
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2015-07-09 16:50:11 +07:00
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struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
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2015-07-09 16:50:08 +07:00
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struct skl_dma_params *dma_params = NULL;
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2015-12-18 16:42:04 +07:00
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struct skl *skl = ebus_to_skl(ebus);
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2015-07-09 16:50:08 +07:00
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dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
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2015-07-09 16:50:11 +07:00
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snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
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2015-07-09 16:50:08 +07:00
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dma_params = snd_soc_dai_get_dma_data(dai, substream);
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/*
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* now we should set this to NULL as we are freeing by the
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* dma_params
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*/
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|
|
snd_soc_dai_set_dma_data(dai, substream, NULL);
|
2015-12-04 01:00:00 +07:00
|
|
|
skl_set_suspend_active(substream, dai, false);
|
2015-07-09 16:50:08 +07:00
|
|
|
|
2015-12-18 16:42:04 +07:00
|
|
|
/*
|
|
|
|
* check if close is for "Reference Pin" and set back the
|
|
|
|
* CGCTL.MISCBDCGE if disabled by driver
|
|
|
|
*/
|
|
|
|
if (!strncmp(dai->name, "Reference Pin", 13) &&
|
|
|
|
skl->skl_sst->miscbdcg_disabled) {
|
|
|
|
skl->skl_sst->enable_miscbdcge(dai->dev, true);
|
|
|
|
skl->skl_sst->miscbdcg_disabled = false;
|
|
|
|
}
|
|
|
|
|
2015-07-09 16:50:08 +07:00
|
|
|
kfree(dma_params);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
|
|
|
|
struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
|
|
|
|
|
|
|
|
dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
|
|
|
|
|
|
|
|
snd_hdac_stream_cleanup(hdac_stream(stream));
|
|
|
|
hdac_stream(stream)->prepared = 0;
|
|
|
|
|
|
|
|
return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:31:57 +07:00
|
|
|
static int skl_be_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct skl_pipe_params p_params = {0};
|
|
|
|
|
|
|
|
p_params.s_fmt = snd_pcm_format_width(params_format(params));
|
|
|
|
p_params.ch = params_channels(params);
|
|
|
|
p_params.s_freq = params_rate(params);
|
|
|
|
p_params.stream = substream->stream;
|
|
|
|
|
2015-10-27 07:22:45 +07:00
|
|
|
return skl_tplg_be_update_params(dai, &p_params);
|
2015-10-07 17:31:57 +07:00
|
|
|
}
|
|
|
|
|
2015-10-27 07:22:53 +07:00
|
|
|
static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
|
|
|
|
int cmd)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = get_bus_ctx(substream);
|
|
|
|
struct hdac_bus *bus = ebus_to_hbus(ebus);
|
|
|
|
struct hdac_ext_stream *stream;
|
|
|
|
int start;
|
|
|
|
unsigned long cookie;
|
|
|
|
struct hdac_stream *hstr;
|
|
|
|
|
|
|
|
stream = get_hdac_ext_stream(substream);
|
|
|
|
hstr = hdac_stream(stream);
|
|
|
|
|
|
|
|
if (!hstr->prepared)
|
|
|
|
return -EPIPE;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
start = 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
start = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_irqsave(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
if (start) {
|
|
|
|
snd_hdac_stream_start(hdac_stream(stream), true);
|
|
|
|
snd_hdac_stream_timecounter_init(hstr, 0);
|
|
|
|
} else {
|
|
|
|
snd_hdac_stream_stop(hdac_stream(stream));
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:31:57 +07:00
|
|
|
static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct skl *skl = get_skl_ctx(dai->dev);
|
|
|
|
struct skl_sst *ctx = skl->skl_sst;
|
|
|
|
struct skl_module_cfg *mconfig;
|
2015-11-23 23:56:24 +07:00
|
|
|
struct hdac_ext_bus *ebus = get_bus_ctx(substream);
|
|
|
|
struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
|
2016-04-28 20:15:28 +07:00
|
|
|
struct snd_soc_dapm_widget *w;
|
2015-10-27 07:22:53 +07:00
|
|
|
int ret;
|
2015-10-07 17:31:57 +07:00
|
|
|
|
|
|
|
mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
|
|
|
|
if (!mconfig)
|
|
|
|
return -EIO;
|
|
|
|
|
2016-04-28 20:15:28 +07:00
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
w = dai->playback_widget;
|
|
|
|
else
|
|
|
|
w = dai->capture_widget;
|
|
|
|
|
2015-10-07 17:31:57 +07:00
|
|
|
switch (cmd) {
|
2015-11-23 23:56:24 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
2016-04-28 20:15:28 +07:00
|
|
|
if (!w->ignore_suspend) {
|
|
|
|
skl_pcm_prepare(substream, dai);
|
|
|
|
/*
|
|
|
|
* enable DMA Resume enable bit for the stream, set the
|
|
|
|
* dpib & lpib position to resume before starting the
|
|
|
|
* DMA
|
|
|
|
*/
|
|
|
|
snd_hdac_ext_stream_drsm_enable(ebus, true,
|
|
|
|
hdac_stream(stream)->index);
|
|
|
|
snd_hdac_ext_stream_set_dpibr(ebus, stream,
|
|
|
|
stream->dpib);
|
|
|
|
snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
|
|
|
|
}
|
2015-12-18 16:42:07 +07:00
|
|
|
|
2015-10-27 07:22:53 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
2015-10-07 17:31:57 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2015-10-27 07:22:53 +07:00
|
|
|
/*
|
|
|
|
* Start HOST DMA and Start FE Pipe.This is to make sure that
|
|
|
|
* there are no underrun/overrun in the case when the FE
|
|
|
|
* pipeline is started but there is a delay in starting the
|
|
|
|
* DMA channel on the host.
|
|
|
|
*/
|
2015-11-23 23:56:24 +07:00
|
|
|
snd_hdac_ext_stream_decouple(ebus, stream, true);
|
2015-10-27 07:22:53 +07:00
|
|
|
ret = skl_decoupled_trigger(substream, cmd);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2015-10-07 17:31:57 +07:00
|
|
|
return skl_run_pipe(ctx, mconfig->pipe);
|
2015-10-27 07:22:53 +07:00
|
|
|
break;
|
2015-10-07 17:31:57 +07:00
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
2015-10-27 07:22:53 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
/*
|
|
|
|
* Stop FE Pipe first and stop DMA. This is to make sure that
|
|
|
|
* there are no underrun/overrun in the case if there is a delay
|
|
|
|
* between the two operations.
|
|
|
|
*/
|
|
|
|
ret = skl_stop_pipe(ctx, mconfig->pipe);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = skl_decoupled_trigger(substream, cmd);
|
2016-04-28 20:15:28 +07:00
|
|
|
if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
|
2015-12-18 16:42:07 +07:00
|
|
|
/* save the dpib and lpib positions */
|
|
|
|
stream->dpib = readl(ebus->bus.remap_addr +
|
|
|
|
AZX_REG_VS_SDXDPIB_XBASE +
|
|
|
|
(AZX_REG_VS_SDXDPIB_XINTERVAL *
|
|
|
|
hdac_stream(stream)->index));
|
|
|
|
|
|
|
|
stream->lpib = snd_hdac_stream_get_pos_lpib(
|
|
|
|
hdac_stream(stream));
|
2015-11-23 23:56:24 +07:00
|
|
|
snd_hdac_ext_stream_decouple(ebus, stream, false);
|
2015-12-18 16:42:07 +07:00
|
|
|
}
|
2015-10-27 07:22:53 +07:00
|
|
|
break;
|
2015-10-07 17:31:57 +07:00
|
|
|
|
|
|
|
default:
|
2015-10-27 07:22:53 +07:00
|
|
|
return -EINVAL;
|
2015-10-07 17:31:57 +07:00
|
|
|
}
|
2015-10-27 07:22:53 +07:00
|
|
|
|
|
|
|
return 0;
|
2015-10-07 17:31:57 +07:00
|
|
|
}
|
|
|
|
|
2015-07-09 16:50:11 +07:00
|
|
|
static int skl_link_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
|
|
|
|
struct hdac_ext_stream *link_dev;
|
|
|
|
struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
|
2016-02-17 23:04:05 +07:00
|
|
|
struct hdac_ext_dma_params *dma_params;
|
2015-07-09 16:50:11 +07:00
|
|
|
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
2015-10-07 17:31:57 +07:00
|
|
|
struct skl_pipe_params p_params = {0};
|
2015-07-09 16:50:11 +07:00
|
|
|
|
|
|
|
link_dev = snd_hdac_ext_stream_assign(ebus, substream,
|
|
|
|
HDAC_EXT_STREAM_TYPE_LINK);
|
|
|
|
if (!link_dev)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
|
|
|
|
|
|
|
|
/* set the stream tag in the codec dai dma params */
|
2016-02-17 23:04:05 +07:00
|
|
|
dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
|
2015-07-09 16:50:11 +07:00
|
|
|
if (dma_params)
|
|
|
|
dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
|
2015-10-07 17:31:57 +07:00
|
|
|
|
|
|
|
p_params.s_fmt = snd_pcm_format_width(params_format(params));
|
|
|
|
p_params.ch = params_channels(params);
|
|
|
|
p_params.s_freq = params_rate(params);
|
|
|
|
p_params.stream = substream->stream;
|
|
|
|
p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
|
|
|
|
|
2015-10-27 07:22:45 +07:00
|
|
|
return skl_tplg_be_update_params(dai, &p_params);
|
2015-07-09 16:50:11 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
|
|
|
|
struct hdac_ext_stream *link_dev =
|
|
|
|
snd_soc_dai_get_dma_data(dai, substream);
|
|
|
|
unsigned int format_val = 0;
|
|
|
|
struct skl_dma_params *dma_params;
|
|
|
|
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
|
|
|
struct hdac_ext_link *link;
|
2016-06-03 19:59:34 +07:00
|
|
|
struct skl *skl = get_skl_ctx(dai->dev);
|
|
|
|
struct skl_module_cfg *mconfig = NULL;
|
2015-07-09 16:50:11 +07:00
|
|
|
|
|
|
|
dma_params = (struct skl_dma_params *)
|
|
|
|
snd_soc_dai_get_dma_data(codec_dai, substream);
|
|
|
|
if (dma_params)
|
|
|
|
format_val = dma_params->format;
|
|
|
|
dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
|
|
|
|
hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
|
|
|
|
|
|
|
|
link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
|
|
|
|
if (!link)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-12-18 16:42:08 +07:00
|
|
|
snd_hdac_ext_link_stream_reset(link_dev);
|
|
|
|
|
2016-06-03 19:59:34 +07:00
|
|
|
/* In case of XRUN recovery, reset the FW pipe to clean state */
|
|
|
|
mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
|
|
|
|
if (mconfig && (substream->runtime->status->state ==
|
|
|
|
SNDRV_PCM_STATE_XRUN))
|
|
|
|
skl_reset_pipe(skl->skl_sst, mconfig->pipe);
|
|
|
|
|
2015-12-18 16:42:08 +07:00
|
|
|
snd_hdac_ext_link_stream_setup(link_dev, format_val);
|
|
|
|
|
2015-07-09 16:50:11 +07:00
|
|
|
snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
|
|
|
|
link_dev->link_prepared = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
|
|
|
|
int cmd, struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct hdac_ext_stream *link_dev =
|
|
|
|
snd_soc_dai_get_dma_data(dai, substream);
|
2015-12-18 16:42:08 +07:00
|
|
|
struct hdac_ext_bus *ebus = get_bus_ctx(substream);
|
|
|
|
struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
|
2015-07-09 16:50:11 +07:00
|
|
|
|
|
|
|
dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
|
|
|
|
switch (cmd) {
|
2015-12-18 16:42:08 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
skl_link_pcm_prepare(substream, dai);
|
2015-07-09 16:50:11 +07:00
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2015-12-18 16:42:08 +07:00
|
|
|
snd_hdac_ext_stream_decouple(ebus, stream, true);
|
2015-07-09 16:50:11 +07:00
|
|
|
snd_hdac_ext_link_stream_start(link_dev);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
snd_hdac_ext_link_stream_clear(link_dev);
|
2015-12-18 16:42:08 +07:00
|
|
|
if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
|
|
|
|
snd_hdac_ext_stream_decouple(ebus, stream, false);
|
2015-07-09 16:50:11 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int skl_link_hw_free(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
|
|
|
|
struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
|
|
|
|
struct hdac_ext_stream *link_dev =
|
|
|
|
snd_soc_dai_get_dma_data(dai, substream);
|
|
|
|
struct hdac_ext_link *link;
|
|
|
|
|
|
|
|
dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
|
|
|
|
|
|
|
|
link_dev->link_prepared = 0;
|
|
|
|
|
|
|
|
link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
|
|
|
|
if (!link)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
|
|
|
|
snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-07-09 16:50:08 +07:00
|
|
|
static struct snd_soc_dai_ops skl_pcm_dai_ops = {
|
|
|
|
.startup = skl_pcm_open,
|
|
|
|
.shutdown = skl_pcm_close,
|
|
|
|
.prepare = skl_pcm_prepare,
|
|
|
|
.hw_params = skl_pcm_hw_params,
|
|
|
|
.hw_free = skl_pcm_hw_free,
|
2015-10-07 17:31:57 +07:00
|
|
|
.trigger = skl_pcm_trigger,
|
2015-07-09 16:50:08 +07:00
|
|
|
};
|
|
|
|
|
2015-07-09 16:50:11 +07:00
|
|
|
static struct snd_soc_dai_ops skl_dmic_dai_ops = {
|
2015-10-07 17:31:57 +07:00
|
|
|
.hw_params = skl_be_hw_params,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
|
|
|
|
.hw_params = skl_be_hw_params,
|
2016-02-05 13:49:07 +07:00
|
|
|
.prepare = skl_be_prepare,
|
2015-07-09 16:50:11 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct snd_soc_dai_ops skl_link_dai_ops = {
|
|
|
|
.prepare = skl_link_pcm_prepare,
|
|
|
|
.hw_params = skl_link_hw_params,
|
|
|
|
.hw_free = skl_link_hw_free,
|
|
|
|
.trigger = skl_link_pcm_trigger,
|
|
|
|
};
|
|
|
|
|
2015-07-09 16:50:08 +07:00
|
|
|
static struct snd_soc_dai_driver skl_platform_dai[] = {
|
|
|
|
{
|
|
|
|
.name = "System Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "System Playback",
|
|
|
|
.channels_min = HDA_MONO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "System Capture",
|
|
|
|
.channels_min = HDA_MONO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-07-09 16:50:11 +07:00
|
|
|
{
|
|
|
|
.name = "Reference Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "Reference Capture",
|
|
|
|
.channels_min = HDA_MONO,
|
2015-11-28 16:31:46 +07:00
|
|
|
.channels_max = HDA_QUAD,
|
2015-07-09 16:50:11 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-07-09 16:50:08 +07:00
|
|
|
{
|
|
|
|
.name = "Deepbuffer Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "Deepbuffer Playback",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "LowLatency Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "Low Latency Playback",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-11-28 16:31:46 +07:00
|
|
|
{
|
|
|
|
.name = "DMIC Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "DMIC Capture",
|
|
|
|
.channels_min = HDA_MONO,
|
|
|
|
.channels_max = HDA_QUAD,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
2016-02-17 23:04:07 +07:00
|
|
|
{
|
|
|
|
.name = "HDMI1 Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "HDMI1 Playback",
|
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2016-02-17 23:04:07 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
|
|
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
|
|
|
|
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
|
|
|
|
SNDRV_PCM_RATE_192000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "HDMI2 Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "HDMI2 Playback",
|
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2016-02-17 23:04:07 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
|
|
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
|
|
|
|
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
|
|
|
|
SNDRV_PCM_RATE_192000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "HDMI3 Pin",
|
|
|
|
.ops = &skl_pcm_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "HDMI3 Playback",
|
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2016-02-17 23:04:07 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
|
|
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
|
|
|
|
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
|
|
|
|
SNDRV_PCM_RATE_192000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-11-28 16:31:46 +07:00
|
|
|
|
2015-07-09 16:50:11 +07:00
|
|
|
/* BE CPU Dais */
|
2015-10-07 17:31:57 +07:00
|
|
|
{
|
|
|
|
.name = "SSP0 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp0 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp0 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-11-06 00:23:06 +07:00
|
|
|
{
|
|
|
|
.name = "SSP1 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp1 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp1 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
2016-05-10 23:32:05 +07:00
|
|
|
{
|
|
|
|
.name = "SSP2 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp2 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp2 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "SSP3 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp3 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp3 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "SSP4 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp4 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp4 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "SSP5 Pin",
|
|
|
|
.ops = &skl_be_ssp_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "ssp5 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "ssp5 Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-07-09 16:50:11 +07:00
|
|
|
{
|
2016-02-17 23:04:07 +07:00
|
|
|
.name = "iDisp1 Pin",
|
2015-07-09 16:50:11 +07:00
|
|
|
.ops = &skl_link_dai_ops,
|
|
|
|
.playback = {
|
2016-02-17 23:04:07 +07:00
|
|
|
.stream_name = "iDisp1 Tx",
|
2015-07-09 16:50:11 +07:00
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2015-07-09 16:50:11 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
|
2016-02-17 23:04:07 +07:00
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "iDisp2 Pin",
|
|
|
|
.ops = &skl_link_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "iDisp2 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2016-02-17 23:04:07 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
|
|
|
|
SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "iDisp3 Pin",
|
|
|
|
.ops = &skl_link_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "iDisp3 Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
2016-04-14 11:37:35 +07:00
|
|
|
.channels_max = 8,
|
2016-02-17 23:04:07 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
|
|
|
|
SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
|
|
|
|
SNDRV_PCM_FMTBIT_S24_LE,
|
2015-07-09 16:50:11 +07:00
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "DMIC01 Pin",
|
|
|
|
.ops = &skl_dmic_dai_ops,
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "DMIC01 Rx",
|
2015-11-28 16:31:46 +07:00
|
|
|
.channels_min = HDA_MONO,
|
|
|
|
.channels_max = HDA_QUAD,
|
2015-07-09 16:50:11 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "HD-Codec Pin",
|
|
|
|
.ops = &skl_link_dai_ops,
|
|
|
|
.playback = {
|
|
|
|
.stream_name = "HD-Codec Tx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "HD-Codec Rx",
|
|
|
|
.channels_min = HDA_STEREO,
|
|
|
|
.channels_max = HDA_STEREO,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
},
|
2015-07-09 16:50:08 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static int skl_platform_open(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime;
|
|
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
|
|
struct snd_soc_dai_link *dai_link = rtd->dai_link;
|
|
|
|
|
|
|
|
dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
|
|
|
|
dai_link->cpu_dai_name);
|
|
|
|
|
|
|
|
runtime = substream->runtime;
|
|
|
|
snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:31:57 +07:00
|
|
|
static int skl_coupled_trigger(struct snd_pcm_substream *substream,
|
2015-07-09 16:50:08 +07:00
|
|
|
int cmd)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = get_bus_ctx(substream);
|
|
|
|
struct hdac_bus *bus = ebus_to_hbus(ebus);
|
|
|
|
struct hdac_ext_stream *stream;
|
|
|
|
struct snd_pcm_substream *s;
|
|
|
|
bool start;
|
|
|
|
int sbits = 0;
|
|
|
|
unsigned long cookie;
|
|
|
|
struct hdac_stream *hstr;
|
|
|
|
|
|
|
|
stream = get_hdac_ext_stream(substream);
|
|
|
|
hstr = hdac_stream(stream);
|
|
|
|
|
|
|
|
dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
|
|
|
|
|
|
|
|
if (!hstr->prepared)
|
|
|
|
return -EPIPE;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
start = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
start = false;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
stream = get_hdac_ext_stream(s);
|
|
|
|
sbits |= 1 << hdac_stream(stream)->index;
|
|
|
|
snd_pcm_trigger_done(s, substream);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_irqsave(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
/* first, set SYNC bits of corresponding streams */
|
|
|
|
snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
|
|
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
|
continue;
|
|
|
|
stream = get_hdac_ext_stream(s);
|
|
|
|
if (start)
|
|
|
|
snd_hdac_stream_start(hdac_stream(stream), true);
|
|
|
|
else
|
|
|
|
snd_hdac_stream_stop(hdac_stream(stream));
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
snd_hdac_stream_sync(hstr, start, sbits);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
/* reset SYNC bits */
|
|
|
|
snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
|
|
|
|
if (start)
|
|
|
|
snd_hdac_stream_timecounter_init(hstr, sbits);
|
|
|
|
spin_unlock_irqrestore(&bus->reg_lock, cookie);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-07-09 16:50:11 +07:00
|
|
|
static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
|
|
|
|
int cmd)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = get_bus_ctx(substream);
|
|
|
|
|
2015-10-27 07:22:53 +07:00
|
|
|
if (!ebus->ppcap)
|
2015-10-07 17:31:57 +07:00
|
|
|
return skl_coupled_trigger(substream, cmd);
|
2015-10-27 07:22:53 +07:00
|
|
|
|
|
|
|
return 0;
|
2015-07-09 16:50:11 +07:00
|
|
|
}
|
|
|
|
|
2015-07-09 16:50:08 +07:00
|
|
|
/* calculate runtime delay from LPIB */
|
|
|
|
static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
|
|
|
|
struct hdac_ext_stream *sstream,
|
|
|
|
unsigned int pos)
|
|
|
|
{
|
|
|
|
struct hdac_bus *bus = ebus_to_hbus(ebus);
|
|
|
|
struct hdac_stream *hstream = hdac_stream(sstream);
|
|
|
|
struct snd_pcm_substream *substream = hstream->substream;
|
|
|
|
int stream = substream->stream;
|
|
|
|
unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
|
|
|
|
int delay;
|
|
|
|
|
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
delay = pos - lpib_pos;
|
|
|
|
else
|
|
|
|
delay = lpib_pos - pos;
|
|
|
|
|
|
|
|
if (delay < 0) {
|
|
|
|
if (delay >= hstream->delay_negative_threshold)
|
|
|
|
delay = 0;
|
|
|
|
else
|
|
|
|
delay += hstream->bufsize;
|
|
|
|
}
|
2016-02-05 13:49:04 +07:00
|
|
|
|
|
|
|
if (hstream->bufsize == delay)
|
|
|
|
delay = 0;
|
2015-07-09 16:50:08 +07:00
|
|
|
|
|
|
|
if (delay >= hstream->period_bytes) {
|
|
|
|
dev_info(bus->dev,
|
|
|
|
"Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
|
|
|
|
delay, hstream->period_bytes);
|
|
|
|
delay = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return bytes_to_frames(substream->runtime, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
|
|
|
|
int codec_delay)
|
|
|
|
{
|
|
|
|
struct hdac_stream *hstr = hdac_stream(hstream);
|
|
|
|
struct snd_pcm_substream *substream = hstr->substream;
|
2015-10-30 22:04:20 +07:00
|
|
|
struct hdac_ext_bus *ebus;
|
2015-07-09 16:50:08 +07:00
|
|
|
unsigned int pos;
|
|
|
|
int delay;
|
|
|
|
|
|
|
|
/* use the position buffer as default */
|
|
|
|
pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
|
|
|
|
|
|
|
|
if (pos >= hdac_stream(hstream)->bufsize)
|
|
|
|
pos = 0;
|
|
|
|
|
|
|
|
if (substream->runtime) {
|
2015-10-30 22:04:20 +07:00
|
|
|
ebus = get_bus_ctx(substream);
|
2015-07-09 16:50:08 +07:00
|
|
|
delay = skl_get_delay_from_lpib(ebus, hstream, pos)
|
|
|
|
+ codec_delay;
|
|
|
|
substream->runtime->delay += delay;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
|
|
|
|
static snd_pcm_uframes_t skl_platform_pcm_pointer
|
|
|
|
(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
|
|
|
|
|
|
|
|
return bytes_to_frames(substream->runtime,
|
|
|
|
skl_get_position(hstream, 0));
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
|
|
|
|
u64 nsec)
|
|
|
|
{
|
|
|
|
struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
|
|
|
|
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
|
|
|
u64 codec_frames, codec_nsecs;
|
|
|
|
|
|
|
|
if (!codec_dai->driver->ops->delay)
|
|
|
|
return nsec;
|
|
|
|
|
|
|
|
codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
|
|
|
|
codec_nsecs = div_u64(codec_frames * 1000000000LL,
|
|
|
|
substream->runtime->rate);
|
|
|
|
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
|
|
return nsec + codec_nsecs;
|
|
|
|
|
|
|
|
return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int skl_get_time_info(struct snd_pcm_substream *substream,
|
|
|
|
struct timespec *system_ts, struct timespec *audio_ts,
|
|
|
|
struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
|
|
|
|
struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
|
|
|
|
{
|
|
|
|
struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
|
|
|
|
struct hdac_stream *hstr = hdac_stream(sstream);
|
|
|
|
u64 nsec;
|
|
|
|
|
|
|
|
if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
|
|
|
|
(audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
|
|
|
|
|
|
|
|
snd_pcm_gettime(substream->runtime, system_ts);
|
|
|
|
|
|
|
|
nsec = timecounter_read(&hstr->tc);
|
|
|
|
nsec = div_u64(nsec, 3); /* can be optimized */
|
|
|
|
if (audio_tstamp_config->report_delay)
|
|
|
|
nsec = skl_adjust_codec_delay(substream, nsec);
|
|
|
|
|
|
|
|
*audio_ts = ns_to_timespec(nsec);
|
|
|
|
|
|
|
|
audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
|
|
|
|
audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
|
|
|
|
audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
|
|
|
|
|
|
|
|
} else {
|
|
|
|
audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_pcm_ops skl_platform_ops = {
|
|
|
|
.open = skl_platform_open,
|
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
|
|
.trigger = skl_platform_pcm_trigger,
|
|
|
|
.pointer = skl_platform_pcm_pointer,
|
|
|
|
.get_time_info = skl_get_time_info,
|
|
|
|
.mmap = snd_pcm_lib_default_mmap,
|
|
|
|
.page = snd_pcm_sgbuf_ops_page,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void skl_pcm_free(struct snd_pcm *pcm)
|
|
|
|
{
|
|
|
|
snd_pcm_lib_preallocate_free_for_all(pcm);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
|
|
|
|
|
|
|
|
static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
|
|
|
|
{
|
|
|
|
struct snd_soc_dai *dai = rtd->cpu_dai;
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
|
|
|
|
struct snd_pcm *pcm = rtd->pcm;
|
|
|
|
unsigned int size;
|
|
|
|
int retval = 0;
|
|
|
|
struct skl *skl = ebus_to_skl(ebus);
|
|
|
|
|
|
|
|
if (dai->driver->playback.channels_min ||
|
|
|
|
dai->driver->capture.channels_min) {
|
|
|
|
/* buffer pre-allocation */
|
|
|
|
size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
|
|
|
|
if (size > MAX_PREALLOC_SIZE)
|
|
|
|
size = MAX_PREALLOC_SIZE;
|
|
|
|
retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
|
|
|
|
SNDRV_DMA_TYPE_DEV_SG,
|
|
|
|
snd_dma_pci_data(skl->pci),
|
|
|
|
size, MAX_PREALLOC_SIZE);
|
|
|
|
if (retval) {
|
|
|
|
dev_err(dai->dev, "dma buffer allocationf fail\n");
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:31:57 +07:00
|
|
|
static int skl_platform_soc_probe(struct snd_soc_platform *platform)
|
|
|
|
{
|
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
|
2016-06-03 19:59:39 +07:00
|
|
|
struct skl *skl = ebus_to_skl(ebus);
|
|
|
|
int ret;
|
2015-10-07 17:31:57 +07:00
|
|
|
|
2016-06-03 19:59:39 +07:00
|
|
|
if (ebus->ppcap) {
|
|
|
|
ret = skl_tplg_init(platform, ebus);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(platform->dev, "Failed to init topology!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
skl->platform = platform;
|
|
|
|
}
|
2015-10-07 17:31:57 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-07-09 16:50:08 +07:00
|
|
|
static struct snd_soc_platform_driver skl_platform_drv = {
|
2015-10-07 17:31:57 +07:00
|
|
|
.probe = skl_platform_soc_probe,
|
2015-07-09 16:50:08 +07:00
|
|
|
.ops = &skl_platform_ops,
|
|
|
|
.pcm_new = skl_pcm_new,
|
|
|
|
.pcm_free = skl_pcm_free,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct snd_soc_component_driver skl_component = {
|
|
|
|
.name = "pcm",
|
|
|
|
};
|
|
|
|
|
|
|
|
int skl_platform_register(struct device *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
2015-10-07 17:31:57 +07:00
|
|
|
struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
|
|
|
|
struct skl *skl = ebus_to_skl(ebus);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&skl->ppl_list);
|
2015-07-09 16:50:08 +07:00
|
|
|
|
|
|
|
ret = snd_soc_register_platform(dev, &skl_platform_drv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "soc platform registration failed %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = snd_soc_register_component(dev, &skl_component,
|
|
|
|
skl_platform_dai,
|
|
|
|
ARRAY_SIZE(skl_platform_dai));
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "soc component registration failed %d\n", ret);
|
|
|
|
snd_soc_unregister_platform(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
int skl_platform_unregister(struct device *dev)
|
|
|
|
{
|
|
|
|
snd_soc_unregister_component(dev);
|
|
|
|
snd_soc_unregister_platform(dev);
|
|
|
|
return 0;
|
|
|
|
}
|