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ASoC: Intel: Skylake: Update DMIC DAIs and capabilities
On Skylake we can support upton 4DMICs on the PDM port, so update the PCM capabilities accordingly Also add a new DAI for DMIC pin which can be used for getting raw DMIC data Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Dharageswari.R <dharageswari.r@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -28,6 +28,7 @@
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#define HDA_MONO 1
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#define HDA_STEREO 2
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#define HDA_QUAD 4
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static struct snd_pcm_hardware azx_pcm_hw = {
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.info = (SNDRV_PCM_INFO_MMAP |
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@ -46,8 +47,8 @@ static struct snd_pcm_hardware azx_pcm_hw = {
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SNDRV_PCM_RATE_8000,
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.rate_min = 8000,
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.rate_max = 48000,
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.channels_min = 2,
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.channels_max = 2,
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.channels_min = 1,
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.channels_max = HDA_QUAD,
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.buffer_bytes_max = AZX_MAX_BUF_SIZE,
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.period_bytes_min = 128,
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.period_bytes_max = AZX_MAX_BUF_SIZE / 2,
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@ -560,7 +561,7 @@ static struct snd_soc_dai_driver skl_platform_dai[] = {
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.capture = {
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.stream_name = "Reference Capture",
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.channels_min = HDA_MONO,
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.channels_max = HDA_STEREO,
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.channels_max = HDA_QUAD,
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.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
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},
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@ -587,6 +588,18 @@ static struct snd_soc_dai_driver skl_platform_dai[] = {
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
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},
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},
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{
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.name = "DMIC Pin",
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.ops = &skl_pcm_dai_ops,
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.capture = {
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.stream_name = "DMIC Capture",
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.channels_min = HDA_MONO,
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.channels_max = HDA_QUAD,
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.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
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},
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},
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/* BE CPU Dais */
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{
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.name = "SSP0 Pin",
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@ -640,8 +653,8 @@ static struct snd_soc_dai_driver skl_platform_dai[] = {
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.ops = &skl_dmic_dai_ops,
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.capture = {
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.stream_name = "DMIC01 Rx",
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.channels_min = HDA_STEREO,
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.channels_max = HDA_STEREO,
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.channels_min = HDA_MONO,
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.channels_max = HDA_QUAD,
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.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
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},
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