2005-04-17 05:20:36 +07:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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2005-05-05 23:45:59 +07:00
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* Copyright (C) 2004 Maciej W. Rozycki
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2005-04-17 05:20:36 +07:00
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*/
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#ifndef __ASM_CPU_FEATURES_H
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#define __ASM_CPU_FEATURES_H
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <cpu-feature-overrides.h>
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/*
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* SMP assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known MIPS systems.
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*/
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#ifndef cpu_has_tlb
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#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
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#endif
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2013-11-14 23:12:23 +07:00
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#ifndef cpu_has_tlbinv
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#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
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#endif
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2013-11-14 23:12:24 +07:00
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#ifndef cpu_has_segments
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#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
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#endif
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2014-01-09 23:01:29 +07:00
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#ifndef cpu_has_eva
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#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
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#endif
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2014-07-14 18:43:28 +07:00
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#ifndef cpu_has_htw
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#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
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#endif
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2014-07-15 20:09:55 +07:00
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#ifndef cpu_has_rixiex
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#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
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#endif
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2014-07-14 16:32:14 +07:00
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#ifndef cpu_has_maar
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#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
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#endif
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2013-06-26 22:06:34 +07:00
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/*
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* For the moment we don't consider R6000 and R8000 so we can assume that
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* anything that doesn't support R4000-style exceptions and interrupts is
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* R3000-like. Users should still treat these two macro definitions as
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* opaque.
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*/
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#ifndef cpu_has_3kex
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#define cpu_has_3kex (!cpu_has_4kex)
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#endif
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2005-04-17 05:20:36 +07:00
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#ifndef cpu_has_4kex
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#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
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#endif
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2005-10-01 19:06:32 +07:00
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#ifndef cpu_has_3k_cache
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#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
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#endif
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#define cpu_has_6k_cache 0
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#define cpu_has_8k_cache 0
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#ifndef cpu_has_4k_cache
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#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
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#endif
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#ifndef cpu_has_tx39_cache
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#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
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#endif
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2008-12-12 06:33:27 +07:00
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#ifndef cpu_has_octeon_cache
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#define cpu_has_octeon_cache 0
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#endif
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2005-04-17 05:20:36 +07:00
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#ifndef cpu_has_fpu
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2006-04-05 15:45:47 +07:00
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#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
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2007-03-09 23:07:45 +07:00
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#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
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#else
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#define raw_cpu_has_fpu cpu_has_fpu
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2005-04-17 05:20:36 +07:00
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#endif
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#ifndef cpu_has_32fpr
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#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
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#endif
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#ifndef cpu_has_counter
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#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
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#endif
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#ifndef cpu_has_watch
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#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
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#endif
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#ifndef cpu_has_divec
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#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
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#endif
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#ifndef cpu_has_vce
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#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
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#endif
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#ifndef cpu_has_cache_cdex_p
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#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
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#endif
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#ifndef cpu_has_cache_cdex_s
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#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
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#endif
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#ifndef cpu_has_prefetch
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#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
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#endif
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#ifndef cpu_has_mcheck
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#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
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#endif
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#ifndef cpu_has_ejtag
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#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
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#endif
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#ifndef cpu_has_llsc
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#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
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#endif
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2009-07-14 01:15:19 +07:00
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#ifndef kernel_uses_llsc
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#define kernel_uses_llsc cpu_has_llsc
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#endif
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2005-05-05 23:45:59 +07:00
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#ifndef cpu_has_mips16
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#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
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#endif
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#ifndef cpu_has_mdmx
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2013-06-21 17:10:46 +07:00
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#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
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2005-05-05 23:45:59 +07:00
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#endif
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#ifndef cpu_has_mips3d
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2013-06-21 17:10:46 +07:00
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#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
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2005-05-05 23:45:59 +07:00
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#endif
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#ifndef cpu_has_smartmips
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2013-06-21 17:10:46 +07:00
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#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
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2005-05-05 23:45:59 +07:00
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#endif
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2014-05-29 04:52:07 +07:00
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2012-09-14 04:47:58 +07:00
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#ifndef cpu_has_rixi
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2014-05-29 04:52:07 +07:00
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# ifdef CONFIG_64BIT
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# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
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# else /* CONFIG_32BIT */
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# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
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# endif
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2012-09-14 04:47:58 +07:00
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#endif
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2014-05-29 04:52:07 +07:00
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2012-12-07 10:51:35 +07:00
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#ifndef cpu_has_mmips
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2013-05-25 03:54:10 +07:00
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# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
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# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
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# else
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# define cpu_has_mmips 0
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# endif
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2012-12-07 10:51:35 +07:00
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#endif
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2014-05-29 04:52:07 +07:00
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2005-04-17 05:20:36 +07:00
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#ifndef cpu_has_vtag_icache
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#endif
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#ifndef cpu_has_dc_aliases
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#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
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#endif
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#ifndef cpu_has_ic_fills_f_dc
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#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
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#endif
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2006-03-13 16:23:03 +07:00
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#ifndef cpu_has_pindexed_dcache
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2013-06-21 17:10:46 +07:00
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#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
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2006-03-13 16:23:03 +07:00
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#endif
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MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem
This and the next patch resolve memory corruption problems while CPU
hotplug. Without these patches, memory corruption can triggered easily
as below:
On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http://
code.google.com/p/byte-unixbench/) and a CPU hotplug script like this
(hotplug.sh):
while true; do
echo 0 >/sys/devices/system/cpu/cpu1/online
echo 0 >/sys/devices/system/cpu/cpu2/online
echo 0 >/sys/devices/system/cpu/cpu3/online
sleep 1
echo 1 >/sys/devices/system/cpu/cpu1/online
echo 1 >/sys/devices/system/cpu/cpu2/online
echo 1 >/sys/devices/system/cpu/cpu3/online
sleep 1
done
Run "hotplug.sh" and then run "spawn 10000", spawn will get segfault
after a few minutes.
This patch:
Currently, clear_page()/copy_page() are generated by Micro-assembler
dynamically. But they are unavailable until uasm_resolve_relocs() has
finished because jump labels are illegal before that. Since these
functions are shared by every CPU, we only call build_clear_page()/
build_copy_page() only once at boot time. Without this patch, programs
will get random memory corruption (segmentation fault, bus error, etc.)
while CPU Hotplug (e.g. one CPU is using clear_page() while another is
generating it in cpu_cache_init()).
For similar reasons we modify build_tlb_refill_handler()'s invocation.
V2:
1, Rework the code to make CPU#0 can be online/offline.
2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU
need a per-CPU tlb_refill_handler().
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongbing Hu <huhb@lemote.com>
Acked-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4994/
Acked-by: John Crispin <blogic@openwrt.org>
2013-03-17 18:49:38 +07:00
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#ifndef cpu_has_local_ebase
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#define cpu_has_local_ebase 1
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#endif
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2005-04-17 05:20:36 +07:00
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/*
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2013-01-22 18:59:30 +07:00
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* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
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2005-04-17 05:20:36 +07:00
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* such as the R10000 have I-Caches that snoop local stores; the embedded ones
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* don't. For maintaining I-cache coherency this means we need to flush the
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* D-cache all the way back to whever the I-cache does refills from, so the
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* I-cache has a chance to see the new data at all. Then we have to flush the
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* I-cache also.
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* Note we may have been rescheduled and may no longer be running on the CPU
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* that did the store so we can't optimize this into only doing the flush on
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* the local CPU.
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*/
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#ifndef cpu_icache_snoops_remote_store
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#ifdef CONFIG_SMP
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#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
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#else
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#define cpu_icache_snoops_remote_store 1
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#endif
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#endif
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2012-12-07 11:31:36 +07:00
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#ifndef cpu_has_mips_2
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# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
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#endif
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#ifndef cpu_has_mips_3
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# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
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#endif
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#ifndef cpu_has_mips_4
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# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
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#endif
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#ifndef cpu_has_mips_5
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# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
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#endif
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2013-06-21 17:10:46 +07:00
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#ifndef cpu_has_mips32r1
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2005-12-09 19:20:49 +07:00
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# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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2013-06-21 17:10:46 +07:00
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#endif
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#ifndef cpu_has_mips32r2
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2005-12-09 19:20:49 +07:00
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# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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2013-06-21 17:10:46 +07:00
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#endif
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#ifndef cpu_has_mips64r1
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2005-12-09 19:20:49 +07:00
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# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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2013-06-21 17:10:46 +07:00
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#endif
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#ifndef cpu_has_mips64r2
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2005-12-09 19:20:49 +07:00
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# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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2013-06-21 17:10:46 +07:00
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#endif
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2005-12-09 19:20:49 +07:00
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/*
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* Shortcuts ...
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*/
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2014-04-19 18:11:37 +07:00
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#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
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#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
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#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
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#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
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#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
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#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
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#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
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#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2)
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2005-12-09 19:20:49 +07:00
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#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
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#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
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2013-01-22 18:59:30 +07:00
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#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
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#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
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2008-10-28 16:37:47 +07:00
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#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
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cpu_has_mips64r1 | cpu_has_mips64r2)
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2005-12-09 19:20:49 +07:00
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2009-05-13 02:41:53 +07:00
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#ifndef cpu_has_mips_r2_exec_hazard
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#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
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#endif
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2009-04-19 08:21:22 +07:00
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/*
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* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
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2013-09-23 04:04:27 +07:00
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* pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
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2010-08-05 19:26:01 +07:00
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* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
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2009-04-19 08:21:22 +07:00
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* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
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*/
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2013-06-21 17:10:46 +07:00
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#ifndef cpu_has_clo_clz
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#define cpu_has_clo_clz cpu_has_mips_r
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#endif
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2009-04-19 08:21:22 +07:00
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2014-08-15 15:56:58 +07:00
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/*
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* MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
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* MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
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* This indicates the availability of WSBH and in case of 64 bit CPUs also
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* DSBH and DSHD.
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*/
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#ifndef cpu_has_wsbh
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#define cpu_has_wsbh cpu_has_mips_r2
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#endif
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2005-05-31 18:49:19 +07:00
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#ifndef cpu_has_dsp
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#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
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#endif
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2012-08-03 22:26:04 +07:00
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#ifndef cpu_has_dsp2
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#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
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#endif
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2005-07-14 14:34:18 +07:00
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#ifndef cpu_has_mipsmt
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2006-06-30 18:32:37 +07:00
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#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
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2005-07-14 14:34:18 +07:00
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#endif
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2007-07-10 23:33:02 +07:00
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#ifndef cpu_has_userlocal
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#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
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#endif
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2005-09-04 05:56:16 +07:00
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#ifdef CONFIG_32BIT
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2005-04-17 05:20:36 +07:00
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# ifndef cpu_has_nofpuex
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# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
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# endif
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# ifndef cpu_has_64bits
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# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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# endif
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# ifndef cpu_has_64bit_zero_reg
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2013-06-21 17:10:46 +07:00
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# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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2005-04-17 05:20:36 +07:00
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# endif
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# ifndef cpu_has_64bit_gp_regs
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# define cpu_has_64bit_gp_regs 0
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# endif
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses 0
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# endif
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2010-02-02 23:52:20 +07:00
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# ifndef cpu_vmbits
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# define cpu_vmbits 31
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# endif
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2005-04-17 05:20:36 +07:00
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#endif
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2005-09-04 05:56:16 +07:00
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#ifdef CONFIG_64BIT
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2005-04-17 05:20:36 +07:00
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# ifndef cpu_has_nofpuex
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# define cpu_has_nofpuex 0
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# endif
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# ifndef cpu_has_64bits
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# define cpu_has_64bits 1
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# endif
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# ifndef cpu_has_64bit_zero_reg
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# define cpu_has_64bit_zero_reg 1
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# endif
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# ifndef cpu_has_64bit_gp_regs
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# define cpu_has_64bit_gp_regs 1
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# endif
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|
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# ifndef cpu_has_64bit_addresses
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|
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# define cpu_has_64bit_addresses 1
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# endif
|
2010-02-02 23:52:20 +07:00
|
|
|
# ifndef cpu_vmbits
|
|
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|
|
# define cpu_vmbits cpu_data[0].vmbits
|
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|
|
# define __NEED_VMBITS_PROBE
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|
|
# endif
|
2005-04-17 05:20:36 +07:00
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|
|
#endif
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|
2006-06-05 23:24:46 +07:00
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|
|
#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
|
|
|
|
|
# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
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|
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|
|
#elif !defined(cpu_has_vint)
|
2005-07-14 14:34:18 +07:00
|
|
|
# define cpu_has_vint 0
|
2006-06-05 23:24:46 +07:00
|
|
|
#endif
|
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|
|
#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
|
|
|
|
|
# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
|
|
|
|
|
#elif !defined(cpu_has_veic)
|
2005-07-14 14:34:18 +07:00
|
|
|
# define cpu_has_veic 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-07-06 19:04:01 +07:00
|
|
|
#ifndef cpu_has_inclusive_pcaches
|
|
|
|
|
#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef cpu_dcache_line_size
|
2007-11-27 23:20:47 +07:00
|
|
|
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
#ifndef cpu_icache_line_size
|
2007-11-27 23:20:47 +07:00
|
|
|
#define cpu_icache_line_size() cpu_data[0].icache.linesz
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
#ifndef cpu_scache_line_size
|
2007-11-27 23:20:47 +07:00
|
|
|
#define cpu_scache_line_size() cpu_data[0].scache.linesz
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
2009-05-14 05:59:55 +07:00
|
|
|
#ifndef cpu_hwrena_impl_bits
|
|
|
|
|
#define cpu_hwrena_impl_bits 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-07-14 03:44:51 +07:00
|
|
|
#ifndef cpu_has_perf_cntr_intr_bit
|
|
|
|
|
#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-02-17 05:42:43 +07:00
|
|
|
#ifndef cpu_has_vz
|
|
|
|
|
#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-01-27 22:23:10 +07:00
|
|
|
#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
|
|
|
|
|
# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
|
|
|
|
|
#elif !defined(cpu_has_msa)
|
|
|
|
|
# define cpu_has_msa 0
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif /* __ASM_CPU_FEATURES_H */
|