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MIPS: Add new option for unique RI/XI exceptions

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MIPSr5 added support for unique exception codes for the Read-Inhibit
and Execute-Inhibit exceptions.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7338/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Leonid Yegoshin 2014-07-15 14:09:55 +01:00 committed by Ralf Baechle
parent f1014d1b79
commit 6ee729aa6c
2 changed files with 4 additions and 0 deletions
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3
arch/mips/include/asm/cpu-features.h
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@ -32,6 +32,9 @@
#ifndef cpu_has_htw
#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
#endif
#ifndef cpu_has_rixiex
#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
#endif
/*
* For the moment we don't consider R6000 and R8000 so we can assume that

1
arch/mips/include/asm/cpu.h
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@ -366,6 +366,7 @@ enum cpu_type_enum {
#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
/*
* CPU ASE encodings