2016-11-01 23:43:03 +07:00
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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2019-04-25 00:48:39 +07:00
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#include "intel_reset.h"
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2016-11-01 23:43:03 +07:00
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#include "i915_drv.h"
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2019-01-25 20:22:28 +07:00
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struct hangcheck {
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u64 acthd;
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2019-05-01 18:45:28 +07:00
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u32 ring;
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2019-05-08 15:06:25 +07:00
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u32 head;
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2019-01-25 20:22:28 +07:00
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enum intel_engine_hangcheck_action action;
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unsigned long action_timestamp;
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int deadlock;
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struct intel_instdone instdone;
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bool wedged:1;
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bool stalled:1;
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};
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2016-11-01 23:43:03 +07:00
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static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
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{
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u32 tmp = current_instdone | *old_instdone;
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bool unchanged;
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unchanged = tmp == *old_instdone;
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*old_instdone |= tmp;
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return unchanged;
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}
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static bool subunits_stuck(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_instdone instdone;
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struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
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bool stuck;
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int slice;
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int subslice;
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2019-03-06 01:03:30 +07:00
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if (engine->id != RCS0)
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2016-11-01 23:43:03 +07:00
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return true;
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intel_engine_get_instdone(engine, &instdone);
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/* There might be unstable subunit states even when
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* actual head is not moving. Filter out the unstable ones by
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* accumulating the undone -> done transitions and only
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* consider those as progress.
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*/
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stuck = instdone_unchanged(instdone.instdone,
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&accu_instdone->instdone);
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stuck &= instdone_unchanged(instdone.slice_common,
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&accu_instdone->slice_common);
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2019-05-29 15:21:50 +07:00
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for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
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2016-11-01 23:43:03 +07:00
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stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
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&accu_instdone->sampler[slice][subslice]);
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stuck &= instdone_unchanged(instdone.row[slice][subslice],
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&accu_instdone->row[slice][subslice]);
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}
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return stuck;
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}
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static enum intel_engine_hangcheck_action
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head_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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if (acthd != engine->hangcheck.acthd) {
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/* Clear subunit states on head movement */
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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2016-11-18 20:09:04 +07:00
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return ENGINE_ACTIVE_HEAD;
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2016-11-01 23:43:03 +07:00
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}
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if (!subunits_stuck(engine))
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2016-11-18 20:09:04 +07:00
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return ENGINE_ACTIVE_SUBUNITS;
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2016-11-01 23:43:03 +07:00
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2016-11-18 20:09:04 +07:00
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return ENGINE_DEAD;
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2016-11-01 23:43:03 +07:00
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}
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static enum intel_engine_hangcheck_action
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engine_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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enum intel_engine_hangcheck_action ha;
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u32 tmp;
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ha = head_stuck(engine, acthd);
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2016-11-18 20:09:04 +07:00
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if (ha != ENGINE_DEAD)
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2016-11-01 23:43:03 +07:00
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return ha;
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drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
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- IS_GEN3(e)
+ IS_GEN(e, 3)
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- IS_GEN4(e)
+ IS_GEN(e, 4)
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- IS_GEN5(e)
+ IS_GEN(e, 5)
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- IS_GEN6(e)
+ IS_GEN(e, 6)
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- IS_GEN7(e)
+ IS_GEN(e, 7)
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- IS_GEN8(e)
+ IS_GEN(e, 8)
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- IS_GEN9(e)
+ IS_GEN(e, 9)
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- IS_GEN10(e)
+ IS_GEN(e, 10)
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- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 01:10:43 +07:00
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if (IS_GEN(dev_priv, 2))
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2016-11-18 20:09:04 +07:00
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return ENGINE_DEAD;
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2016-11-01 23:43:03 +07:00
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/* Is the chip hanging on a WAIT_FOR_EVENT?
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* If so we can simply poke the RB_WAIT bit
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* and break the hang. This should work on
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* all but the second generation chipsets.
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*/
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2019-03-26 04:49:40 +07:00
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tmp = ENGINE_READ(engine, RING_CTL);
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2016-11-01 23:43:03 +07:00
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if (tmp & RING_WAIT) {
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2019-03-06 01:03:30 +07:00
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i915_handle_error(dev_priv, engine->mask, 0,
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2018-03-20 17:04:49 +07:00
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"stuck wait on %s", engine->name);
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2019-03-26 04:49:40 +07:00
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ENGINE_WRITE(engine, RING_CTL, tmp);
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2016-11-18 20:09:04 +07:00
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return ENGINE_WAIT_KICK;
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2016-11-01 23:43:03 +07:00
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}
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2016-11-18 20:09:04 +07:00
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return ENGINE_DEAD;
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2016-11-01 23:43:03 +07:00
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}
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2016-11-16 22:20:29 +07:00
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static void hangcheck_load_sample(struct intel_engine_cs *engine,
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2019-01-25 20:22:28 +07:00
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struct hangcheck *hc)
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2016-11-16 22:20:29 +07:00
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{
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hc->acthd = intel_engine_get_active_head(engine);
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2019-05-01 18:45:28 +07:00
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hc->ring = ENGINE_READ(engine, RING_START);
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2019-05-08 15:06:25 +07:00
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hc->head = ENGINE_READ(engine, RING_HEAD);
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2016-11-16 22:20:29 +07:00
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}
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static void hangcheck_store_sample(struct intel_engine_cs *engine,
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2019-01-25 20:22:28 +07:00
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const struct hangcheck *hc)
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2016-11-16 22:20:29 +07:00
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{
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engine->hangcheck.acthd = hc->acthd;
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2019-05-01 18:45:28 +07:00
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engine->hangcheck.last_ring = hc->ring;
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2019-05-08 15:06:25 +07:00
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engine->hangcheck.last_head = hc->head;
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2016-11-16 22:20:29 +07:00
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}
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static enum intel_engine_hangcheck_action
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hangcheck_get_action(struct intel_engine_cs *engine,
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2019-01-25 20:22:28 +07:00
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const struct hangcheck *hc)
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2016-11-16 22:20:29 +07:00
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{
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2017-07-21 19:32:23 +07:00
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if (intel_engine_is_idle(engine))
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2016-11-18 20:09:04 +07:00
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return ENGINE_IDLE;
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2016-11-16 22:20:29 +07:00
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2019-05-01 18:45:28 +07:00
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if (engine->hangcheck.last_ring != hc->ring)
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return ENGINE_ACTIVE_SEQNO;
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2019-05-08 15:06:25 +07:00
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if (engine->hangcheck.last_head != hc->head)
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2019-05-01 18:45:28 +07:00
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return ENGINE_ACTIVE_SEQNO;
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2016-11-16 22:20:29 +07:00
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return engine_stuck(engine, hc->acthd);
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}
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static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
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2019-01-25 20:22:28 +07:00
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struct hangcheck *hc)
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2016-11-16 22:20:29 +07:00
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{
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2016-11-18 20:09:04 +07:00
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unsigned long timeout = I915_ENGINE_DEAD_TIMEOUT;
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2016-11-16 22:20:29 +07:00
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hc->action = hangcheck_get_action(engine, hc);
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2016-11-18 20:09:04 +07:00
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/* We always increment the progress
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* if the engine is busy and still processing
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* the same request, so that no single request
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* can run indefinitely (such as a chain of
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* batches). The only time we do not increment
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* the hangcheck score on this ring, if this
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* engine is in a legitimate wait for another
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* engine. In that case the waiting engine is a
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* victim and we want to be sure we catch the
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* right culprit. Then every time we do kick
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* the ring, make it as a progress as the seqno
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* advancement might ensure and if not, it
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* will catch the hanging engine.
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*/
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2016-11-16 22:20:29 +07:00
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2016-11-18 20:09:04 +07:00
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switch (hc->action) {
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case ENGINE_IDLE:
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case ENGINE_ACTIVE_SEQNO:
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/* Clear head and subunit states on seqno movement */
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hc->acthd = 0;
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2016-11-16 22:20:29 +07:00
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2016-11-18 20:09:04 +07:00
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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2016-11-16 22:20:29 +07:00
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2016-11-18 20:09:04 +07:00
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/* Intentional fall through */
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case ENGINE_WAIT_KICK:
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case ENGINE_WAIT:
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engine->hangcheck.action_timestamp = jiffies;
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2016-11-16 22:20:29 +07:00
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break;
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2016-11-18 20:09:04 +07:00
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case ENGINE_ACTIVE_HEAD:
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case ENGINE_ACTIVE_SUBUNITS:
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2017-12-14 19:26:13 +07:00
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/*
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* Seqno stuck with still active engine gets leeway,
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2016-11-18 20:09:04 +07:00
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* in hopes that it is just a long shader.
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2016-11-16 22:20:29 +07:00
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*/
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2016-11-18 20:09:04 +07:00
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timeout = I915_SEQNO_DEAD_TIMEOUT;
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break;
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2016-11-16 22:20:29 +07:00
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2016-11-18 20:09:04 +07:00
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case ENGINE_DEAD:
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2016-11-16 22:20:29 +07:00
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break;
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default:
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MISSING_CASE(hc->action);
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}
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2016-11-18 20:09:04 +07:00
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hc->stalled = time_after(jiffies,
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engine->hangcheck.action_timestamp + timeout);
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2018-06-02 17:48:53 +07:00
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hc->wedged = time_after(jiffies,
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engine->hangcheck.action_timestamp +
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I915_ENGINE_WEDGED_TIMEOUT);
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2016-11-16 22:20:29 +07:00
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}
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static void hangcheck_declare_hang(struct drm_i915_private *i915,
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2019-06-07 15:25:54 +07:00
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intel_engine_mask_t hung,
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intel_engine_mask_t stuck)
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2016-11-16 22:20:29 +07:00
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{
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struct intel_engine_cs *engine;
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2019-04-01 23:26:39 +07:00
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intel_engine_mask_t tmp;
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2016-11-16 22:20:29 +07:00
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char msg[80];
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int len;
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/* If some rings hung but others were still busy, only
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* blame the hanging rings in the synopsis.
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*/
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if (stuck != hung)
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hung &= ~stuck;
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len = scnprintf(msg, sizeof(msg),
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2018-03-20 17:04:49 +07:00
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"%s on ", stuck == hung ? "no progress" : "hang");
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2016-11-16 22:20:29 +07:00
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for_each_engine_masked(engine, i915, hung, tmp)
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len += scnprintf(msg + len, sizeof(msg) - len,
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"%s, ", engine->name);
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msg[len-2] = '\0';
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2018-03-20 17:04:49 +07:00
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return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
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2016-11-16 22:20:29 +07:00
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}
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2016-11-01 23:43:03 +07:00
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/*
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* This is called when the chip hasn't reported back with completed
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* batchbuffers in a long time. We keep track per ring seqno progress and
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* if there are no progress, hangcheck score for that ring is increased.
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* Further, acthd is inspected to see if the ring is stuck. On stuck case
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* we kick the ring. If we see no progress on three subsequent calls
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* we assume chip is wedged and try to fix it by resetting the chip.
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*/
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static void i915_hangcheck_elapsed(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv),
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gpu_error.hangcheck_work.work);
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2019-06-07 15:25:54 +07:00
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intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
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2016-11-01 23:43:03 +07:00
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
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|
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intel_wakeref_t wakeref;
|
2016-11-01 23:43:03 +07:00
|
|
|
|
2017-09-20 02:38:44 +07:00
|
|
|
if (!i915_modparams.enable_hangcheck)
|
2016-11-01 23:43:03 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
if (!READ_ONCE(dev_priv->gt.awake))
|
|
|
|
return;
|
|
|
|
|
2019-02-20 21:56:37 +07:00
|
|
|
if (i915_terminally_wedged(dev_priv))
|
2016-11-22 21:41:19 +07:00
|
|
|
return;
|
|
|
|
|
2019-06-14 06:21:54 +07:00
|
|
|
wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
|
drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
|
|
|
if (!wakeref)
|
|
|
|
return;
|
|
|
|
|
2016-11-01 23:43:03 +07:00
|
|
|
/* As enabling the GPU requires fairly extensive mmio access,
|
|
|
|
* periodically arm the mmio checker to see if we are triggering
|
|
|
|
* any invalid access.
|
|
|
|
*/
|
2019-03-26 04:49:34 +07:00
|
|
|
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
|
2016-11-01 23:43:03 +07:00
|
|
|
|
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2019-01-25 20:22:28 +07:00
|
|
|
struct hangcheck hc;
|
2016-11-01 23:43:03 +07:00
|
|
|
|
2019-01-30 03:52:30 +07:00
|
|
|
intel_engine_signal_breadcrumbs(engine);
|
|
|
|
|
2017-12-19 20:09:48 +07:00
|
|
|
hangcheck_load_sample(engine, &hc);
|
|
|
|
hangcheck_accumulate_sample(engine, &hc);
|
|
|
|
hangcheck_store_sample(engine, &hc);
|
2016-11-16 22:20:29 +07:00
|
|
|
|
2019-01-25 20:22:28 +07:00
|
|
|
if (hc.stalled) {
|
2019-03-06 01:03:30 +07:00
|
|
|
hung |= engine->mask;
|
2017-12-19 20:09:48 +07:00
|
|
|
if (hc.action != ENGINE_DEAD)
|
2019-03-06 01:03:30 +07:00
|
|
|
stuck |= engine->mask;
|
2016-11-01 23:43:03 +07:00
|
|
|
}
|
2018-06-02 17:48:53 +07:00
|
|
|
|
2019-01-25 20:22:28 +07:00
|
|
|
if (hc.wedged)
|
2019-03-06 01:03:30 +07:00
|
|
|
wedged |= engine->mask;
|
2018-06-02 17:48:53 +07:00
|
|
|
}
|
|
|
|
|
2019-01-22 05:20:46 +07:00
|
|
|
if (GEM_SHOW_DEBUG() && (hung | stuck)) {
|
|
|
|
struct drm_printer p = drm_debug_printer("hangcheck");
|
|
|
|
|
|
|
|
for_each_engine(engine, dev_priv, id) {
|
|
|
|
if (intel_engine_is_idle(engine))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
intel_engine_dump(engine, &p, "%s\n", engine->name);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-02 17:48:53 +07:00
|
|
|
if (wedged) {
|
|
|
|
dev_err(dev_priv->drm.dev,
|
|
|
|
"GPU recovery timed out,"
|
|
|
|
" cancelling all in-flight rendering.\n");
|
|
|
|
GEM_TRACE_DUMP();
|
|
|
|
i915_gem_set_wedged(dev_priv);
|
2016-11-01 23:43:03 +07:00
|
|
|
}
|
|
|
|
|
2016-11-16 22:20:29 +07:00
|
|
|
if (hung)
|
|
|
|
hangcheck_declare_hang(dev_priv, hung, stuck);
|
2016-11-01 23:43:03 +07:00
|
|
|
|
2019-06-14 06:21:54 +07:00
|
|
|
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
|
drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
|
|
|
|
2016-11-01 23:43:03 +07:00
|
|
|
/* Reset timer in case GPU hangs without another request being added */
|
drm/i915: Always run hangcheck while the GPU is busy
Previously, we relied on only running the hangcheck while somebody was
waiting on the GPU, in order to minimise the amount of time hangcheck
had to run. (If nobody was watching the GPU, nobody would notice if the
GPU wasn't responding -- eventually somebody would care and so kick
hangcheck into action.) However, this falls apart from around commit
4680816be336 ("drm/i915: Wait first for submission, before waiting for
request completion"), as not all waiters declare themselves to hangcheck
and so we could switch off hangcheck and miss GPU hangs even when
waiting under the struct_mutex.
If we enable hangcheck from the first request submission, and let it run
until the GPU is idle again, we forgo all the complexity involved with
only enabling around waiters. We just have to remember to be careful that
we do not declare a GPU hang when idly waiting for the next request to
be come ready, as we will run hangcheck continuously even when the
engines are stalled waiting for external events. This should be true
already as we should only be tracking requests submitted to hardware for
execution as an indicator that the engine is busy.
Fixes: 4680816be336 ("drm/i915: Wait first for submission, before waiting for request completion"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104840
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180129144104.3921-1-chris@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
2018-01-29 21:41:04 +07:00
|
|
|
i915_queue_hangcheck(dev_priv);
|
2016-11-01 23:43:03 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
2018-05-03 05:03:12 +07:00
|
|
|
engine->hangcheck.action_timestamp = jiffies;
|
2016-11-01 23:43:03 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_hangcheck_init(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
|
|
|
|
i915_hangcheck_elapsed);
|
|
|
|
}
|
2017-02-14 00:15:58 +07:00
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
2019-04-25 00:48:39 +07:00
|
|
|
#include "selftest_hangcheck.c"
|
2017-02-14 00:15:58 +07:00
|
|
|
#endif
|