2012-08-23 08:09:34 +07:00
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/*
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* TI EDMA DMA engine driver
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*
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* Copyright 2012 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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2014-07-31 17:12:38 +07:00
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#include <linux/of.h>
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2012-08-23 08:09:34 +07:00
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2013-03-06 23:15:31 +07:00
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#include <linux/platform_data/edma.h>
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2012-08-23 08:09:34 +07:00
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#include "dmaengine.h"
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#include "virt-dma.h"
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/*
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* This will go away when the private EDMA API is folded
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* into this driver and the platform device(s) are
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* instantiated in the arch code. We can only get away
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* with this simplification because DA8XX may not be built
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* in the same kernel image with other DaVinci parts. This
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* avoids having to sprinkle dmaengine driver platform devices
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* and data throughout all the existing board files.
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*/
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#ifdef CONFIG_ARCH_DAVINCI_DA8XX
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#define EDMA_CTLRS 2
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#define EDMA_CHANS 32
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#else
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#define EDMA_CTLRS 1
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#define EDMA_CHANS 64
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#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
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2013-09-24 06:05:15 +07:00
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/*
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* Max of 20 segments per channel to conserve PaRAM slots
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* Also note that MAX_NR_SG should be atleast the no.of periods
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* that are required for ASoC, otherwise DMA prep calls will
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* fail. Today davinci-pcm is the only user of this driver and
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* requires atleast 17 slots, so we setup the default to 20.
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*/
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#define MAX_NR_SG 20
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2012-08-23 08:09:34 +07:00
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#define EDMA_MAX_SLOTS MAX_NR_SG
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#define EDMA_DESCRIPTORS 16
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2014-04-29 02:23:55 +07:00
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struct edma_pset {
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2014-04-29 02:29:57 +07:00
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u32 len;
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dma_addr_t addr;
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2014-04-29 02:23:55 +07:00
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struct edmacc_param param;
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};
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2012-08-23 08:09:34 +07:00
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struct edma_desc {
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struct virt_dma_desc vdesc;
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struct list_head node;
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2014-04-29 02:29:57 +07:00
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enum dma_transfer_direction direction;
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2013-11-01 04:31:23 +07:00
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int cyclic;
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2012-08-23 08:09:34 +07:00
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int absync;
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int pset_nr;
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2014-04-29 03:19:31 +07:00
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struct edma_chan *echan;
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2013-09-03 22:02:46 +07:00
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int processed;
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2014-04-29 03:19:31 +07:00
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/*
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* The following 4 elements are used for residue accounting.
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*
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* - processed_stat: the number of SG elements we have traversed
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* so far to cover accounting. This is updated directly to processed
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* during edma_callback and is always <= processed, because processed
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* refers to the number of pending transfer (programmed to EDMA
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* controller), where as processed_stat tracks number of transfers
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* accounted for so far.
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*
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* - residue: The amount of bytes we have left to transfer for this desc
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*
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* - residue_stat: The residue in bytes of data we have covered
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* so far for accounting. This is updated directly to residue
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* during callbacks to keep it current.
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*
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* - sg_len: Tracks the length of the current intermediate transfer,
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* this is required to update the residue during intermediate transfer
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* completion callback.
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*/
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2014-04-29 02:34:11 +07:00
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int processed_stat;
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u32 sg_len;
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2014-04-29 03:19:31 +07:00
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u32 residue;
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2014-04-29 02:34:11 +07:00
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u32 residue_stat;
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2014-04-29 03:19:31 +07:00
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2014-04-29 02:23:55 +07:00
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struct edma_pset pset[0];
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2012-08-23 08:09:34 +07:00
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};
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struct edma_cc;
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struct edma_chan {
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struct virt_dma_chan vchan;
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struct list_head node;
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struct edma_desc *edesc;
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struct edma_cc *ecc;
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int ch_num;
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bool alloced;
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int slot[EDMA_MAX_SLOTS];
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dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
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int missed;
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2013-01-11 01:41:04 +07:00
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struct dma_slave_config cfg;
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2012-08-23 08:09:34 +07:00
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};
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struct edma_cc {
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int ctlr;
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struct dma_device dma_slave;
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struct edma_chan slave_chans[EDMA_CHANS];
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int num_slave_chans;
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int dummy_slot;
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};
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static inline struct edma_cc *to_edma_cc(struct dma_device *d)
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{
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return container_of(d, struct edma_cc, dma_slave);
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}
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static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
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{
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return container_of(c, struct edma_chan, vchan.chan);
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}
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static inline struct edma_desc
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*to_edma_desc(struct dma_async_tx_descriptor *tx)
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{
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return container_of(tx, struct edma_desc, vdesc.tx);
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}
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static void edma_desc_free(struct virt_dma_desc *vdesc)
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{
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kfree(container_of(vdesc, struct edma_desc, vdesc));
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}
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/* Dispatch a queued descriptor to the controller (caller holds lock) */
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static void edma_execute(struct edma_chan *echan)
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{
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2013-09-03 22:02:46 +07:00
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struct virt_dma_desc *vdesc;
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2012-08-23 08:09:34 +07:00
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struct edma_desc *edesc;
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2013-09-03 22:02:46 +07:00
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struct device *dev = echan->vchan.chan.device->dev;
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int i, j, left, nslots;
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/* If either we processed all psets or we're still not started */
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if (!echan->edesc ||
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echan->edesc->pset_nr == echan->edesc->processed) {
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/* Get next vdesc */
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vdesc = vchan_next_desc(&echan->vchan);
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if (!vdesc) {
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echan->edesc = NULL;
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return;
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}
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list_del(&vdesc->node);
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echan->edesc = to_edma_desc(&vdesc->tx);
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2012-08-23 08:09:34 +07:00
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}
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2013-09-03 22:02:46 +07:00
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edesc = echan->edesc;
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2012-08-23 08:09:34 +07:00
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2013-09-03 22:02:46 +07:00
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/* Find out how many left */
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left = edesc->pset_nr - edesc->processed;
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nslots = min(MAX_NR_SG, left);
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2014-04-29 02:34:11 +07:00
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edesc->sg_len = 0;
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2012-08-23 08:09:34 +07:00
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/* Write descriptor PaRAM set(s) */
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2013-09-03 22:02:46 +07:00
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for (i = 0; i < nslots; i++) {
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j = i + edesc->processed;
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2014-04-29 02:23:55 +07:00
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edma_write_slot(echan->slot[i], &edesc->pset[j].param);
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2014-04-29 02:34:11 +07:00
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edesc->sg_len += edesc->pset[j].len;
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2014-04-14 18:42:02 +07:00
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dev_vdbg(echan->vchan.chan.device->dev,
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2012-08-23 08:09:34 +07:00
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"\n pset[%d]:\n"
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" chnum\t%d\n"
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" slot\t%d\n"
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" opt\t%08x\n"
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" src\t%08x\n"
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" dst\t%08x\n"
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" abcnt\t%08x\n"
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" ccnt\t%08x\n"
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" bidx\t%08x\n"
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" cidx\t%08x\n"
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" lkrld\t%08x\n",
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2013-09-03 22:02:46 +07:00
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j, echan->ch_num, echan->slot[i],
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2014-04-29 02:23:55 +07:00
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edesc->pset[j].param.opt,
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edesc->pset[j].param.src,
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edesc->pset[j].param.dst,
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edesc->pset[j].param.a_b_cnt,
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edesc->pset[j].param.ccnt,
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edesc->pset[j].param.src_dst_bidx,
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edesc->pset[j].param.src_dst_cidx,
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edesc->pset[j].param.link_bcntrld);
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2012-08-23 08:09:34 +07:00
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/* Link to the previous slot if not the last set */
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2013-09-03 22:02:46 +07:00
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if (i != (nslots - 1))
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2012-08-23 08:09:34 +07:00
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edma_link(echan->slot[i], echan->slot[i+1]);
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}
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2013-09-03 22:02:46 +07:00
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edesc->processed += nslots;
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2013-08-30 06:05:44 +07:00
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/*
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* If this is either the last set in a set of SG-list transactions
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* then setup a link to the dummy slot, this results in all future
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* events being absorbed and that's OK because we're done
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*/
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2013-11-01 04:31:23 +07:00
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if (edesc->processed == edesc->pset_nr) {
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if (edesc->cyclic)
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edma_link(echan->slot[nslots-1], echan->slot[1]);
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else
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edma_link(echan->slot[nslots-1],
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echan->ecc->dummy_slot);
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}
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2013-08-30 06:05:44 +07:00
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2013-09-03 22:02:46 +07:00
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if (edesc->processed <= MAX_NR_SG) {
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2014-04-24 14:29:50 +07:00
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dev_dbg(dev, "first transfer starting on channel %d\n",
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echan->ch_num);
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2013-09-03 22:02:46 +07:00
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edma_start(echan->ch_num);
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2014-03-19 12:55:50 +07:00
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} else {
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dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
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echan->ch_num, edesc->processed);
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edma_resume(echan->ch_num);
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2013-09-03 22:02:46 +07:00
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}
|
dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
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/*
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* This happens due to setup times between intermediate transfers
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* in long SG lists which have to be broken up into transfers of
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* MAX_NR_SG
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*/
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if (echan->missed) {
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2014-04-24 14:29:50 +07:00
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dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
|
dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
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edma_clean_channel(echan->ch_num);
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edma_stop(echan->ch_num);
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edma_start(echan->ch_num);
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edma_trigger_channel(echan->ch_num);
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echan->missed = 0;
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}
|
2012-08-23 08:09:34 +07:00
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}
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static int edma_terminate_all(struct edma_chan *echan)
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{
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&echan->vchan.lock, flags);
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/*
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* Stop DMA activity: we assume the callback will not be called
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|
* after edma_dma() returns (even if it does, it will see
|
|
|
|
* echan->edesc is NULL and exit.)
|
|
|
|
*/
|
|
|
|
if (echan->edesc) {
|
2014-07-08 17:46:38 +07:00
|
|
|
int cyclic = echan->edesc->cyclic;
|
2012-08-23 08:09:34 +07:00
|
|
|
echan->edesc = NULL;
|
|
|
|
edma_stop(echan->ch_num);
|
2014-07-08 17:46:38 +07:00
|
|
|
/* Move the cyclic channel back to default queue */
|
|
|
|
if (cyclic)
|
|
|
|
edma_assign_channel_eventq(echan->ch_num,
|
|
|
|
EVENTQ_DEFAULT);
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
vchan_get_all_descriptors(&echan->vchan, &head);
|
|
|
|
spin_unlock_irqrestore(&echan->vchan.lock, flags);
|
|
|
|
vchan_dma_desc_free_list(&echan->vchan, &head);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int edma_slave_config(struct edma_chan *echan,
|
2013-01-11 01:41:04 +07:00
|
|
|
struct dma_slave_config *cfg)
|
2012-08-23 08:09:34 +07:00
|
|
|
{
|
2013-01-11 01:41:04 +07:00
|
|
|
if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
|
|
|
|
cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
|
2012-08-23 08:09:34 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2013-01-11 01:41:04 +07:00
|
|
|
memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-14 18:41:59 +07:00
|
|
|
static int edma_dma_pause(struct edma_chan *echan)
|
|
|
|
{
|
|
|
|
/* Pause/Resume only allowed with cyclic mode */
|
2014-09-30 01:06:45 +07:00
|
|
|
if (!echan->edesc || !echan->edesc->cyclic)
|
2014-04-14 18:41:59 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
edma_pause(echan->ch_num);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int edma_dma_resume(struct edma_chan *echan)
|
|
|
|
{
|
|
|
|
/* Pause/Resume only allowed with cyclic mode */
|
|
|
|
if (!echan->edesc->cyclic)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
edma_resume(echan->ch_num);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct dma_slave_config *config;
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case DMA_TERMINATE_ALL:
|
|
|
|
edma_terminate_all(echan);
|
|
|
|
break;
|
|
|
|
case DMA_SLAVE_CONFIG:
|
|
|
|
config = (struct dma_slave_config *)arg;
|
|
|
|
ret = edma_slave_config(echan, config);
|
|
|
|
break;
|
2014-04-14 18:41:59 +07:00
|
|
|
case DMA_PAUSE:
|
|
|
|
ret = edma_dma_pause(echan);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_RESUME:
|
|
|
|
ret = edma_dma_resume(echan);
|
|
|
|
break;
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
default:
|
|
|
|
ret = -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-09-24 06:05:13 +07:00
|
|
|
/*
|
|
|
|
* A PaRAM set configuration abstraction used by other modes
|
|
|
|
* @chan: Channel who's PaRAM set we're configuring
|
|
|
|
* @pset: PaRAM set to initialize and setup.
|
|
|
|
* @src_addr: Source address of the DMA
|
|
|
|
* @dst_addr: Destination address of the DMA
|
|
|
|
* @burst: In units of dev_width, how much to send
|
|
|
|
* @dev_width: How much is the dev_width
|
|
|
|
* @dma_length: Total length of the DMA transfer
|
|
|
|
* @direction: Direction of the transfer
|
|
|
|
*/
|
2014-04-29 02:23:55 +07:00
|
|
|
static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
|
2013-09-24 06:05:13 +07:00
|
|
|
dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
|
|
|
|
enum dma_slave_buswidth dev_width, unsigned int dma_length,
|
|
|
|
enum dma_transfer_direction direction)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct device *dev = chan->device->dev;
|
2014-04-29 02:23:55 +07:00
|
|
|
struct edmacc_param *param = &epset->param;
|
2013-09-24 06:05:13 +07:00
|
|
|
int acnt, bcnt, ccnt, cidx;
|
|
|
|
int src_bidx, dst_bidx, src_cidx, dst_cidx;
|
|
|
|
int absync;
|
|
|
|
|
|
|
|
acnt = dev_width;
|
2014-04-14 18:41:58 +07:00
|
|
|
|
|
|
|
/* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
|
|
|
|
if (!burst)
|
|
|
|
burst = 1;
|
2013-09-24 06:05:13 +07:00
|
|
|
/*
|
|
|
|
* If the maxburst is equal to the fifo width, use
|
|
|
|
* A-synced transfers. This allows for large contiguous
|
|
|
|
* buffer transfers using only one PaRAM set.
|
|
|
|
*/
|
|
|
|
if (burst == 1) {
|
|
|
|
/*
|
|
|
|
* For the A-sync case, bcnt and ccnt are the remainder
|
|
|
|
* and quotient respectively of the division of:
|
|
|
|
* (dma_length / acnt) by (SZ_64K -1). This is so
|
|
|
|
* that in case bcnt over flows, we have ccnt to use.
|
|
|
|
* Note: In A-sync tranfer only, bcntrld is used, but it
|
|
|
|
* only applies for sg_dma_len(sg) >= SZ_64K.
|
|
|
|
* In this case, the best way adopted is- bccnt for the
|
|
|
|
* first frame will be the remainder below. Then for
|
|
|
|
* every successive frame, bcnt will be SZ_64K-1. This
|
|
|
|
* is assured as bcntrld = 0xffff in end of function.
|
|
|
|
*/
|
|
|
|
absync = false;
|
|
|
|
ccnt = dma_length / acnt / (SZ_64K - 1);
|
|
|
|
bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
|
|
|
|
/*
|
|
|
|
* If bcnt is non-zero, we have a remainder and hence an
|
|
|
|
* extra frame to transfer, so increment ccnt.
|
|
|
|
*/
|
|
|
|
if (bcnt)
|
|
|
|
ccnt++;
|
|
|
|
else
|
|
|
|
bcnt = SZ_64K - 1;
|
|
|
|
cidx = acnt;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* If maxburst is greater than the fifo address_width,
|
|
|
|
* use AB-synced transfers where A count is the fifo
|
|
|
|
* address_width and B count is the maxburst. In this
|
|
|
|
* case, we are limited to transfers of C count frames
|
|
|
|
* of (address_width * maxburst) where C count is limited
|
|
|
|
* to SZ_64K-1. This places an upper bound on the length
|
|
|
|
* of an SG segment that can be handled.
|
|
|
|
*/
|
|
|
|
absync = true;
|
|
|
|
bcnt = burst;
|
|
|
|
ccnt = dma_length / (acnt * bcnt);
|
|
|
|
if (ccnt > (SZ_64K - 1)) {
|
|
|
|
dev_err(dev, "Exceeded max SG segment size\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
cidx = acnt * bcnt;
|
|
|
|
}
|
|
|
|
|
2014-04-29 02:29:57 +07:00
|
|
|
epset->len = dma_length;
|
|
|
|
|
2013-09-24 06:05:13 +07:00
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
|
|
src_bidx = acnt;
|
|
|
|
src_cidx = cidx;
|
|
|
|
dst_bidx = 0;
|
|
|
|
dst_cidx = 0;
|
2014-04-29 02:29:57 +07:00
|
|
|
epset->addr = src_addr;
|
2013-09-24 06:05:13 +07:00
|
|
|
} else if (direction == DMA_DEV_TO_MEM) {
|
|
|
|
src_bidx = 0;
|
|
|
|
src_cidx = 0;
|
|
|
|
dst_bidx = acnt;
|
|
|
|
dst_cidx = cidx;
|
2014-04-29 02:29:57 +07:00
|
|
|
epset->addr = dst_addr;
|
2014-04-19 09:50:33 +07:00
|
|
|
} else if (direction == DMA_MEM_TO_MEM) {
|
|
|
|
src_bidx = acnt;
|
|
|
|
src_cidx = cidx;
|
|
|
|
dst_bidx = acnt;
|
|
|
|
dst_cidx = cidx;
|
2013-09-24 06:05:13 +07:00
|
|
|
} else {
|
|
|
|
dev_err(dev, "%s: direction not implemented yet\n", __func__);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2014-04-29 02:23:55 +07:00
|
|
|
param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
|
2013-09-24 06:05:13 +07:00
|
|
|
/* Configure A or AB synchronized transfers */
|
|
|
|
if (absync)
|
2014-04-29 02:23:55 +07:00
|
|
|
param->opt |= SYNCDIM;
|
2013-09-24 06:05:13 +07:00
|
|
|
|
2014-04-29 02:23:55 +07:00
|
|
|
param->src = src_addr;
|
|
|
|
param->dst = dst_addr;
|
2013-09-24 06:05:13 +07:00
|
|
|
|
2014-04-29 02:23:55 +07:00
|
|
|
param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
|
|
|
|
param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
|
2013-09-24 06:05:13 +07:00
|
|
|
|
2014-04-29 02:23:55 +07:00
|
|
|
param->a_b_cnt = bcnt << 16 | acnt;
|
|
|
|
param->ccnt = ccnt;
|
2013-09-24 06:05:13 +07:00
|
|
|
/*
|
|
|
|
* Only time when (bcntrld) auto reload is required is for
|
|
|
|
* A-sync case, and in this case, a requirement of reload value
|
|
|
|
* of SZ_64K-1 only is assured. 'link' is initially set to NULL
|
|
|
|
* and then later will be populated by edma_execute.
|
|
|
|
*/
|
2014-04-29 02:23:55 +07:00
|
|
|
param->link_bcntrld = 0xffffffff;
|
2013-09-24 06:05:13 +07:00
|
|
|
return absync;
|
|
|
|
}
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
|
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
|
|
|
unsigned long tx_flags, void *context)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct device *dev = chan->device->dev;
|
|
|
|
struct edma_desc *edesc;
|
2013-09-24 06:05:13 +07:00
|
|
|
dma_addr_t src_addr = 0, dst_addr = 0;
|
2013-01-11 01:41:04 +07:00
|
|
|
enum dma_slave_buswidth dev_width;
|
|
|
|
u32 burst;
|
2012-08-23 08:09:34 +07:00
|
|
|
struct scatterlist *sg;
|
2013-09-24 06:05:13 +07:00
|
|
|
int i, nslots, ret;
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
if (unlikely(!echan || !sgl || !sg_len))
|
|
|
|
return NULL;
|
|
|
|
|
2013-01-11 01:41:04 +07:00
|
|
|
if (direction == DMA_DEV_TO_MEM) {
|
2013-09-24 06:05:13 +07:00
|
|
|
src_addr = echan->cfg.src_addr;
|
2013-01-11 01:41:04 +07:00
|
|
|
dev_width = echan->cfg.src_addr_width;
|
|
|
|
burst = echan->cfg.src_maxburst;
|
|
|
|
} else if (direction == DMA_MEM_TO_DEV) {
|
2013-09-24 06:05:13 +07:00
|
|
|
dst_addr = echan->cfg.dst_addr;
|
2013-01-11 01:41:04 +07:00
|
|
|
dev_width = echan->cfg.dst_addr_width;
|
|
|
|
burst = echan->cfg.dst_maxburst;
|
|
|
|
} else {
|
2014-04-14 18:42:05 +07:00
|
|
|
dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
|
2013-01-11 01:41:04 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
|
2012-08-23 08:09:34 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
edesc = kzalloc(sizeof(*edesc) + sg_len *
|
|
|
|
sizeof(edesc->pset[0]), GFP_ATOMIC);
|
|
|
|
if (!edesc) {
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
|
2012-08-23 08:09:34 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
edesc->pset_nr = sg_len;
|
2014-04-29 02:18:45 +07:00
|
|
|
edesc->residue = 0;
|
2014-04-29 02:29:57 +07:00
|
|
|
edesc->direction = direction;
|
2014-04-29 02:34:11 +07:00
|
|
|
edesc->echan = echan;
|
2012-08-23 08:09:34 +07:00
|
|
|
|
2013-08-30 06:05:40 +07:00
|
|
|
/* Allocate a PaRAM slot, if needed */
|
|
|
|
nslots = min_t(unsigned, MAX_NR_SG, sg_len);
|
|
|
|
|
|
|
|
for (i = 0; i < nslots; i++) {
|
2012-08-23 08:09:34 +07:00
|
|
|
if (echan->slot[i] < 0) {
|
|
|
|
echan->slot[i] =
|
|
|
|
edma_alloc_slot(EDMA_CTLR(echan->ch_num),
|
|
|
|
EDMA_SLOT_ANY);
|
|
|
|
if (echan->slot[i] < 0) {
|
2013-10-24 20:14:22 +07:00
|
|
|
kfree(edesc);
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Failed to allocate slot\n",
|
|
|
|
__func__);
|
2012-08-23 08:09:34 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
2013-08-30 06:05:40 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure PaRAM sets for each SG */
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
2013-09-24 06:05:13 +07:00
|
|
|
/* Get address for each SG */
|
|
|
|
if (direction == DMA_DEV_TO_MEM)
|
|
|
|
dst_addr = sg_dma_address(sg);
|
|
|
|
else
|
|
|
|
src_addr = sg_dma_address(sg);
|
2012-08-23 08:09:34 +07:00
|
|
|
|
2013-09-24 06:05:13 +07:00
|
|
|
ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
|
|
|
|
dst_addr, burst, dev_width,
|
|
|
|
sg_dma_len(sg), direction);
|
2013-10-30 14:37:18 +07:00
|
|
|
if (ret < 0) {
|
|
|
|
kfree(edesc);
|
2013-09-24 06:05:13 +07:00
|
|
|
return NULL;
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
2013-09-24 06:05:13 +07:00
|
|
|
edesc->absync = ret;
|
2014-04-29 02:18:45 +07:00
|
|
|
edesc->residue += sg_dma_len(sg);
|
2013-08-30 06:05:40 +07:00
|
|
|
|
|
|
|
/* If this is the last in a current SG set of transactions,
|
|
|
|
enable interrupts so that next set is processed */
|
|
|
|
if (!((i+1) % MAX_NR_SG))
|
2014-04-29 02:23:55 +07:00
|
|
|
edesc->pset[i].param.opt |= TCINTEN;
|
2013-08-30 06:05:40 +07:00
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
/* If this is the last set, enable completion interrupt flag */
|
|
|
|
if (i == sg_len - 1)
|
2014-04-29 02:23:55 +07:00
|
|
|
edesc->pset[i].param.opt |= TCINTEN;
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
2014-04-29 02:34:11 +07:00
|
|
|
edesc->residue_stat = edesc->residue;
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
|
|
|
|
}
|
|
|
|
|
2014-04-19 09:50:33 +07:00
|
|
|
struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
|
|
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
|
|
size_t len, unsigned long tx_flags)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
struct edma_desc *edesc;
|
|
|
|
struct device *dev = chan->device->dev;
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
|
|
|
|
if (unlikely(!echan || !len))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC);
|
|
|
|
if (!edesc) {
|
|
|
|
dev_dbg(dev, "Failed to allocate a descriptor\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
edesc->pset_nr = 1;
|
|
|
|
|
|
|
|
ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
|
|
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM);
|
|
|
|
if (ret < 0)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
edesc->absync = ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable intermediate transfer chaining to re-trigger channel
|
|
|
|
* on completion of every TR, and enable transfer-completion
|
|
|
|
* interrupt on completion of the whole transfer.
|
|
|
|
*/
|
2014-04-29 03:30:32 +07:00
|
|
|
edesc->pset[0].param.opt |= ITCCHEN;
|
|
|
|
edesc->pset[0].param.opt |= TCINTEN;
|
2014-04-19 09:50:33 +07:00
|
|
|
|
|
|
|
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
|
|
|
|
}
|
|
|
|
|
2013-11-01 04:31:23 +07:00
|
|
|
static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
|
|
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
|
|
|
size_t period_len, enum dma_transfer_direction direction,
|
2014-08-01 17:20:10 +07:00
|
|
|
unsigned long tx_flags)
|
2013-11-01 04:31:23 +07:00
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct device *dev = chan->device->dev;
|
|
|
|
struct edma_desc *edesc;
|
|
|
|
dma_addr_t src_addr, dst_addr;
|
|
|
|
enum dma_slave_buswidth dev_width;
|
|
|
|
u32 burst;
|
|
|
|
int i, ret, nslots;
|
|
|
|
|
|
|
|
if (unlikely(!echan || !buf_len || !period_len))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (direction == DMA_DEV_TO_MEM) {
|
|
|
|
src_addr = echan->cfg.src_addr;
|
|
|
|
dst_addr = buf_addr;
|
|
|
|
dev_width = echan->cfg.src_addr_width;
|
|
|
|
burst = echan->cfg.src_maxburst;
|
|
|
|
} else if (direction == DMA_MEM_TO_DEV) {
|
|
|
|
src_addr = buf_addr;
|
|
|
|
dst_addr = echan->cfg.dst_addr;
|
|
|
|
dev_width = echan->cfg.dst_addr_width;
|
|
|
|
burst = echan->cfg.dst_maxburst;
|
|
|
|
} else {
|
2014-04-14 18:42:05 +07:00
|
|
|
dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
|
2013-11-01 04:31:23 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
|
2013-11-01 04:31:23 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(buf_len % period_len)) {
|
|
|
|
dev_err(dev, "Period should be multiple of Buffer length\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
nslots = (buf_len / period_len) + 1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Cyclic DMA users such as audio cannot tolerate delays introduced
|
|
|
|
* by cases where the number of periods is more than the maximum
|
|
|
|
* number of SGs the EDMA driver can handle at a time. For DMA types
|
|
|
|
* such as Slave SGs, such delays are tolerable and synchronized,
|
|
|
|
* but the synchronization is difficult to achieve with Cyclic and
|
|
|
|
* cannot be guaranteed, so we error out early.
|
|
|
|
*/
|
|
|
|
if (nslots > MAX_NR_SG)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
edesc = kzalloc(sizeof(*edesc) + nslots *
|
|
|
|
sizeof(edesc->pset[0]), GFP_ATOMIC);
|
|
|
|
if (!edesc) {
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
|
2013-11-01 04:31:23 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
edesc->cyclic = 1;
|
|
|
|
edesc->pset_nr = nslots;
|
2014-04-29 02:34:11 +07:00
|
|
|
edesc->residue = edesc->residue_stat = buf_len;
|
2014-04-29 02:29:57 +07:00
|
|
|
edesc->direction = direction;
|
2014-04-29 02:34:11 +07:00
|
|
|
edesc->echan = echan;
|
2013-11-01 04:31:23 +07:00
|
|
|
|
2014-04-14 18:42:02 +07:00
|
|
|
dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
|
|
|
|
__func__, echan->ch_num, nslots, period_len, buf_len);
|
2013-11-01 04:31:23 +07:00
|
|
|
|
|
|
|
for (i = 0; i < nslots; i++) {
|
|
|
|
/* Allocate a PaRAM slot, if needed */
|
|
|
|
if (echan->slot[i] < 0) {
|
|
|
|
echan->slot[i] =
|
|
|
|
edma_alloc_slot(EDMA_CTLR(echan->ch_num),
|
|
|
|
EDMA_SLOT_ANY);
|
|
|
|
if (echan->slot[i] < 0) {
|
2013-12-31 02:48:39 +07:00
|
|
|
kfree(edesc);
|
2014-04-14 18:42:03 +07:00
|
|
|
dev_err(dev, "%s: Failed to allocate slot\n",
|
|
|
|
__func__);
|
2013-11-01 04:31:23 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == nslots - 1) {
|
|
|
|
memcpy(&edesc->pset[i], &edesc->pset[0],
|
|
|
|
sizeof(edesc->pset[0]));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
|
|
|
|
dst_addr, burst, dev_width, period_len,
|
|
|
|
direction);
|
2013-12-31 02:48:39 +07:00
|
|
|
if (ret < 0) {
|
|
|
|
kfree(edesc);
|
2013-11-01 04:31:23 +07:00
|
|
|
return NULL;
|
2013-12-31 02:48:39 +07:00
|
|
|
}
|
2012-08-23 08:09:34 +07:00
|
|
|
|
2013-11-01 04:31:23 +07:00
|
|
|
if (direction == DMA_DEV_TO_MEM)
|
|
|
|
dst_addr += period_len;
|
|
|
|
else
|
|
|
|
src_addr += period_len;
|
2012-08-23 08:09:34 +07:00
|
|
|
|
2014-04-14 18:42:02 +07:00
|
|
|
dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
|
|
|
|
dev_vdbg(dev,
|
2013-11-01 04:31:23 +07:00
|
|
|
"\n pset[%d]:\n"
|
|
|
|
" chnum\t%d\n"
|
|
|
|
" slot\t%d\n"
|
|
|
|
" opt\t%08x\n"
|
|
|
|
" src\t%08x\n"
|
|
|
|
" dst\t%08x\n"
|
|
|
|
" abcnt\t%08x\n"
|
|
|
|
" ccnt\t%08x\n"
|
|
|
|
" bidx\t%08x\n"
|
|
|
|
" cidx\t%08x\n"
|
|
|
|
" lkrld\t%08x\n",
|
|
|
|
i, echan->ch_num, echan->slot[i],
|
2014-04-29 02:23:55 +07:00
|
|
|
edesc->pset[i].param.opt,
|
|
|
|
edesc->pset[i].param.src,
|
|
|
|
edesc->pset[i].param.dst,
|
|
|
|
edesc->pset[i].param.a_b_cnt,
|
|
|
|
edesc->pset[i].param.ccnt,
|
|
|
|
edesc->pset[i].param.src_dst_bidx,
|
|
|
|
edesc->pset[i].param.src_dst_cidx,
|
|
|
|
edesc->pset[i].param.link_bcntrld);
|
2013-11-01 04:31:23 +07:00
|
|
|
|
|
|
|
edesc->absync = ret;
|
|
|
|
|
|
|
|
/*
|
2014-07-16 19:29:21 +07:00
|
|
|
* Enable period interrupt only if it is requested
|
2013-11-01 04:31:23 +07:00
|
|
|
*/
|
2014-07-16 19:29:21 +07:00
|
|
|
if (tx_flags & DMA_PREP_INTERRUPT)
|
|
|
|
edesc->pset[i].param.opt |= TCINTEN;
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
2014-07-08 17:46:38 +07:00
|
|
|
/* Place the cyclic channel to highest priority queue */
|
|
|
|
edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = data;
|
|
|
|
struct device *dev = echan->vchan.chan.device->dev;
|
|
|
|
struct edma_desc *edesc;
|
dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
|
|
|
struct edmacc_param p;
|
2012-08-23 08:09:34 +07:00
|
|
|
|
2013-11-01 04:31:23 +07:00
|
|
|
edesc = echan->edesc;
|
|
|
|
|
|
|
|
/* Pause the channel for non-cyclic */
|
|
|
|
if (!edesc || (edesc && !edesc->cyclic))
|
|
|
|
edma_pause(echan->ch_num);
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
switch (ch_status) {
|
2013-10-30 19:52:30 +07:00
|
|
|
case EDMA_DMA_COMPLETE:
|
2014-04-17 12:58:33 +07:00
|
|
|
spin_lock(&echan->vchan.lock);
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
if (edesc) {
|
2013-11-01 04:31:23 +07:00
|
|
|
if (edesc->cyclic) {
|
|
|
|
vchan_cyclic_callback(&edesc->vdesc);
|
|
|
|
} else if (edesc->processed == edesc->pset_nr) {
|
2013-09-03 22:02:46 +07:00
|
|
|
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
|
2014-04-29 02:18:45 +07:00
|
|
|
edesc->residue = 0;
|
2013-09-03 22:02:46 +07:00
|
|
|
edma_stop(echan->ch_num);
|
|
|
|
vchan_cookie_complete(&edesc->vdesc);
|
2013-11-01 04:31:23 +07:00
|
|
|
edma_execute(echan);
|
2013-09-03 22:02:46 +07:00
|
|
|
} else {
|
|
|
|
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
|
2014-04-29 02:34:11 +07:00
|
|
|
|
|
|
|
/* Update statistics for tx_status */
|
|
|
|
edesc->residue -= edesc->sg_len;
|
|
|
|
edesc->residue_stat = edesc->residue;
|
|
|
|
edesc->processed_stat = edesc->processed;
|
|
|
|
|
2013-11-01 04:31:23 +07:00
|
|
|
edma_execute(echan);
|
2013-09-03 22:02:46 +07:00
|
|
|
}
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
2014-04-17 12:58:33 +07:00
|
|
|
spin_unlock(&echan->vchan.lock);
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
break;
|
2013-10-30 19:52:30 +07:00
|
|
|
case EDMA_DMA_CC_ERROR:
|
2014-04-17 12:58:33 +07:00
|
|
|
spin_lock(&echan->vchan.lock);
|
dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
|
|
|
|
|
|
|
edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Issue later based on missed flag which will be sure
|
|
|
|
* to happen as:
|
|
|
|
* (1) we finished transmitting an intermediate slot and
|
|
|
|
* edma_execute is coming up.
|
|
|
|
* (2) or we finished current transfer and issue will
|
|
|
|
* call edma_execute.
|
|
|
|
*
|
|
|
|
* Important note: issuing can be dangerous here and
|
|
|
|
* lead to some nasty recursion when we are in a NULL
|
|
|
|
* slot. So we avoid doing so and set the missed flag.
|
|
|
|
*/
|
|
|
|
if (p.a_b_cnt == 0 && p.ccnt == 0) {
|
|
|
|
dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
|
|
|
|
echan->missed = 1;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The slot is already programmed but the event got
|
|
|
|
* missed, so its safe to issue it here.
|
|
|
|
*/
|
|
|
|
dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
|
|
|
|
edma_clean_channel(echan->ch_num);
|
|
|
|
edma_stop(echan->ch_num);
|
|
|
|
edma_start(echan->ch_num);
|
|
|
|
edma_trigger_channel(echan->ch_num);
|
|
|
|
}
|
|
|
|
|
2014-04-17 12:58:33 +07:00
|
|
|
spin_unlock(&echan->vchan.lock);
|
dma: edma: Find missed events and issue them
In an effort to move to using Scatter gather lists of any size with
EDMA as discussed at [1] instead of placing limitations on the driver,
we work through the limitations of the EDMAC hardware to find missed
events and issue them.
The sequence of events that require this are:
For the scenario where MAX slots for an EDMA channel is 3:
SG1 -> SG2 -> SG3 -> SG4 -> SG5 -> SG6 -> Null
The above SG list will have to be DMA'd in 2 sets:
(1) SG1 -> SG2 -> SG3 -> Null
(2) SG4 -> SG5 -> SG6 -> Null
After (1) is succesfully transferred, the events from the MMC controller
donot stop coming and are missed by the time we have setup the transfer
for (2). So here, we catch the events missed as an error condition and
issue them manually.
In the second part of the patch, we make handle the NULL slot cases:
For crypto IP, we continue to receive events even continuously in
NULL slot, the setup of the next set of SG elements happens after
the error handler executes. This is results in some recursion problems.
Due to this, we continously receive error interrupts when we manually
trigger an event from the error handler.
We fix this, by first detecting if the Channel is currently transferring
from a NULL slot or not, that's where the edma_read_slot in the error
callback from interrupt handler comes in. With this we can determine if
the set up of the next SG list has completed, and we manually trigger
only in this case. If the setup has _not_ completed, we are still in NULL
so we just set a missed flag and allow the manual triggerring to happen
in edma_execute which will be eventually called. This fixes the above
mentioned race conditions seen with the crypto drivers.
[1] http://marc.info/?l=linux-omap&m=137416733628831&w=2
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-30 06:05:43 +07:00
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Alloc channel resources */
|
|
|
|
static int edma_alloc_chan_resources(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct device *dev = chan->device->dev;
|
|
|
|
int ret;
|
|
|
|
int a_ch_num;
|
|
|
|
LIST_HEAD(descs);
|
|
|
|
|
|
|
|
a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
|
|
|
|
chan, EVENTQ_DEFAULT);
|
|
|
|
|
|
|
|
if (a_ch_num < 0) {
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_no_chan;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a_ch_num != echan->ch_num) {
|
|
|
|
dev_err(dev, "failed to allocate requested channel %u:%u\n",
|
|
|
|
EDMA_CTLR(echan->ch_num),
|
|
|
|
EDMA_CHAN_SLOT(echan->ch_num));
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_wrong_chan;
|
|
|
|
}
|
|
|
|
|
|
|
|
echan->alloced = true;
|
|
|
|
echan->slot[0] = echan->ch_num;
|
|
|
|
|
2014-04-24 14:29:50 +07:00
|
|
|
dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
|
2013-12-13 21:06:18 +07:00
|
|
|
EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_wrong_chan:
|
|
|
|
edma_free_channel(a_ch_num);
|
|
|
|
err_no_chan:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Free channel resources */
|
|
|
|
static void edma_free_chan_resources(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct device *dev = chan->device->dev;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Terminate transfers */
|
|
|
|
edma_stop(echan->ch_num);
|
|
|
|
|
|
|
|
vchan_free_chan_resources(&echan->vchan);
|
|
|
|
|
|
|
|
/* Free EDMA PaRAM slots */
|
|
|
|
for (i = 1; i < EDMA_MAX_SLOTS; i++) {
|
|
|
|
if (echan->slot[i] >= 0) {
|
|
|
|
edma_free_slot(echan->slot[i]);
|
|
|
|
echan->slot[i] = -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Free EDMA channel */
|
|
|
|
if (echan->alloced) {
|
|
|
|
edma_free_channel(echan->ch_num);
|
|
|
|
echan->alloced = false;
|
|
|
|
}
|
|
|
|
|
2013-12-13 21:06:18 +07:00
|
|
|
dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Send pending descriptor to hardware */
|
|
|
|
static void edma_issue_pending(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&echan->vchan.lock, flags);
|
|
|
|
if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
|
|
|
|
edma_execute(echan);
|
|
|
|
spin_unlock_irqrestore(&echan->vchan.lock, flags);
|
|
|
|
}
|
|
|
|
|
2014-04-29 02:34:11 +07:00
|
|
|
static u32 edma_residue(struct edma_desc *edesc)
|
|
|
|
{
|
|
|
|
bool dst = edesc->direction == DMA_DEV_TO_MEM;
|
|
|
|
struct edma_pset *pset = edesc->pset;
|
|
|
|
dma_addr_t done, pos;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We always read the dst/src position from the first RamPar
|
|
|
|
* pset. That's the one which is active now.
|
|
|
|
*/
|
|
|
|
pos = edma_get_position(edesc->echan->slot[0], dst);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Cyclic is simple. Just subtract pset[0].addr from pos.
|
|
|
|
*
|
|
|
|
* We never update edesc->residue in the cyclic case, so we
|
|
|
|
* can tell the remaining room to the end of the circular
|
|
|
|
* buffer.
|
|
|
|
*/
|
|
|
|
if (edesc->cyclic) {
|
|
|
|
done = pos - pset->addr;
|
|
|
|
edesc->residue_stat = edesc->residue - done;
|
|
|
|
return edesc->residue_stat;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For SG operation we catch up with the last processed
|
|
|
|
* status.
|
|
|
|
*/
|
|
|
|
pset += edesc->processed_stat;
|
|
|
|
|
|
|
|
for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
|
|
|
|
/*
|
|
|
|
* If we are inside this pset address range, we know
|
|
|
|
* this is the active one. Get the current delta and
|
|
|
|
* stop walking the psets.
|
|
|
|
*/
|
|
|
|
if (pos >= pset->addr && pos < pset->addr + pset->len)
|
|
|
|
return edesc->residue_stat - (pos - pset->addr);
|
|
|
|
|
|
|
|
/* Otherwise mark it done and update residue_stat. */
|
|
|
|
edesc->processed_stat++;
|
|
|
|
edesc->residue_stat -= pset->len;
|
|
|
|
}
|
|
|
|
return edesc->residue_stat;
|
|
|
|
}
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
/* Check request completion status */
|
|
|
|
static enum dma_status edma_tx_status(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie,
|
|
|
|
struct dma_tx_state *txstate)
|
|
|
|
{
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
struct virt_dma_desc *vdesc;
|
|
|
|
enum dma_status ret;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
ret = dma_cookie_status(chan, cookie, txstate);
|
2013-10-16 15:12:15 +07:00
|
|
|
if (ret == DMA_COMPLETE || !txstate)
|
2012-08-23 08:09:34 +07:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&echan->vchan.lock, flags);
|
2014-04-29 02:19:51 +07:00
|
|
|
if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
|
2014-04-29 02:34:11 +07:00
|
|
|
txstate->residue = edma_residue(echan->edesc);
|
2014-04-29 02:19:51 +07:00
|
|
|
else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
|
|
|
|
txstate->residue = to_edma_desc(&vdesc->tx)->residue;
|
2012-08-23 08:09:34 +07:00
|
|
|
spin_unlock_irqrestore(&echan->vchan.lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init edma_chan_init(struct edma_cc *ecc,
|
|
|
|
struct dma_device *dma,
|
|
|
|
struct edma_chan *echans)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < EDMA_CHANS; i++) {
|
|
|
|
struct edma_chan *echan = &echans[i];
|
|
|
|
echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
|
|
|
|
echan->ecc = ecc;
|
|
|
|
echan->vchan.desc_free = edma_desc_free;
|
|
|
|
|
|
|
|
vchan_init(&echan->vchan, dma);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&echan->node);
|
|
|
|
for (j = 0; j < EDMA_MAX_SLOTS; j++)
|
|
|
|
echan->slot[j] = -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-14 18:42:01 +07:00
|
|
|
#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
2014-07-03 11:51:56 +07:00
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
|
2014-04-14 18:42:01 +07:00
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
|
|
|
|
|
|
|
|
static int edma_dma_device_slave_caps(struct dma_chan *dchan,
|
|
|
|
struct dma_slave_caps *caps)
|
|
|
|
{
|
|
|
|
caps->src_addr_widths = EDMA_DMA_BUSWIDTHS;
|
|
|
|
caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS;
|
|
|
|
caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
|
|
caps->cmd_pause = true;
|
|
|
|
caps->cmd_terminate = true;
|
2014-07-16 19:29:20 +07:00
|
|
|
caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
2014-04-14 18:42:01 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
dma->device_prep_slave_sg = edma_prep_slave_sg;
|
2013-11-01 04:31:23 +07:00
|
|
|
dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
|
2014-04-19 09:50:33 +07:00
|
|
|
dma->device_prep_dma_memcpy = edma_prep_dma_memcpy;
|
2012-08-23 08:09:34 +07:00
|
|
|
dma->device_alloc_chan_resources = edma_alloc_chan_resources;
|
|
|
|
dma->device_free_chan_resources = edma_free_chan_resources;
|
|
|
|
dma->device_issue_pending = edma_issue_pending;
|
|
|
|
dma->device_tx_status = edma_tx_status;
|
|
|
|
dma->device_control = edma_control;
|
2014-04-14 18:42:01 +07:00
|
|
|
dma->device_slave_caps = edma_dma_device_slave_caps;
|
2012-08-23 08:09:34 +07:00
|
|
|
dma->dev = dev;
|
|
|
|
|
2014-04-19 09:50:33 +07:00
|
|
|
/*
|
|
|
|
* code using dma memcpy must make sure alignment of
|
|
|
|
* length is at dma->copy_align boundary.
|
|
|
|
*/
|
|
|
|
dma->copy_align = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
INIT_LIST_HEAD(&dma->channels);
|
|
|
|
}
|
|
|
|
|
2012-11-20 01:22:55 +07:00
|
|
|
static int edma_probe(struct platform_device *pdev)
|
2012-08-23 08:09:34 +07:00
|
|
|
{
|
|
|
|
struct edma_cc *ecc;
|
|
|
|
int ret;
|
|
|
|
|
2013-06-27 19:45:16 +07:00
|
|
|
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-08-23 08:09:34 +07:00
|
|
|
ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
|
|
|
|
if (!ecc) {
|
|
|
|
dev_err(&pdev->dev, "Can't allocate controller\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
ecc->ctlr = pdev->id;
|
|
|
|
ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
|
|
|
|
if (ecc->dummy_slot < 0) {
|
|
|
|
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
|
2014-07-31 17:12:37 +07:00
|
|
|
return ecc->dummy_slot;
|
2012-08-23 08:09:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
dma_cap_zero(ecc->dma_slave.cap_mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
|
2014-04-14 18:42:00 +07:00
|
|
|
dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
|
2014-04-19 09:50:33 +07:00
|
|
|
dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
|
2012-08-23 08:09:34 +07:00
|
|
|
|
|
|
|
edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
|
|
|
|
|
|
|
|
edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
|
|
|
|
|
|
|
|
ret = dma_async_device_register(&ecc->dma_slave);
|
|
|
|
if (ret)
|
|
|
|
goto err_reg1;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, ecc);
|
|
|
|
|
|
|
|
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_reg1:
|
|
|
|
edma_free_slot(ecc->dummy_slot);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-22 06:09:59 +07:00
|
|
|
static int edma_remove(struct platform_device *pdev)
|
2012-08-23 08:09:34 +07:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct edma_cc *ecc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
dma_async_device_unregister(&ecc->dma_slave);
|
|
|
|
edma_free_slot(ecc->dummy_slot);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver edma_driver = {
|
|
|
|
.probe = edma_probe,
|
2012-11-20 01:20:04 +07:00
|
|
|
.remove = edma_remove,
|
2012-08-23 08:09:34 +07:00
|
|
|
.driver = {
|
|
|
|
.name = "edma-dma-engine",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
bool edma_filter_fn(struct dma_chan *chan, void *param)
|
|
|
|
{
|
|
|
|
if (chan->device->dev->driver == &edma_driver.driver) {
|
|
|
|
struct edma_chan *echan = to_edma_chan(chan);
|
|
|
|
unsigned ch_req = *(unsigned *)param;
|
|
|
|
return ch_req == echan->ch_num;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(edma_filter_fn);
|
|
|
|
|
|
|
|
static struct platform_device *pdev0, *pdev1;
|
|
|
|
|
|
|
|
static const struct platform_device_info edma_dev_info0 = {
|
|
|
|
.name = "edma-dma-engine",
|
|
|
|
.id = 0,
|
2013-06-27 19:45:16 +07:00
|
|
|
.dma_mask = DMA_BIT_MASK(32),
|
2012-08-23 08:09:34 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct platform_device_info edma_dev_info1 = {
|
|
|
|
.name = "edma-dma-engine",
|
|
|
|
.id = 1,
|
2013-06-27 19:45:16 +07:00
|
|
|
.dma_mask = DMA_BIT_MASK(32),
|
2012-08-23 08:09:34 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static int edma_init(void)
|
|
|
|
{
|
|
|
|
int ret = platform_driver_register(&edma_driver);
|
|
|
|
|
|
|
|
if (ret == 0) {
|
|
|
|
pdev0 = platform_device_register_full(&edma_dev_info0);
|
|
|
|
if (IS_ERR(pdev0)) {
|
|
|
|
platform_driver_unregister(&edma_driver);
|
|
|
|
ret = PTR_ERR(pdev0);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-31 17:12:38 +07:00
|
|
|
if (!of_have_populated_dt() && EDMA_CTLRS == 2) {
|
2012-08-23 08:09:34 +07:00
|
|
|
pdev1 = platform_device_register_full(&edma_dev_info1);
|
|
|
|
if (IS_ERR(pdev1)) {
|
|
|
|
platform_driver_unregister(&edma_driver);
|
|
|
|
platform_device_unregister(pdev0);
|
|
|
|
ret = PTR_ERR(pdev1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
subsys_initcall(edma_init);
|
|
|
|
|
|
|
|
static void __exit edma_exit(void)
|
|
|
|
{
|
|
|
|
platform_device_unregister(pdev0);
|
|
|
|
if (pdev1)
|
|
|
|
platform_device_unregister(pdev1);
|
|
|
|
platform_driver_unregister(&edma_driver);
|
|
|
|
}
|
|
|
|
module_exit(edma_exit);
|
|
|
|
|
2013-09-04 21:32:50 +07:00
|
|
|
MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
|
2012-08-23 08:09:34 +07:00
|
|
|
MODULE_DESCRIPTION("TI EDMA DMA engine driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|