2014-02-19 01:15:46 +07:00
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Brad Volkin <bradley.d.volkin@intel.com>
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*
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*/
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#include "i915_drv.h"
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/**
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2014-04-25 21:59:00 +07:00
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* DOC: batch buffer command parser
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2014-02-19 01:15:46 +07:00
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*
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* Motivation:
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* Certain OpenGL features (e.g. transform feedback, performance monitoring)
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* require userspace code to submit batches containing commands such as
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* MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
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* generations of the hardware will noop these commands in "unsecure" batches
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* (which includes all userspace batches submitted via i915) even though the
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* commands may be safe and represent the intended programming model of the
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* device.
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*
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* The software command parser is similar in operation to the command parsing
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* done in hardware for unsecure batches. However, the software parser allows
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* some operations that would be noop'd by hardware, if the parser determines
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* the operation is safe, and submits the batch as "secure" to prevent hardware
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* parsing.
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*
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* Threats:
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* At a high level, the hardware (and software) checks attempt to prevent
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* granting userspace undue privileges. There are three categories of privilege.
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*
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* First, commands which are explicitly defined as privileged or which should
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* only be used by the kernel driver. The parser generally rejects such
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* commands, though it may allow some from the drm master process.
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*
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* Second, commands which access registers. To support correct/enhanced
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* userspace functionality, particularly certain OpenGL extensions, the parser
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* provides a whitelist of registers which userspace may safely access (for both
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* normal and drm master processes).
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*
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* Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
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* The parser always rejects such commands.
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*
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* The majority of the problematic commands fall in the MI_* range, with only a
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2016-07-27 15:07:26 +07:00
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* few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
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2014-02-19 01:15:46 +07:00
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*
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* Implementation:
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2016-07-27 15:07:26 +07:00
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* Each engine maintains tables of commands and registers which the parser
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* uses in scanning batch buffers submitted to that engine.
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2014-02-19 01:15:46 +07:00
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*
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* Since the set of commands that the parser must check for is significantly
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* smaller than the number of commands supported, the parser tables contain only
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* those commands required by the parser. This generally works because command
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* opcode ranges have standard command length encodings. So for commands that
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* the parser does not need to check, it can easily skip them. This is
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2016-07-27 15:07:26 +07:00
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* implemented via a per-engine length decoding vfunc.
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2014-02-19 01:15:46 +07:00
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*
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* Unfortunately, there are a number of commands that do not follow the standard
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* length encoding for their opcode range, primarily amongst the MI_* commands.
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* To handle this, the parser provides a way to define explicit "skip" entries
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2016-07-27 15:07:26 +07:00
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* in the per-engine command tables.
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2014-02-19 01:15:46 +07:00
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*
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* Other command table entries map fairly directly to high level categories
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* mentioned above: rejected, master-only, register whitelist. The parser
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* implements a number of checks, including the privileged memory checks, via a
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* general bitmasking mechanism.
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*/
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2016-11-24 06:02:27 +07:00
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/*
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* A command that requires special handling by the command parser.
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*/
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struct drm_i915_cmd_descriptor {
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/*
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* Flags describing how the command parser processes the command.
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*
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* CMD_DESC_FIXED: The command has a fixed length if this is set,
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* a length mask if not set
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* CMD_DESC_SKIP: The command is allowed but does not follow the
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* standard length encoding for the opcode range in
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* which it falls
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* CMD_DESC_REJECT: The command is never allowed
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* CMD_DESC_REGISTER: The command should be checked against the
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* register whitelist for the appropriate ring
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* CMD_DESC_MASTER: The command is allowed if the submitting process
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* is the DRM master
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*/
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u32 flags;
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#define CMD_DESC_FIXED (1<<0)
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#define CMD_DESC_SKIP (1<<1)
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#define CMD_DESC_REJECT (1<<2)
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#define CMD_DESC_REGISTER (1<<3)
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#define CMD_DESC_BITMASK (1<<4)
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#define CMD_DESC_MASTER (1<<5)
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/*
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* The command's unique identification bits and the bitmask to get them.
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* This isn't strictly the opcode field as defined in the spec and may
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* also include type, subtype, and/or subop fields.
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*/
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struct {
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u32 value;
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u32 mask;
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} cmd;
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/*
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* The command's length. The command is either fixed length (i.e. does
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* not include a length field) or has a length field mask. The flag
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* CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
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* a length mask. All command entries in a command table must include
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* length information.
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*/
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union {
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u32 fixed;
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u32 mask;
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} length;
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/*
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* Describes where to find a register address in the command to check
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* against the ring's register whitelist. Only valid if flags has the
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* CMD_DESC_REGISTER bit set.
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*
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* A non-zero step value implies that the command may access multiple
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* registers in sequence (e.g. LRI), in that case step gives the
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* distance in dwords between individual offset fields.
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*/
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struct {
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u32 offset;
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u32 mask;
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u32 step;
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} reg;
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#define MAX_CMD_DESC_BITMASKS 3
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/*
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* Describes command checks where a particular dword is masked and
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* compared against an expected value. If the command does not match
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* the expected value, the parser rejects it. Only valid if flags has
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* the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
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* are valid.
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*
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* If the check specifies a non-zero condition_mask then the parser
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* only performs the check when the bits specified by condition_mask
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* are non-zero.
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*/
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struct {
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u32 offset;
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u32 mask;
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u32 expected;
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u32 condition_offset;
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u32 condition_mask;
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} bits[MAX_CMD_DESC_BITMASKS];
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};
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/*
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* A table of commands requiring special handling by the command parser.
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*
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* Each engine has an array of tables. Each table consists of an array of
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* command descriptors, which must be sorted with command opcodes in
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* ascending order.
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*/
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struct drm_i915_cmd_table {
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const struct drm_i915_cmd_descriptor *table;
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int count;
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};
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2016-08-18 23:17:14 +07:00
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#define STD_MI_OPCODE_SHIFT (32 - 9)
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#define STD_3D_OPCODE_SHIFT (32 - 16)
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#define STD_2D_OPCODE_SHIFT (32 - 10)
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#define STD_MFX_OPCODE_SHIFT (32 - 16)
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2016-08-18 23:17:15 +07:00
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#define MIN_OPCODE_SHIFT 16
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2014-02-19 01:15:47 +07:00
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#define CMD(op, opm, f, lm, fl, ...) \
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{ \
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.flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
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2016-08-18 23:17:14 +07:00
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.cmd = { (op), ~0u << (opm) }, \
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2014-02-19 01:15:47 +07:00
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.length = { (lm) }, \
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__VA_ARGS__ \
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}
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/* Convenience macros to compress the tables */
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2016-08-18 23:17:14 +07:00
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#define SMI STD_MI_OPCODE_SHIFT
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#define S3D STD_3D_OPCODE_SHIFT
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#define S2D STD_2D_OPCODE_SHIFT
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#define SMFX STD_MFX_OPCODE_SHIFT
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2014-02-19 01:15:47 +07:00
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#define F true
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#define S CMD_DESC_SKIP
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#define R CMD_DESC_REJECT
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#define W CMD_DESC_REGISTER
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#define B CMD_DESC_BITMASK
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#define M CMD_DESC_MASTER
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/* Command Mask Fixed Len Action
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---------------------------------------------------------- */
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static const struct drm_i915_cmd_descriptor common_cmds[] = {
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CMD( MI_NOOP, SMI, F, 1, S ),
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2014-02-19 01:15:53 +07:00
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CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
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2014-02-19 01:15:49 +07:00
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CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
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2014-02-19 01:15:47 +07:00
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CMD( MI_ARB_CHECK, SMI, F, 1, S ),
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CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
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CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
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2014-02-19 01:15:48 +07:00
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CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
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CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
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2014-02-19 01:15:52 +07:00
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CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
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2015-05-29 20:44:13 +07:00
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.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
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2015-09-02 18:29:40 +07:00
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CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
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2014-02-19 01:15:54 +07:00
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.reg = { .offset = 1, .mask = 0x007FFFFC },
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.bits = {{
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.offset = 0,
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.mask = MI_GLOBAL_GTT,
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.expected = 0,
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}}, ),
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2015-09-02 18:29:40 +07:00
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CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
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2014-02-19 01:15:54 +07:00
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.reg = { .offset = 1, .mask = 0x007FFFFC },
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.bits = {{
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.offset = 0,
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.mask = MI_GLOBAL_GTT,
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.expected = 0,
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}}, ),
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2014-10-17 02:24:42 +07:00
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/*
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* MI_BATCH_BUFFER_START requires some special handling. It's not
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* really a 'skip' action but it doesn't seem like it's worth adding
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* a new action. See i915_parse_cmds().
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*/
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2014-02-19 01:15:47 +07:00
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CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
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};
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static const struct drm_i915_cmd_descriptor render_cmds[] = {
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CMD( MI_FLUSH, SMI, F, 1, S ),
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2014-02-19 01:15:48 +07:00
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CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
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2014-02-19 01:15:47 +07:00
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CMD( MI_PREDICATE, SMI, F, 1, S ),
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CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
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2014-11-22 00:35:36 +07:00
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CMD( MI_SET_APPID, SMI, F, 1, S ),
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2015-07-29 15:29:58 +07:00
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CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
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2014-02-19 01:15:48 +07:00
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CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
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2014-02-19 01:15:47 +07:00
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CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
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2014-02-19 01:15:54 +07:00
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CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
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.bits = {{
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.offset = 0,
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.mask = MI_GLOBAL_GTT,
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.expected = 0,
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}}, ),
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2014-02-19 01:15:48 +07:00
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CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
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2014-02-19 01:15:54 +07:00
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CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
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.bits = {{
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.offset = 0,
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.mask = MI_GLOBAL_GTT,
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.expected = 0,
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}}, ),
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CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
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.bits = {{
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.offset = 1,
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.mask = MI_REPORT_PERF_COUNT_GGTT,
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.expected = 0,
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}}, ),
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CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
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.bits = {{
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.offset = 0,
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.mask = MI_GLOBAL_GTT,
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.expected = 0,
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}}, ),
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2014-02-19 01:15:47 +07:00
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CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
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CMD( PIPELINE_SELECT, S3D, F, 1, S ),
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2014-02-19 01:15:52 +07:00
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CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
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.bits = {{
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.offset = 2,
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.mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
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.expected = 0,
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}}, ),
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2014-02-19 01:15:47 +07:00
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CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
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CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
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CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
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2014-02-19 01:15:52 +07:00
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CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
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.bits = {{
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.offset = 1,
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2014-02-19 01:15:53 +07:00
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.mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
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2014-02-19 01:15:52 +07:00
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.expected = 0,
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2014-02-19 01:15:54 +07:00
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},
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{
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.offset = 1,
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2014-02-19 01:15:55 +07:00
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.mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_STORE_DATA_INDEX),
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2014-02-19 01:15:54 +07:00
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.expected = 0,
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.condition_offset = 1,
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.condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
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2014-02-19 01:15:52 +07:00
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}}, ),
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2014-02-19 01:15:47 +07:00
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};
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static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
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CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
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CMD( MI_RS_CONTROL, SMI, F, 1, S ),
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|
|
CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
|
2014-11-22 00:35:36 +07:00
|
|
|
CMD( MI_SET_APPID, SMI, F, 1, S ),
|
2014-02-19 01:15:47 +07:00
|
|
|
CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
|
2014-02-19 01:15:49 +07:00
|
|
|
CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
|
2016-05-06 14:50:14 +07:00
|
|
|
CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
|
|
|
|
.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
|
2014-02-19 01:15:47 +07:00
|
|
|
CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
|
|
|
|
CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
|
|
|
|
CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
|
|
|
|
|
|
|
|
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
|
|
|
|
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_descriptor video_cmds[] = {
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
|
2014-11-22 00:35:36 +07:00
|
|
|
CMD( MI_SET_APPID, SMI, F, 1, S ),
|
2014-02-19 01:15:54 +07:00
|
|
|
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_GLOBAL_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
}}, ),
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
|
2014-02-19 01:15:53 +07:00
|
|
|
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_NOTIFY,
|
|
|
|
.expected = 0,
|
2014-02-19 01:15:54 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 1,
|
|
|
|
.mask = MI_FLUSH_DW_USE_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:55 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_STORE_INDEX,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:54 +07:00
|
|
|
}}, ),
|
|
|
|
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_GLOBAL_GTT,
|
|
|
|
.expected = 0,
|
2014-02-19 01:15:53 +07:00
|
|
|
}}, ),
|
2014-02-19 01:15:47 +07:00
|
|
|
/*
|
|
|
|
* MFX_WAIT doesn't fit the way we handle length for most commands.
|
|
|
|
* It has a length field but it uses a non-standard length bias.
|
|
|
|
* It is always 1 dword though, so just treat it as fixed length.
|
|
|
|
*/
|
|
|
|
CMD( MFX_WAIT, SMFX, F, 1, S ),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
|
2014-11-22 00:35:36 +07:00
|
|
|
CMD( MI_SET_APPID, SMI, F, 1, S ),
|
2014-02-19 01:15:54 +07:00
|
|
|
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_GLOBAL_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
}}, ),
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
|
2014-02-19 01:15:53 +07:00
|
|
|
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_NOTIFY,
|
|
|
|
.expected = 0,
|
2014-02-19 01:15:54 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 1,
|
|
|
|
.mask = MI_FLUSH_DW_USE_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:55 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_STORE_INDEX,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:54 +07:00
|
|
|
}}, ),
|
|
|
|
CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_GLOBAL_GTT,
|
|
|
|
.expected = 0,
|
2014-02-19 01:15:53 +07:00
|
|
|
}}, ),
|
2014-02-19 01:15:47 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_descriptor blt_cmds[] = {
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
|
2014-02-19 01:15:54 +07:00
|
|
|
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_GLOBAL_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
}}, ),
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
|
2014-02-19 01:15:53 +07:00
|
|
|
CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
|
|
|
|
.bits = {{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_NOTIFY,
|
|
|
|
.expected = 0,
|
2014-02-19 01:15:54 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 1,
|
|
|
|
.mask = MI_FLUSH_DW_USE_GTT,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:55 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.offset = 0,
|
|
|
|
.mask = MI_FLUSH_DW_STORE_INDEX,
|
|
|
|
.expected = 0,
|
|
|
|
.condition_offset = 0,
|
|
|
|
.condition_mask = MI_FLUSH_DW_OP_MASK,
|
2014-02-19 01:15:53 +07:00
|
|
|
}}, ),
|
2014-02-19 01:15:47 +07:00
|
|
|
CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
|
|
|
|
CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
|
|
|
|
};
|
|
|
|
|
2014-02-19 01:15:48 +07:00
|
|
|
static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
|
2014-02-19 01:15:49 +07:00
|
|
|
CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
|
2014-02-19 01:15:48 +07:00
|
|
|
CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
|
|
|
|
};
|
|
|
|
|
2016-08-18 23:17:15 +07:00
|
|
|
static const struct drm_i915_cmd_descriptor noop_desc =
|
|
|
|
CMD(MI_NOOP, SMI, F, 1, S);
|
|
|
|
|
2014-02-19 01:15:47 +07:00
|
|
|
#undef CMD
|
|
|
|
#undef SMI
|
|
|
|
#undef S3D
|
|
|
|
#undef S2D
|
|
|
|
#undef SMFX
|
|
|
|
#undef F
|
|
|
|
#undef S
|
|
|
|
#undef R
|
|
|
|
#undef W
|
|
|
|
#undef B
|
|
|
|
#undef M
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_table gen7_render_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ render_cmds, ARRAY_SIZE(render_cmds) },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ render_cmds, ARRAY_SIZE(render_cmds) },
|
|
|
|
{ hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_table gen7_video_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ video_cmds, ARRAY_SIZE(video_cmds) },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ vecs_cmds, ARRAY_SIZE(vecs_cmds) },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
|
|
|
|
};
|
|
|
|
|
2014-02-19 01:15:48 +07:00
|
|
|
static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
|
|
|
|
{ common_cmds, ARRAY_SIZE(common_cmds) },
|
|
|
|
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
|
|
|
|
{ hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
|
|
|
|
};
|
|
|
|
|
2014-02-19 01:15:50 +07:00
|
|
|
/*
|
|
|
|
* Register whitelists, sorted by increasing register offset.
|
2015-05-29 20:44:14 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* An individual whitelist entry granting access to register addr. If
|
|
|
|
* mask is non-zero the argument of immediate register writes will be
|
|
|
|
* AND-ed with mask, and the command will be rejected if the result
|
|
|
|
* doesn't match value.
|
|
|
|
*
|
|
|
|
* Registers with non-zero mask are only allowed to be written using
|
|
|
|
* LRI.
|
|
|
|
*/
|
|
|
|
struct drm_i915_reg_descriptor {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t addr;
|
2015-05-29 20:44:14 +07:00
|
|
|
u32 mask;
|
|
|
|
u32 value;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Convenience macro for adding 32-bit registers. */
|
2015-11-07 02:44:40 +07:00
|
|
|
#define REG32(_reg, ...) \
|
|
|
|
{ .addr = (_reg), __VA_ARGS__ }
|
2015-05-29 20:44:14 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Convenience macro for adding 64-bit registers.
|
2014-02-19 01:15:50 +07:00
|
|
|
*
|
|
|
|
* Some registers that userspace accesses are 64 bits. The register
|
|
|
|
* access commands only allow 32-bit accesses. Hence, we have to include
|
|
|
|
* entries for both halves of the 64-bit registers.
|
|
|
|
*/
|
2015-11-07 02:44:40 +07:00
|
|
|
#define REG64(_reg) \
|
|
|
|
{ .addr = _reg }, \
|
|
|
|
{ .addr = _reg ## _UDW }
|
|
|
|
|
|
|
|
#define REG64_IDX(_reg, idx) \
|
|
|
|
{ .addr = _reg(idx) }, \
|
|
|
|
{ .addr = _reg ## _UDW(idx) }
|
2014-02-19 01:15:50 +07:00
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
|
2014-12-12 04:28:09 +07:00
|
|
|
REG64(GPGPU_THREADS_DISPATCHED),
|
2014-02-19 01:15:50 +07:00
|
|
|
REG64(HS_INVOCATION_COUNT),
|
|
|
|
REG64(DS_INVOCATION_COUNT),
|
|
|
|
REG64(IA_VERTICES_COUNT),
|
|
|
|
REG64(IA_PRIMITIVES_COUNT),
|
|
|
|
REG64(VS_INVOCATION_COUNT),
|
|
|
|
REG64(GS_INVOCATION_COUNT),
|
|
|
|
REG64(GS_PRIMITIVES_COUNT),
|
|
|
|
REG64(CL_INVOCATION_COUNT),
|
|
|
|
REG64(CL_PRIMITIVES_COUNT),
|
|
|
|
REG64(PS_INVOCATION_COUNT),
|
|
|
|
REG64(PS_DEPTH_COUNT),
|
2016-03-07 14:30:26 +07:00
|
|
|
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
|
2014-11-08 02:00:26 +07:00
|
|
|
REG64(MI_PREDICATE_SRC0),
|
|
|
|
REG64(MI_PREDICATE_SRC1),
|
2015-05-29 20:44:14 +07:00
|
|
|
REG32(GEN7_3DPRIM_END_OFFSET),
|
|
|
|
REG32(GEN7_3DPRIM_START_VERTEX),
|
|
|
|
REG32(GEN7_3DPRIM_VERTEX_COUNT),
|
|
|
|
REG32(GEN7_3DPRIM_INSTANCE_COUNT),
|
|
|
|
REG32(GEN7_3DPRIM_START_INSTANCE),
|
|
|
|
REG32(GEN7_3DPRIM_BASE_VERTEX),
|
2015-10-02 13:09:58 +07:00
|
|
|
REG32(GEN7_GPGPU_DISPATCHDIMX),
|
|
|
|
REG32(GEN7_GPGPU_DISPATCHDIMY),
|
|
|
|
REG32(GEN7_GPGPU_DISPATCHDIMZ),
|
2016-08-18 23:17:11 +07:00
|
|
|
REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
|
2015-11-07 02:44:40 +07:00
|
|
|
REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
|
|
|
|
REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
|
|
|
|
REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
|
|
|
|
REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
|
|
|
|
REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
|
|
|
|
REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
|
|
|
|
REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
|
|
|
|
REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
|
2015-05-29 20:44:14 +07:00
|
|
|
REG32(GEN7_SO_WRITE_OFFSET(0)),
|
|
|
|
REG32(GEN7_SO_WRITE_OFFSET(1)),
|
|
|
|
REG32(GEN7_SO_WRITE_OFFSET(2)),
|
|
|
|
REG32(GEN7_SO_WRITE_OFFSET(3)),
|
|
|
|
REG32(GEN7_L3SQCREG1),
|
|
|
|
REG32(GEN7_L3CNTLREG2),
|
|
|
|
REG32(GEN7_L3CNTLREG3),
|
2016-08-18 23:17:11 +07:00
|
|
|
REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
|
2016-03-07 14:30:28 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
|
2016-03-07 14:30:29 +07:00
|
|
|
REG64_IDX(HSW_CS_GPR, 0),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 1),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 2),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 3),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 4),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 5),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 6),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 7),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 8),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 9),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 10),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 11),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 12),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 13),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 14),
|
|
|
|
REG64_IDX(HSW_CS_GPR, 15),
|
2015-05-29 20:44:15 +07:00
|
|
|
REG32(HSW_SCRATCH1,
|
|
|
|
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
|
|
|
|
.value = 0),
|
|
|
|
REG32(HSW_ROW_CHICKEN3,
|
|
|
|
.mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
|
|
|
|
HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
|
|
|
|
.value = 0),
|
2014-02-19 01:15:50 +07:00
|
|
|
};
|
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
|
2016-08-18 23:17:11 +07:00
|
|
|
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
|
|
|
|
REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
|
2015-05-29 20:44:14 +07:00
|
|
|
REG32(BCS_SWCTRL),
|
2016-08-18 23:17:11 +07:00
|
|
|
REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
|
2014-02-19 01:15:50 +07:00
|
|
|
};
|
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
|
|
|
|
REG32(FORCEWAKE_MT),
|
|
|
|
REG32(DERRMR),
|
|
|
|
REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
|
|
|
|
REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
|
|
|
|
REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
|
2014-02-19 01:15:51 +07:00
|
|
|
};
|
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
|
|
|
|
REG32(FORCEWAKE_MT),
|
|
|
|
REG32(DERRMR),
|
2014-02-19 01:15:51 +07:00
|
|
|
};
|
|
|
|
|
2014-02-19 01:15:50 +07:00
|
|
|
#undef REG64
|
2015-05-29 20:44:14 +07:00
|
|
|
#undef REG32
|
2014-02-19 01:15:50 +07:00
|
|
|
|
2016-03-07 14:30:27 +07:00
|
|
|
struct drm_i915_reg_table {
|
|
|
|
const struct drm_i915_reg_descriptor *regs;
|
|
|
|
int num_regs;
|
|
|
|
bool master;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
|
|
|
|
{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
|
|
|
|
{ ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
|
|
|
|
{ gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
|
|
|
|
{ ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
|
|
|
|
{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
|
2016-03-07 14:30:28 +07:00
|
|
|
{ hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
|
2016-03-07 14:30:27 +07:00
|
|
|
{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
|
|
|
|
{ gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
|
|
|
|
{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
|
|
|
|
};
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
|
|
|
|
{
|
2016-11-15 05:39:34 +07:00
|
|
|
u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 subclient =
|
|
|
|
(cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
|
|
|
|
|
|
|
|
if (client == INSTR_MI_CLIENT)
|
|
|
|
return 0x3F;
|
|
|
|
else if (client == INSTR_RC_CLIENT) {
|
|
|
|
if (subclient == INSTR_MEDIA_SUBCLIENT)
|
|
|
|
return 0xFFFF;
|
|
|
|
else
|
|
|
|
return 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
|
|
|
|
{
|
2016-11-15 05:39:34 +07:00
|
|
|
u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 subclient =
|
|
|
|
(cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
|
2014-11-22 00:35:36 +07:00
|
|
|
u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
if (client == INSTR_MI_CLIENT)
|
|
|
|
return 0x3F;
|
|
|
|
else if (client == INSTR_RC_CLIENT) {
|
2014-11-22 00:35:36 +07:00
|
|
|
if (subclient == INSTR_MEDIA_SUBCLIENT) {
|
|
|
|
if (op == 6)
|
|
|
|
return 0xFFFF;
|
|
|
|
else
|
|
|
|
return 0xFFF;
|
|
|
|
} else
|
2014-02-19 01:15:46 +07:00
|
|
|
return 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
|
|
|
|
{
|
2016-11-15 05:39:34 +07:00
|
|
|
u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
if (client == INSTR_MI_CLIENT)
|
|
|
|
return 0x3F;
|
|
|
|
else if (client == INSTR_BC_CLIENT)
|
|
|
|
return 0xFF;
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-07-27 15:07:26 +07:00
|
|
|
static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
|
2014-05-11 04:10:43 +07:00
|
|
|
const struct drm_i915_cmd_table *cmd_tables,
|
|
|
|
int cmd_table_count)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
|
|
|
int i;
|
2014-03-28 01:43:38 +07:00
|
|
|
bool ret = true;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-05-11 04:10:43 +07:00
|
|
|
if (!cmd_tables || cmd_table_count == 0)
|
2014-03-28 01:43:38 +07:00
|
|
|
return true;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-05-11 04:10:43 +07:00
|
|
|
for (i = 0; i < cmd_table_count; i++) {
|
|
|
|
const struct drm_i915_cmd_table *table = &cmd_tables[i];
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 previous = 0;
|
|
|
|
int j;
|
|
|
|
|
|
|
|
for (j = 0; j < table->count; j++) {
|
|
|
|
const struct drm_i915_cmd_descriptor *desc =
|
2015-07-29 15:31:04 +07:00
|
|
|
&table->table[j];
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 curr = desc->cmd.value & desc->cmd.mask;
|
|
|
|
|
2014-03-28 01:43:38 +07:00
|
|
|
if (curr < previous) {
|
2016-07-27 15:07:26 +07:00
|
|
|
DRM_ERROR("CMD: %s [%d] command table not sorted: "
|
|
|
|
"table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
|
|
|
|
engine->name, engine->id,
|
|
|
|
i, j, curr, previous);
|
2014-03-28 01:43:38 +07:00
|
|
|
ret = false;
|
|
|
|
}
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
previous = curr;
|
|
|
|
}
|
|
|
|
}
|
2014-03-28 01:43:38 +07:00
|
|
|
|
|
|
|
return ret;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2016-07-27 15:07:26 +07:00
|
|
|
static bool check_sorted(const struct intel_engine_cs *engine,
|
2015-05-29 20:44:14 +07:00
|
|
|
const struct drm_i915_reg_descriptor *reg_table,
|
|
|
|
int reg_count)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u32 previous = 0;
|
2014-03-28 01:43:38 +07:00
|
|
|
bool ret = true;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
for (i = 0; i < reg_count; i++) {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-03-28 01:43:38 +07:00
|
|
|
if (curr < previous) {
|
2016-07-27 15:07:26 +07:00
|
|
|
DRM_ERROR("CMD: %s [%d] register table not sorted: "
|
|
|
|
"entry=%d reg=0x%08X prev=0x%08X\n",
|
|
|
|
engine->name, engine->id,
|
|
|
|
i, curr, previous);
|
2014-03-28 01:43:38 +07:00
|
|
|
ret = false;
|
|
|
|
}
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
previous = curr;
|
|
|
|
}
|
2014-03-28 01:43:38 +07:00
|
|
|
|
|
|
|
return ret;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static bool validate_regs_sorted(struct intel_engine_cs *engine)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
2016-03-07 14:30:27 +07:00
|
|
|
int i;
|
|
|
|
const struct drm_i915_reg_table *table;
|
|
|
|
|
|
|
|
for (i = 0; i < engine->reg_table_count; i++) {
|
|
|
|
table = &engine->reg_tables[i];
|
2016-07-27 15:07:26 +07:00
|
|
|
if (!check_sorted(engine, table->regs, table->num_regs))
|
2016-03-07 14:30:27 +07:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2014-05-11 04:10:43 +07:00
|
|
|
struct cmd_node {
|
|
|
|
const struct drm_i915_cmd_descriptor *desc;
|
|
|
|
struct hlist_node node;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Different command ranges have different numbers of bits for the opcode. For
|
|
|
|
* example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
|
|
|
|
* problem is that, for example, MI commands use bits 22:16 for other fields
|
|
|
|
* such as GGTT vs PPGTT bits. If we include those bits in the mask then when
|
|
|
|
* we mask a command from a batch it could hash to the wrong bucket due to
|
|
|
|
* non-opcode bits being set. But if we don't include those bits, some 3D
|
|
|
|
* commands may hash to the same bucket due to not including opcode bits that
|
|
|
|
* make the command unique. For now, we will risk hashing to the same bucket.
|
|
|
|
*/
|
2016-08-18 23:17:14 +07:00
|
|
|
static inline u32 cmd_header_key(u32 x)
|
|
|
|
{
|
|
|
|
u32 shift;
|
|
|
|
|
|
|
|
switch (x >> INSTR_CLIENT_SHIFT) {
|
|
|
|
default:
|
|
|
|
case INSTR_MI_CLIENT:
|
|
|
|
shift = STD_MI_OPCODE_SHIFT;
|
|
|
|
break;
|
|
|
|
case INSTR_RC_CLIENT:
|
|
|
|
shift = STD_3D_OPCODE_SHIFT;
|
|
|
|
break;
|
|
|
|
case INSTR_BC_CLIENT:
|
|
|
|
shift = STD_2D_OPCODE_SHIFT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return x >> shift;
|
|
|
|
}
|
2014-05-11 04:10:43 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int init_hash_table(struct intel_engine_cs *engine,
|
2014-05-11 04:10:43 +07:00
|
|
|
const struct drm_i915_cmd_table *cmd_tables,
|
|
|
|
int cmd_table_count)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
hash_init(engine->cmd_hash);
|
2014-05-11 04:10:43 +07:00
|
|
|
|
|
|
|
for (i = 0; i < cmd_table_count; i++) {
|
|
|
|
const struct drm_i915_cmd_table *table = &cmd_tables[i];
|
|
|
|
|
|
|
|
for (j = 0; j < table->count; j++) {
|
|
|
|
const struct drm_i915_cmd_descriptor *desc =
|
|
|
|
&table->table[j];
|
|
|
|
struct cmd_node *desc_node =
|
|
|
|
kmalloc(sizeof(*desc_node), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!desc_node)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
desc_node->desc = desc;
|
2016-03-16 18:00:37 +07:00
|
|
|
hash_add(engine->cmd_hash, &desc_node->node,
|
2016-08-18 23:17:14 +07:00
|
|
|
cmd_header_key(desc->cmd.value));
|
2014-05-11 04:10:43 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void fini_hash_table(struct intel_engine_cs *engine)
|
2014-05-11 04:10:43 +07:00
|
|
|
{
|
|
|
|
struct hlist_node *tmp;
|
|
|
|
struct cmd_node *desc_node;
|
|
|
|
int i;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
|
2014-05-11 04:10:43 +07:00
|
|
|
hash_del(&desc_node->node);
|
|
|
|
kfree(desc_node);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
/**
|
2016-07-27 15:07:26 +07:00
|
|
|
* intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
|
2016-06-03 20:02:17 +07:00
|
|
|
* @engine: the engine to initialize
|
2014-02-19 01:15:46 +07:00
|
|
|
*
|
|
|
|
* Optionally initializes fields related to batch buffer command parsing in the
|
2014-05-22 20:13:33 +07:00
|
|
|
* struct intel_engine_cs based on whether the platform requires software
|
2014-02-19 01:15:46 +07:00
|
|
|
* command parsing.
|
|
|
|
*/
|
2016-08-18 23:17:10 +07:00
|
|
|
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
2014-05-11 04:10:43 +07:00
|
|
|
const struct drm_i915_cmd_table *cmd_tables;
|
|
|
|
int cmd_table_count;
|
|
|
|
int ret;
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (!IS_GEN7(engine->i915))
|
2016-08-18 23:17:10 +07:00
|
|
|
return;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
switch (engine->id) {
|
2014-02-19 01:15:46 +07:00
|
|
|
case RCS:
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_HASWELL(engine->i915)) {
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = hsw_render_ring_cmds;
|
|
|
|
cmd_table_count =
|
2014-02-19 01:15:47 +07:00
|
|
|
ARRAY_SIZE(hsw_render_ring_cmds);
|
|
|
|
} else {
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = gen7_render_cmds;
|
|
|
|
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
|
2014-02-19 01:15:47 +07:00
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_HASWELL(engine->i915)) {
|
2016-03-07 14:30:27 +07:00
|
|
|
engine->reg_tables = hsw_render_reg_tables;
|
|
|
|
engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
|
2014-02-19 01:15:51 +07:00
|
|
|
} else {
|
2016-03-07 14:30:27 +07:00
|
|
|
engine->reg_tables = ivb_render_reg_tables;
|
|
|
|
engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
|
2014-02-19 01:15:51 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
|
|
|
case VCS:
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = gen7_video_cmds;
|
|
|
|
cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
|
|
|
case BCS:
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_HASWELL(engine->i915)) {
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = hsw_blt_ring_cmds;
|
|
|
|
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
|
2014-02-19 01:15:48 +07:00
|
|
|
} else {
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = gen7_blt_cmds;
|
|
|
|
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
|
2014-02-19 01:15:48 +07:00
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_HASWELL(engine->i915)) {
|
2016-03-07 14:30:27 +07:00
|
|
|
engine->reg_tables = hsw_blt_reg_tables;
|
|
|
|
engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
|
2014-02-19 01:15:51 +07:00
|
|
|
} else {
|
2016-03-07 14:30:27 +07:00
|
|
|
engine->reg_tables = ivb_blt_reg_tables;
|
|
|
|
engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
|
2014-02-19 01:15:51 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
|
|
|
case VECS:
|
2014-05-11 04:10:43 +07:00
|
|
|
cmd_tables = hsw_vebox_cmds;
|
|
|
|
cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
|
2014-02-19 01:15:46 +07:00
|
|
|
/* VECS can use the same length_mask function as VCS */
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
|
|
|
default:
|
2016-07-27 15:07:26 +07:00
|
|
|
MISSING_CASE(engine->id);
|
2016-08-18 23:17:10 +07:00
|
|
|
return;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2016-08-18 23:17:10 +07:00
|
|
|
if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
|
|
|
|
DRM_ERROR("%s: command descriptions are not sorted\n",
|
|
|
|
engine->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!validate_regs_sorted(engine)) {
|
|
|
|
DRM_ERROR("%s: registers are not sorted\n", engine->name);
|
|
|
|
return;
|
|
|
|
}
|
2014-11-20 06:33:08 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = init_hash_table(engine, cmd_tables, cmd_table_count);
|
2014-11-20 06:33:08 +07:00
|
|
|
if (ret) {
|
2016-08-18 23:17:10 +07:00
|
|
|
DRM_ERROR("%s: initialised failed!\n", engine->name);
|
2016-03-16 18:00:37 +07:00
|
|
|
fini_hash_table(engine);
|
2016-08-18 23:17:10 +07:00
|
|
|
return;
|
2014-05-11 04:10:43 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->needs_cmd_parser = true;
|
2014-05-11 04:10:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-07-27 15:07:26 +07:00
|
|
|
* intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
|
2016-06-03 20:02:17 +07:00
|
|
|
* @engine: the engine to clean up
|
2014-05-11 04:10:43 +07:00
|
|
|
*
|
|
|
|
* Releases any resources related to command parsing that may have been
|
2016-07-27 15:07:26 +07:00
|
|
|
* initialized for the specified engine.
|
2014-05-11 04:10:43 +07:00
|
|
|
*/
|
2016-07-27 15:07:26 +07:00
|
|
|
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
|
2014-05-11 04:10:43 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
if (!engine->needs_cmd_parser)
|
2014-05-11 04:10:43 +07:00
|
|
|
return;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
fini_hash_table(engine);
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_i915_cmd_descriptor*
|
2016-03-16 18:00:37 +07:00
|
|
|
find_cmd_in_table(struct intel_engine_cs *engine,
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 cmd_header)
|
|
|
|
{
|
2014-05-11 04:10:43 +07:00
|
|
|
struct cmd_node *desc_node;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
hash_for_each_possible(engine->cmd_hash, desc_node, node,
|
2016-08-18 23:17:14 +07:00
|
|
|
cmd_header_key(cmd_header)) {
|
2014-05-11 04:10:43 +07:00
|
|
|
const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
|
2016-08-18 23:17:14 +07:00
|
|
|
if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
|
2014-02-19 01:15:46 +07:00
|
|
|
return desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returns a pointer to a descriptor for the command specified by cmd_header.
|
|
|
|
*
|
|
|
|
* The caller must supply space for a default descriptor via the default_desc
|
2016-07-27 15:07:26 +07:00
|
|
|
* parameter. If no descriptor for the specified command exists in the engine's
|
2014-02-19 01:15:46 +07:00
|
|
|
* command parser tables, this function fills in default_desc based on the
|
2016-07-27 15:07:26 +07:00
|
|
|
* engine's default length encoding and returns default_desc.
|
2014-02-19 01:15:46 +07:00
|
|
|
*/
|
|
|
|
static const struct drm_i915_cmd_descriptor*
|
2016-03-16 18:00:37 +07:00
|
|
|
find_cmd(struct intel_engine_cs *engine,
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 cmd_header,
|
2016-08-18 23:17:15 +07:00
|
|
|
const struct drm_i915_cmd_descriptor *desc,
|
2014-02-19 01:15:46 +07:00
|
|
|
struct drm_i915_cmd_descriptor *default_desc)
|
|
|
|
{
|
|
|
|
u32 mask;
|
|
|
|
|
2016-08-18 23:17:15 +07:00
|
|
|
if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
|
|
|
|
return desc;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
desc = find_cmd_in_table(engine, cmd_header);
|
2014-05-11 04:10:43 +07:00
|
|
|
if (desc)
|
|
|
|
return desc;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
mask = engine->get_cmd_length_mask(cmd_header);
|
2014-02-19 01:15:46 +07:00
|
|
|
if (!mask)
|
|
|
|
return NULL;
|
|
|
|
|
2016-08-18 23:17:15 +07:00
|
|
|
default_desc->cmd.value = cmd_header;
|
|
|
|
default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
|
2014-02-19 01:15:46 +07:00
|
|
|
default_desc->length.mask = mask;
|
2016-08-18 23:17:15 +07:00
|
|
|
default_desc->flags = CMD_DESC_SKIP;
|
2014-02-19 01:15:46 +07:00
|
|
|
return default_desc;
|
|
|
|
}
|
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
static const struct drm_i915_reg_descriptor *
|
2016-08-18 23:17:17 +07:00
|
|
|
__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
2016-08-18 23:17:17 +07:00
|
|
|
int start = 0, end = count;
|
|
|
|
while (start < end) {
|
|
|
|
int mid = start + (end - start) / 2;
|
|
|
|
int ret = addr - i915_mmio_reg_offset(table[mid].addr);
|
|
|
|
if (ret < 0)
|
|
|
|
end = mid;
|
|
|
|
else if (ret > 0)
|
|
|
|
start = mid + 1;
|
|
|
|
else
|
|
|
|
return &table[mid];
|
2016-03-07 14:30:27 +07:00
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_i915_reg_descriptor *
|
2016-08-18 23:17:17 +07:00
|
|
|
find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr)
|
2016-03-07 14:30:27 +07:00
|
|
|
{
|
2016-08-18 23:17:17 +07:00
|
|
|
const struct drm_i915_reg_table *table = engine->reg_tables;
|
|
|
|
int count = engine->reg_table_count;
|
2016-03-07 14:30:27 +07:00
|
|
|
|
2016-08-18 23:17:17 +07:00
|
|
|
do {
|
2016-03-07 14:30:27 +07:00
|
|
|
if (!table->master || is_master) {
|
2016-08-18 23:17:17 +07:00
|
|
|
const struct drm_i915_reg_descriptor *reg;
|
|
|
|
|
|
|
|
reg = __find_reg(table->regs, table->num_regs, addr);
|
2016-03-07 14:30:27 +07:00
|
|
|
if (reg != NULL)
|
|
|
|
return reg;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
2016-08-18 23:17:17 +07:00
|
|
|
} while (table++, --count);
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
return NULL;
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
/* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
|
|
|
|
static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
|
2014-12-12 03:13:10 +07:00
|
|
|
struct drm_i915_gem_object *src_obj,
|
|
|
|
u32 batch_start_offset,
|
2016-08-18 23:17:12 +07:00
|
|
|
u32 batch_len,
|
|
|
|
bool *needs_clflush_after)
|
2014-12-12 03:13:09 +07:00
|
|
|
{
|
2016-08-18 23:17:12 +07:00
|
|
|
unsigned int src_needs_clflush;
|
|
|
|
unsigned int dst_needs_clflush;
|
2016-08-18 23:17:18 +07:00
|
|
|
void *dst, *src;
|
2015-01-14 18:20:57 +07:00
|
|
|
int ret;
|
2014-12-12 03:13:10 +07:00
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
ret = i915_gem_obj_prepare_shmem_read(src_obj, &src_needs_clflush);
|
|
|
|
if (ret)
|
2014-12-12 03:13:09 +07:00
|
|
|
return ERR_PTR(ret);
|
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
ret = i915_gem_obj_prepare_shmem_write(dst_obj, &dst_needs_clflush);
|
|
|
|
if (ret) {
|
|
|
|
dst = ERR_PTR(ret);
|
2014-12-12 03:13:09 +07:00
|
|
|
goto unpin_src;
|
|
|
|
}
|
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
|
|
|
|
if (IS_ERR(dst))
|
2016-08-18 23:17:13 +07:00
|
|
|
goto unpin_dst;
|
2014-12-12 03:13:09 +07:00
|
|
|
|
2016-08-18 23:17:18 +07:00
|
|
|
src = ERR_PTR(-ENODEV);
|
|
|
|
if (src_needs_clflush &&
|
2017-01-06 22:20:09 +07:00
|
|
|
i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {
|
2016-08-18 23:17:18 +07:00
|
|
|
src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
|
|
|
|
if (!IS_ERR(src)) {
|
|
|
|
i915_memcpy_from_wc(dst,
|
|
|
|
src + batch_start_offset,
|
|
|
|
ALIGN(batch_len, 16));
|
|
|
|
i915_gem_object_unpin_map(src_obj);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (IS_ERR(src)) {
|
|
|
|
void *ptr;
|
|
|
|
int offset, n;
|
|
|
|
|
|
|
|
offset = offset_in_page(batch_start_offset);
|
|
|
|
|
|
|
|
/* We can avoid clflushing partial cachelines before the write
|
|
|
|
* if we only every write full cache-lines. Since we know that
|
|
|
|
* both the source and destination are in multiples of
|
|
|
|
* PAGE_SIZE, we can simply round up to the next cacheline.
|
|
|
|
* We don't care about copying too much here as we only
|
|
|
|
* validate up to the end of the batch.
|
|
|
|
*/
|
|
|
|
if (dst_needs_clflush & CLFLUSH_BEFORE)
|
|
|
|
batch_len = roundup(batch_len,
|
|
|
|
boot_cpu_data.x86_clflush_size);
|
|
|
|
|
|
|
|
ptr = dst;
|
|
|
|
for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) {
|
|
|
|
int len = min_t(int, batch_len, PAGE_SIZE - offset);
|
|
|
|
|
|
|
|
src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
|
|
|
|
if (src_needs_clflush)
|
|
|
|
drm_clflush_virt_range(src + offset, len);
|
|
|
|
memcpy(ptr, src + offset, len);
|
|
|
|
kunmap_atomic(src);
|
|
|
|
|
|
|
|
ptr += len;
|
|
|
|
batch_len -= len;
|
|
|
|
offset = 0;
|
|
|
|
}
|
2016-08-18 23:17:13 +07:00
|
|
|
}
|
2014-12-12 03:13:09 +07:00
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
/* dst_obj is returned with vmap pinned */
|
|
|
|
*needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
|
|
|
|
|
|
|
|
unpin_dst:
|
|
|
|
i915_gem_obj_finish_shmem_access(dst_obj);
|
2014-12-12 03:13:09 +07:00
|
|
|
unpin_src:
|
2016-08-18 23:16:47 +07:00
|
|
|
i915_gem_obj_finish_shmem_access(src_obj);
|
2016-08-18 23:17:12 +07:00
|
|
|
return dst;
|
2014-12-12 03:13:09 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static bool check_cmd(const struct intel_engine_cs *engine,
|
2014-03-28 01:43:39 +07:00
|
|
|
const struct drm_i915_cmd_descriptor *desc,
|
2015-05-29 20:44:13 +07:00
|
|
|
const u32 *cmd, u32 length,
|
2016-11-08 19:51:48 +07:00
|
|
|
const bool is_master)
|
2014-03-28 01:43:39 +07:00
|
|
|
{
|
2016-08-18 23:17:16 +07:00
|
|
|
if (desc->flags & CMD_DESC_SKIP)
|
|
|
|
return true;
|
|
|
|
|
2014-03-28 01:43:39 +07:00
|
|
|
if (desc->flags & CMD_DESC_REJECT) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
|
|
|
|
*cmd);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (desc->flags & CMD_DESC_REGISTER) {
|
2014-03-29 00:21:50 +07:00
|
|
|
/*
|
2015-05-29 20:44:13 +07:00
|
|
|
* Get the distance between individual register offset
|
|
|
|
* fields if the command can perform more than one
|
|
|
|
* access at a time.
|
2014-03-29 00:21:50 +07:00
|
|
|
*/
|
2015-05-29 20:44:13 +07:00
|
|
|
const u32 step = desc->reg.step ? desc->reg.step : length;
|
|
|
|
u32 offset;
|
|
|
|
|
|
|
|
for (offset = desc->reg.offset; offset < length;
|
|
|
|
offset += step) {
|
|
|
|
const u32 reg_addr = cmd[offset] & desc->reg.mask;
|
2015-05-29 20:44:14 +07:00
|
|
|
const struct drm_i915_reg_descriptor *reg =
|
2016-08-18 23:17:17 +07:00
|
|
|
find_reg(engine, is_master, reg_addr);
|
2015-05-29 20:44:14 +07:00
|
|
|
|
|
|
|
if (!reg) {
|
2017-04-11 19:43:06 +07:00
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
|
|
|
|
reg_addr, *cmd, engine->name);
|
2015-05-29 20:44:14 +07:00
|
|
|
return false;
|
|
|
|
}
|
2015-05-29 20:44:13 +07:00
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
/*
|
|
|
|
* Check the value written to the register against the
|
|
|
|
* allowed mask/value pair given in the whitelist entry.
|
|
|
|
*/
|
|
|
|
if (reg->mask) {
|
2015-08-04 22:22:20 +07:00
|
|
|
if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
|
2015-05-29 20:44:14 +07:00
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
|
|
|
|
reg_addr);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-05-06 14:50:14 +07:00
|
|
|
if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
|
|
|
|
reg_addr);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-05-29 20:44:14 +07:00
|
|
|
if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
|
|
|
|
(offset + 2 > length ||
|
|
|
|
(cmd[offset + 1] & reg->mask) != reg->value)) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
|
|
|
|
reg_addr);
|
2015-05-29 20:44:13 +07:00
|
|
|
return false;
|
|
|
|
}
|
2014-03-28 01:43:39 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (desc->flags & CMD_DESC_BITMASK) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
|
|
|
|
u32 dword;
|
|
|
|
|
|
|
|
if (desc->bits[i].mask == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (desc->bits[i].condition_mask != 0) {
|
|
|
|
u32 offset =
|
|
|
|
desc->bits[i].condition_offset;
|
|
|
|
u32 condition = cmd[offset] &
|
|
|
|
desc->bits[i].condition_mask;
|
|
|
|
|
|
|
|
if (condition == 0)
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
dword = cmd[desc->bits[i].offset] &
|
|
|
|
desc->bits[i].mask;
|
|
|
|
|
|
|
|
if (dword != desc->bits[i].expected) {
|
2017-04-11 19:43:06 +07:00
|
|
|
DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
|
2014-03-28 01:43:39 +07:00
|
|
|
*cmd,
|
|
|
|
desc->bits[i].mask,
|
|
|
|
desc->bits[i].expected,
|
2017-04-11 19:43:06 +07:00
|
|
|
dword, engine->name);
|
2014-03-28 01:43:39 +07:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
#define LENGTH_BIAS 2
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_parse_cmds() - parse a submitted batch buffer for privilege violations
|
2016-06-03 20:02:17 +07:00
|
|
|
* @engine: the engine on which the batch is to execute
|
2014-02-19 01:15:46 +07:00
|
|
|
* @batch_obj: the batch buffer in question
|
2014-12-12 03:13:09 +07:00
|
|
|
* @shadow_batch_obj: copy of the batch buffer in question
|
2014-02-19 01:15:46 +07:00
|
|
|
* @batch_start_offset: byte offset in the batch at which execution starts
|
2014-12-12 03:13:10 +07:00
|
|
|
* @batch_len: length of the commands in batch_obj
|
2014-02-19 01:15:46 +07:00
|
|
|
* @is_master: is the submitting process the drm master?
|
|
|
|
*
|
|
|
|
* Parses the specified batch buffer looking for privilege violations as
|
|
|
|
* described in the overview.
|
|
|
|
*
|
2014-10-17 02:24:42 +07:00
|
|
|
* Return: non-zero if the parser finds violations or otherwise fails; -EACCES
|
|
|
|
* if the batch appears legal but should use hardware parsing
|
2014-02-19 01:15:46 +07:00
|
|
|
*/
|
2016-07-27 15:07:26 +07:00
|
|
|
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
|
|
|
|
struct drm_i915_gem_object *batch_obj,
|
|
|
|
struct drm_i915_gem_object *shadow_batch_obj,
|
|
|
|
u32 batch_start_offset,
|
|
|
|
u32 batch_len,
|
|
|
|
bool is_master)
|
2014-02-19 01:15:46 +07:00
|
|
|
{
|
2016-08-18 23:17:12 +07:00
|
|
|
u32 *cmd, *batch_end;
|
2016-08-18 23:17:15 +07:00
|
|
|
struct drm_i915_cmd_descriptor default_desc = noop_desc;
|
|
|
|
const struct drm_i915_cmd_descriptor *desc = &default_desc;
|
2016-08-18 23:17:12 +07:00
|
|
|
bool needs_clflush_after = false;
|
2015-01-14 18:20:57 +07:00
|
|
|
int ret = 0;
|
2014-12-12 03:13:12 +07:00
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
cmd = copy_batch(shadow_batch_obj, batch_obj,
|
|
|
|
batch_start_offset, batch_len,
|
|
|
|
&needs_clflush_after);
|
|
|
|
if (IS_ERR(cmd)) {
|
2014-12-12 03:13:09 +07:00
|
|
|
DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
|
2016-08-18 23:17:12 +07:00
|
|
|
return PTR_ERR(cmd);
|
2014-02-19 01:15:46 +07:00
|
|
|
}
|
|
|
|
|
2014-12-12 03:13:09 +07:00
|
|
|
/*
|
2014-12-12 03:13:10 +07:00
|
|
|
* We use the batch length as size because the shadow object is as
|
2014-12-12 03:13:09 +07:00
|
|
|
* large or larger and copy_batch() will write MI_NOPs to the extra
|
|
|
|
* space. Parsing should be faster in some cases this way.
|
|
|
|
*/
|
2016-08-18 23:17:12 +07:00
|
|
|
batch_end = cmd + (batch_len / sizeof(*batch_end));
|
2017-03-10 18:55:18 +07:00
|
|
|
do {
|
2014-02-19 01:15:46 +07:00
|
|
|
u32 length;
|
|
|
|
|
2017-03-10 18:55:18 +07:00
|
|
|
if (*cmd == MI_BATCH_BUFFER_END) {
|
|
|
|
if (needs_clflush_after) {
|
|
|
|
void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);
|
|
|
|
drm_clflush_virt_range(ptr,
|
|
|
|
(void *)(cmd + 1) - ptr);
|
|
|
|
}
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
2017-03-10 18:55:18 +07:00
|
|
|
}
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2016-08-18 23:17:15 +07:00
|
|
|
desc = find_cmd(engine, *cmd, desc, &default_desc);
|
2014-02-19 01:15:46 +07:00
|
|
|
if (!desc) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
|
|
|
|
*cmd);
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-10-17 02:24:42 +07:00
|
|
|
/*
|
|
|
|
* If the batch buffer contains a chained batch, return an
|
|
|
|
* error that tells the caller to abort and dispatch the
|
|
|
|
* workload as a non-secure batch.
|
|
|
|
*/
|
|
|
|
if (desc->cmd.value == MI_BATCH_BUFFER_START) {
|
|
|
|
ret = -EACCES;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
if (desc->flags & CMD_DESC_FIXED)
|
|
|
|
length = desc->length.fixed;
|
|
|
|
else
|
|
|
|
length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
|
|
|
|
|
|
|
|
if ((batch_end - cmd) < length) {
|
2014-04-02 15:24:20 +07:00
|
|
|
DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
|
2014-02-19 01:15:46 +07:00
|
|
|
*cmd,
|
|
|
|
length,
|
2014-04-28 20:03:23 +07:00
|
|
|
batch_end - cmd);
|
2014-02-19 01:15:46 +07:00
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-11-08 19:51:48 +07:00
|
|
|
if (!check_cmd(engine, desc, cmd, length, is_master)) {
|
2016-11-08 02:49:49 +07:00
|
|
|
ret = -EACCES;
|
2014-02-19 01:15:46 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd += length;
|
2017-03-10 18:55:18 +07:00
|
|
|
if (cmd >= batch_end) {
|
|
|
|
DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} while (1);
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2016-08-18 23:17:12 +07:00
|
|
|
i915_gem_object_unpin_map(shadow_batch_obj);
|
2014-02-19 01:15:46 +07:00
|
|
|
return ret;
|
|
|
|
}
|
2014-02-19 01:15:56 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_cmd_parser_get_version() - get the cmd parser version number
|
2016-06-03 20:02:17 +07:00
|
|
|
* @dev_priv: i915 device private
|
2014-02-19 01:15:56 +07:00
|
|
|
*
|
|
|
|
* The cmd parser maintains a simple increasing integer version number suitable
|
|
|
|
* for passing to userspace clients to determine what operations are permitted.
|
|
|
|
*
|
|
|
|
* Return: the current version number of the cmd parser
|
|
|
|
*/
|
2016-05-04 20:25:36 +07:00
|
|
|
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
|
2014-02-19 01:15:56 +07:00
|
|
|
{
|
2016-05-04 20:25:36 +07:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 00:14:48 +07:00
|
|
|
enum intel_engine_id id;
|
2016-05-04 20:25:36 +07:00
|
|
|
bool active = false;
|
|
|
|
|
|
|
|
/* If the command parser is not enabled, report 0 - unsupported */
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 00:14:48 +07:00
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for_each_engine(engine, dev_priv, id) {
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2016-11-24 19:58:51 +07:00
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if (engine->needs_cmd_parser) {
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2016-05-04 20:25:36 +07:00
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active = true;
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break;
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}
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}
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if (!active)
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return 0;
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2014-02-19 01:15:56 +07:00
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/*
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* Command parser version history
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*
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* 1. Initial version. Checks batches and reports violations, but leaves
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* hardware parsing enabled (so does not allow new use cases).
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2014-11-08 02:00:26 +07:00
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* 2. Allow access to the MI_PREDICATE_SRC0 and
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* MI_PREDICATE_SRC1 registers.
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2014-12-12 04:28:09 +07:00
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* 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
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2015-06-15 18:03:29 +07:00
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* 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
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2015-10-02 13:09:58 +07:00
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* 5. GPGPU dispatch compute indirect registers.
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2016-03-07 14:30:30 +07:00
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* 6. TIMESTAMP register and Haswell CS GPR registers
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2016-05-06 14:50:14 +07:00
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* 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
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2016-11-08 02:49:49 +07:00
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* 8. Don't report cmd_check() failures as EINVAL errors to userspace;
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* rely on the HW to NOOP disallowed commands as it would without
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* the parser enabled.
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2016-11-08 19:51:48 +07:00
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* 9. Don't whitelist or handle oacontrol specially, as ownership
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* for oacontrol state is moving to i915-perf.
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2014-02-19 01:15:56 +07:00
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*/
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2016-11-08 19:51:48 +07:00
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return 9;
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2014-02-19 01:15:56 +07:00
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}
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