linux_dsm_epyc7002/drivers/clk/sunxi/clk-factors.h

#ifndef __MACH_SUNXI_CLK_FACTORS_H
#define __MACH_SUNXI_CLK_FACTORS_H

#include <linux/clk-provider.h>
#include <linux/clkdev.h>

#define SUNXI_FACTORS_NOT_APPLICABLE	(0)

struct clk_factors_config {
	u8 nshift;
	u8 nwidth;
	u8 kshift;
	u8 kwidth;
	u8 mshift;
	u8 mwidth;
	u8 pshift;
	u8 pwidth;
};

struct clk *clk_register_factors(struct device *dev, const char *name,
				 const char *parent_name,
				 unsigned long flags, void __iomem *reg,
				 struct clk_factors_config *config,
				 void (*get_factors) (u32 *rate, u32 parent_rate,
						      u8 *n, u8 *k, u8 *m, u8 *p),
				 spinlock_t *lock);
#endif
clk: arm: sunxi: Add a new clock driver for sunxi SOCs This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2013-02-25 21:44:26 +07:00			`#ifndef __MACH_SUNXI_CLK_FACTORS_H`
			`#define __MACH_SUNXI_CLK_FACTORS_H`

			`#include <linux/clk-provider.h>`
			`#include <linux/clkdev.h>`

			`#define SUNXI_FACTORS_NOT_APPLICABLE (0)`

			`struct clk_factors_config {`
			`u8 nshift;`
			`u8 nwidth;`
			`u8 kshift;`
			`u8 kwidth;`
			`u8 mshift;`
			`u8 mwidth;`
			`u8 pshift;`
			`u8 pwidth;`
			`};`

			`struct clk clk_register_factors(struct device dev, const char *name,`
			`const char *parent_name,`
			`unsigned long flags, void __iomem *reg,`
			`struct clk_factors_config *config,`
			`void (get_factors) (u32 rate, u32 parent_rate,`
			`u8 n, u8 k, u8 m, u8 p),`
			`spinlock_t *lock);`
			`#endif`