linux_dsm_epyc7002/drivers/clk/tegra/Makefile

obj-y					+= clk.o
obj-y					+= clk-audio-sync.o
obj-y					+= clk-dfll.o
obj-y					+= clk-divider.o
obj-y					+= clk-periph.o
obj-y					+= clk-periph-fixed.o
obj-y					+= clk-periph-gate.o
obj-y					+= clk-pll.o
obj-y					+= clk-pll-out.o
obj-y					+= clk-super.o
obj-y					+= clk-tegra-audio.o
obj-y					+= clk-tegra-periph.o
obj-y					+= clk-tegra-pmc.o
obj-y					+= clk-tegra-fixed.o
obj-y					+= clk-tegra-super-gen4.o
obj-$(CONFIG_TEGRA_CLK_EMC)		+= clk-emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o
obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
obj-y					+= cvb.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
clk: tegra: add Tegra specific clocks Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re: storing pointers to stack variables, make a timeout loop more idiomatic, use _clk_pll_disable() not clk_disable_pll() from _program_pll() to avoid redundant lock operations, unified tegra_clk_periph() and tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock registration functions so they don't have the same name as the clock structs, return -EINVAL from clk_plle_enable when matching table rate not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-01-11 14:46:20 +07:00			`obj-y += clk.o`
			`obj-y += clk-audio-sync.o`
clk: tegra: Add library for the DFLL clock source (open-loop mode) Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from December (http://comments.gmane.org/gmane.linux.ports.tegra/15273), which in turn comes from the internal driver by originally created by Aleksandr Frid <afrid@nvidia.com>. Subsequent patches will add support for closed loop mode and drivers for the Tegra124 fast CPU cluster DFLL devices, which rely on this code. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-13 21:58:36 +07:00			`obj-y += clk-dfll.o`
clk: tegra: add Tegra specific clocks Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re: storing pointers to stack variables, make a timeout loop more idiomatic, use _clk_pll_disable() not clk_disable_pll() from _program_pll() to avoid redundant lock operations, unified tegra_clk_periph() and tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock registration functions so they don't have the same name as the clock structs, return -EINVAL from clk_plle_enable when matching table rate not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-01-11 14:46:20 +07:00			`obj-y += clk-divider.o`
			`obj-y += clk-periph.o`
clk: tegra: Add fixed factor peripheral clock type Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-20 19:34:57 +07:00			`obj-y += clk-periph-fixed.o`
clk: tegra: add Tegra specific clocks Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re: storing pointers to stack variables, make a timeout loop more idiomatic, use _clk_pll_disable() not clk_disable_pll() from _program_pll() to avoid redundant lock operations, unified tegra_clk_periph() and tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock registration functions so they don't have the same name as the clock structs, return -EINVAL from clk_plle_enable when matching table rate not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-01-11 14:46:20 +07:00			`obj-y += clk-periph-gate.o`
			`obj-y += clk-pll.o`
			`obj-y += clk-pll-out.o`
			`obj-y += clk-super.o`
clk: tegra: move audio clk to common file Move audio clocks and PLLA initialization to a common file so it can be used by multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114 which specifies which common clocks are available on Tegra114 and what their DT IDs are. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 2013-09-17 19:42:24 +07:00			`obj-y += clk-tegra-audio.o`
clk: tegra: move periph clocks to common file Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 2013-09-04 21:04:19 +07:00			`obj-y += clk-tegra-periph.o`
clk: tegra: move PMC, fixed clocks to common files Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 2013-10-15 21:19:13 +07:00			`obj-y += clk-tegra-pmc.o`
			`obj-y += clk-tegra-fixed.o`
clk: tegra: introduce common gen4 super clock Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> 2013-09-03 19:46:01 +07:00			`obj-y += clk-tegra-super-gen4.o`
clk: tegra: EMC clock driver depends on EMC driver The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-01 14:10:58 +07:00			`obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o`
clk: tegra: add clock support for Tegra20 Add Tegra20 clock support based on common clock framework. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe, implemented KBC clock, ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-01-11 14:46:24 +07:00			`obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o`
clk: tegra: add clock support for Tegra30 Add Tegra30 clock support based on common clock framework. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-01-11 14:46:25 +07:00			`obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o`
clk: tegra: Implement clocks for Tegra114 Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> 2013-04-03 21:40:45 +07:00			`obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o`
clk: tegra: EMC clock driver depends on EMC driver The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-01 14:10:58 +07:00			`obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o`
clk: tegra: Add Tegra124 DFLL clocksource platform driver Add basic platform driver support for the fast CPU cluster DFLL clocksource found on Tegra124 SoCs. This small driver selects the appropriate Tegra124-specific characterization data and integration code. It relies on the DFLL common code to do most of the work. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> [treding@nvidia.com: move setup code into ->probe()] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-13 21:58:41 +07:00			`obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o`
clk: tegra: Add support for the Tegra132 CAR IP block Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences. Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support. This patch is based on several patches from others: 1. a patch from Peter De Schrijver: http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html 2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and 3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132"). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Bill Huang <bilhuang@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> 2014-12-17 03:38:29 +07:00			`obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o`
clk: tegra: Add Tegra124 DFLL clocksource platform driver Add basic platform driver support for the fast CPU cluster DFLL clocksource found on Tegra124 SoCs. This small driver selects the appropriate Tegra124-specific characterization data and integration code. It relies on the DFLL common code to do most of the work. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> [treding@nvidia.com: move setup code into ->probe()] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-13 21:58:41 +07:00			`obj-y += cvb.o`
clk: tegra: Add support for Tegra210 clocks Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-06-19 04:28:36 +07:00			`obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o`