2009-01-03 04:33:00 +07:00
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/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/delay.h>
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2013-08-07 02:32:18 +07:00
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#include <linux/hdmi.h>
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2019-04-05 18:00:03 +07:00
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#include <linux/i2c.h>
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#include <linux/slab.h>
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2015-01-23 07:50:32 +07:00
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#include <drm/drm_atomic_helper.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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2018-01-09 02:55:42 +07:00
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#include <drm/drm_hdcp.h>
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drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
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#include <drm/drm_scdc_helper.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/i915_drm.h>
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2017-01-25 05:57:50 +07:00
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#include <drm/intel_lpe_audio.h>
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2019-04-05 18:00:03 +07:00
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2019-05-02 22:02:43 +07:00
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#include "i915_debugfs.h"
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2009-01-03 04:33:00 +07:00
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#include "i915_drv.h"
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2019-04-29 19:53:31 +07:00
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#include "intel_atomic.h"
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2019-04-05 18:00:03 +07:00
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#include "intel_audio.h"
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2019-04-05 18:00:06 +07:00
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#include "intel_connector.h"
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2019-04-05 18:00:05 +07:00
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#include "intel_ddi.h"
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2019-08-06 18:39:33 +07:00
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#include "intel_display_types.h"
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2019-04-05 18:00:17 +07:00
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#include "intel_dp.h"
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2019-05-02 22:02:40 +07:00
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#include "intel_dpio_phy.h"
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2019-04-29 19:29:24 +07:00
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#include "intel_fifo_underrun.h"
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2019-05-02 22:02:47 +07:00
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#include "intel_gmbus.h"
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2019-04-05 18:00:13 +07:00
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#include "intel_hdcp.h"
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2019-04-05 18:00:18 +07:00
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#include "intel_hdmi.h"
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2019-04-29 19:50:11 +07:00
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#include "intel_hotplug.h"
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2019-04-05 18:00:11 +07:00
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#include "intel_lspcon.h"
|
2019-04-05 18:00:14 +07:00
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#include "intel_panel.h"
|
2019-08-06 18:39:33 +07:00
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#include "intel_sdvo.h"
|
2019-04-26 15:17:22 +07:00
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#include "intel_sideband.h"
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2009-01-03 04:33:00 +07:00
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2012-10-27 04:05:45 +07:00
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static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
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{
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2012-10-27 04:05:46 +07:00
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return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
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2012-10-27 04:05:45 +07:00
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}
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2012-06-12 21:36:45 +07:00
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static void
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assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
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{
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2012-10-27 04:05:45 +07:00
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struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
|
2016-07-04 17:34:36 +07:00
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struct drm_i915_private *dev_priv = to_i915(dev);
|
2018-06-12 16:19:30 +07:00
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u32 enabled_bits;
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2012-06-12 21:36:45 +07:00
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2016-10-13 17:02:52 +07:00
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enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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2012-06-12 21:36:45 +07:00
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2013-02-19 05:00:26 +07:00
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WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
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2012-06-12 21:36:45 +07:00
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"HDMI port enabled, expecting disabled\n");
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}
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2018-06-14 00:07:08 +07:00
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static void
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assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
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enum transcoder cpu_transcoder)
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{
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WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
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TRANS_DDI_FUNC_ENABLE,
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"HDMI transcoder function enabled, expecting disabled\n");
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}
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2012-05-10 01:37:30 +07:00
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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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2010-08-04 19:50:23 +07:00
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{
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2012-10-27 04:05:46 +07:00
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struct intel_digital_port *intel_dig_port =
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container_of(encoder, struct intel_digital_port, base.base);
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return &intel_dig_port->hdmi;
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2010-08-04 19:50:23 +07:00
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}
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2010-09-09 22:20:55 +07:00
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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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{
|
2012-10-27 04:05:46 +07:00
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return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
|
2010-09-09 22:20:55 +07:00
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}
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|
2017-10-14 02:40:51 +07:00
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static u32 g4x_infoframe_index(unsigned int type)
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2010-09-25 02:44:32 +07:00
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{
|
2013-08-07 02:32:18 +07:00
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switch (type) {
|
2019-02-26 00:40:58 +07:00
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case HDMI_PACKET_TYPE_GAMUT_METADATA:
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return VIDEO_DIP_SELECT_GAMUT;
|
2013-08-07 02:32:18 +07:00
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case HDMI_INFOFRAME_TYPE_AVI:
|
2012-05-15 03:12:50 +07:00
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return VIDEO_DIP_SELECT_AVI;
|
2013-08-07 02:32:18 +07:00
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case HDMI_INFOFRAME_TYPE_SPD:
|
2012-05-15 03:12:50 +07:00
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return VIDEO_DIP_SELECT_SPD;
|
2013-08-19 22:59:04 +07:00
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|
|
case HDMI_INFOFRAME_TYPE_VENDOR:
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return VIDEO_DIP_SELECT_VENDOR;
|
2011-08-03 23:22:55 +07:00
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default:
|
2015-12-16 23:10:00 +07:00
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|
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MISSING_CASE(type);
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2012-05-15 03:12:50 +07:00
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|
return 0;
|
2011-08-03 23:22:55 +07:00
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|
}
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}
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|
2017-10-14 02:40:51 +07:00
|
|
|
static u32 g4x_infoframe_enable(unsigned int type)
|
2011-08-03 23:22:55 +07:00
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|
{
|
2013-08-07 02:32:18 +07:00
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|
switch (type) {
|
2019-02-26 00:40:58 +07:00
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case HDMI_PACKET_TYPE_GENERAL_CONTROL:
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return VIDEO_DIP_ENABLE_GCP;
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case HDMI_PACKET_TYPE_GAMUT_METADATA:
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return VIDEO_DIP_ENABLE_GAMUT;
|
2019-02-26 00:40:59 +07:00
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case DP_SDP_VSC:
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return 0;
|
2013-08-07 02:32:18 +07:00
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case HDMI_INFOFRAME_TYPE_AVI:
|
2012-05-15 03:12:50 +07:00
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|
return VIDEO_DIP_ENABLE_AVI;
|
2013-08-07 02:32:18 +07:00
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case HDMI_INFOFRAME_TYPE_SPD:
|
2012-05-15 03:12:50 +07:00
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|
return VIDEO_DIP_ENABLE_SPD;
|
2013-08-19 22:59:04 +07:00
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case HDMI_INFOFRAME_TYPE_VENDOR:
|
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return VIDEO_DIP_ENABLE_VENDOR;
|
2019-05-16 21:10:15 +07:00
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|
case HDMI_INFOFRAME_TYPE_DRM:
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return 0;
|
2012-05-05 03:18:20 +07:00
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default:
|
2015-12-16 23:10:00 +07:00
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MISSING_CASE(type);
|
2012-05-15 03:12:50 +07:00
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return 0;
|
2012-05-05 03:18:20 +07:00
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}
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}
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|
2017-10-14 02:40:51 +07:00
|
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static u32 hsw_infoframe_enable(unsigned int type)
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2012-05-15 03:12:51 +07:00
|
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|
{
|
2013-08-07 02:32:18 +07:00
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switch (type) {
|
2019-02-26 00:40:58 +07:00
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case HDMI_PACKET_TYPE_GENERAL_CONTROL:
|
|
|
|
return VIDEO_DIP_ENABLE_GCP_HSW;
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case HDMI_PACKET_TYPE_GAMUT_METADATA:
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|
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|
return VIDEO_DIP_ENABLE_GMP_HSW;
|
2017-10-14 02:40:51 +07:00
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case DP_SDP_VSC:
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|
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return VIDEO_DIP_ENABLE_VSC_HSW;
|
2018-11-29 03:26:20 +07:00
|
|
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case DP_SDP_PPS:
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|
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return VDIP_ENABLE_PPS;
|
2013-08-07 02:32:18 +07:00
|
|
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case HDMI_INFOFRAME_TYPE_AVI:
|
2012-05-15 03:12:51 +07:00
|
|
|
return VIDEO_DIP_ENABLE_AVI_HSW;
|
2013-08-07 02:32:18 +07:00
|
|
|
case HDMI_INFOFRAME_TYPE_SPD:
|
2012-05-15 03:12:51 +07:00
|
|
|
return VIDEO_DIP_ENABLE_SPD_HSW;
|
2013-08-19 22:59:04 +07:00
|
|
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case HDMI_INFOFRAME_TYPE_VENDOR:
|
|
|
|
return VIDEO_DIP_ENABLE_VS_HSW;
|
2019-05-17 23:22:25 +07:00
|
|
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case HDMI_INFOFRAME_TYPE_DRM:
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return VIDEO_DIP_ENABLE_DRM_GLK;
|
2012-05-15 03:12:51 +07:00
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default:
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2015-12-16 23:10:00 +07:00
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MISSING_CASE(type);
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2012-05-15 03:12:51 +07:00
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return 0;
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}
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}
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|
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
static i915_reg_t
|
|
|
|
hsw_dip_data_reg(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
int i)
|
2012-05-15 03:12:51 +07:00
|
|
|
{
|
2013-08-07 02:32:18 +07:00
|
|
|
switch (type) {
|
2019-02-26 00:40:58 +07:00
|
|
|
case HDMI_PACKET_TYPE_GAMUT_METADATA:
|
|
|
|
return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
|
2017-10-14 02:40:51 +07:00
|
|
|
case DP_SDP_VSC:
|
|
|
|
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
|
2018-11-29 03:26:20 +07:00
|
|
|
case DP_SDP_PPS:
|
|
|
|
return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
|
2013-08-07 02:32:18 +07:00
|
|
|
case HDMI_INFOFRAME_TYPE_AVI:
|
2015-09-19 00:03:37 +07:00
|
|
|
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
|
2013-08-07 02:32:18 +07:00
|
|
|
case HDMI_INFOFRAME_TYPE_SPD:
|
2015-09-19 00:03:37 +07:00
|
|
|
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
|
2013-08-19 22:59:04 +07:00
|
|
|
case HDMI_INFOFRAME_TYPE_VENDOR:
|
2015-09-19 00:03:37 +07:00
|
|
|
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
|
2019-05-17 23:22:25 +07:00
|
|
|
case HDMI_INFOFRAME_TYPE_DRM:
|
|
|
|
return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
|
2012-05-15 03:12:51 +07:00
|
|
|
default:
|
2015-12-16 23:10:00 +07:00
|
|
|
MISSING_CASE(type);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
return INVALID_MMIO_REG;
|
2012-05-15 03:12:51 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-20 02:53:09 +07:00
|
|
|
static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int type)
|
2018-11-29 03:26:20 +07:00
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case DP_SDP_VSC:
|
|
|
|
return VIDEO_DIP_VSC_DATA_SIZE;
|
|
|
|
case DP_SDP_PPS:
|
|
|
|
return VIDEO_DIP_PPS_DATA_SIZE;
|
2019-09-20 02:53:09 +07:00
|
|
|
case HDMI_PACKET_TYPE_GAMUT_METADATA:
|
|
|
|
if (INTEL_GEN(dev_priv) >= 11)
|
|
|
|
return VIDEO_DIP_GMP_DATA_SIZE;
|
|
|
|
else
|
|
|
|
return VIDEO_DIP_DATA_SIZE;
|
2018-11-29 03:26:20 +07:00
|
|
|
default:
|
|
|
|
return VIDEO_DIP_DATA_SIZE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void g4x_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2013-12-10 20:19:08 +07:00
|
|
|
const void *frame, ssize_t len)
|
2011-08-03 23:22:55 +07:00
|
|
|
{
|
2018-06-12 16:19:30 +07:00
|
|
|
const u32 *data = frame;
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2012-05-05 03:18:17 +07:00
|
|
|
u32 val = I915_READ(VIDEO_DIP_CTL);
|
2013-08-07 02:32:18 +07:00
|
|
|
int i;
|
2010-09-25 02:44:32 +07:00
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
|
|
|
|
|
2012-05-05 03:18:18 +07:00
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_index(type);
|
2012-05-05 03:18:17 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val &= ~g4x_infoframe_enable(type);
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(VIDEO_DIP_CTL, val);
|
2010-09-25 02:44:32 +07:00
|
|
|
|
2011-08-03 23:22:55 +07:00
|
|
|
for (i = 0; i < len; i += 4) {
|
2010-09-25 02:44:32 +07:00
|
|
|
I915_WRITE(VIDEO_DIP_DATA, *data);
|
|
|
|
data++;
|
|
|
|
}
|
2012-09-25 23:23:34 +07:00
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
|
|
|
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
|
|
|
|
I915_WRITE(VIDEO_DIP_DATA, 0);
|
2010-09-25 02:44:32 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_enable(type);
|
2012-05-05 03:18:22 +07:00
|
|
|
val &= ~VIDEO_DIP_FREQ_MASK;
|
2012-05-08 19:41:00 +07:00
|
|
|
val |= VIDEO_DIP_FREQ_VSYNC;
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(VIDEO_DIP_CTL, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(VIDEO_DIP_CTL);
|
2010-09-25 02:44:32 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
static void g4x_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
u32 val, *data = frame;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = I915_READ(VIDEO_DIP_CTL);
|
|
|
|
|
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
|
|
|
val |= g4x_infoframe_index(type);
|
|
|
|
|
|
|
|
I915_WRITE(VIDEO_DIP_CTL, val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4)
|
|
|
|
*data++ = I915_READ(VIDEO_DIP_DATA);
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
|
2015-11-26 23:27:07 +07:00
|
|
|
const struct intel_crtc_state *pipe_config)
|
2014-11-06 05:26:08 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2014-11-06 05:26:08 +07:00
|
|
|
u32 val = I915_READ(VIDEO_DIP_CTL);
|
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
if ((val & VIDEO_DIP_ENABLE) == 0)
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2014-11-21 04:24:13 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-05-05 21:06:25 +07:00
|
|
|
|
|
|
|
return val & (VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
|
2014-11-06 05:26:08 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void ibx_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2013-12-10 20:19:08 +07:00
|
|
|
const void *frame, ssize_t len)
|
2012-05-05 03:18:24 +07:00
|
|
|
{
|
2018-06-12 16:19:30 +07:00
|
|
|
const u32 *data = frame;
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
2012-05-05 03:18:24 +07:00
|
|
|
u32 val = I915_READ(reg);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
int i;
|
2012-05-05 03:18:24 +07:00
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
|
|
|
|
|
2012-05-05 03:18:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_index(type);
|
2012-05-05 03:18:24 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val &= ~g4x_infoframe_enable(type);
|
2012-05-05 03:18:24 +07:00
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4) {
|
|
|
|
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
|
|
|
|
data++;
|
|
|
|
}
|
2012-09-25 23:23:34 +07:00
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
|
|
|
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
|
|
|
|
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
|
2012-05-05 03:18:24 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_enable(type);
|
2012-05-05 03:18:24 +07:00
|
|
|
val &= ~VIDEO_DIP_FREQ_MASK;
|
2012-05-08 19:41:00 +07:00
|
|
|
val |= VIDEO_DIP_FREQ_VSYNC;
|
2012-05-05 03:18:24 +07:00
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-05 03:18:24 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
static void ibx_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
u32 val, *data = frame;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
|
|
|
|
|
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
|
|
|
val |= g4x_infoframe_index(type);
|
|
|
|
|
|
|
|
I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4)
|
|
|
|
*data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
|
2015-11-26 23:27:07 +07:00
|
|
|
const struct intel_crtc_state *pipe_config)
|
2014-11-06 05:26:08 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-11-26 23:27:07 +07:00
|
|
|
enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
|
|
|
|
i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
|
2014-11-06 05:26:08 +07:00
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
if ((val & VIDEO_DIP_ENABLE) == 0)
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-05-05 21:06:25 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-04-29 19:30:07 +07:00
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
return val & (VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2014-11-06 05:26:08 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void cpt_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2013-12-10 20:19:08 +07:00
|
|
|
const void *frame, ssize_t len)
|
2011-07-09 01:31:57 +07:00
|
|
|
{
|
2018-06-12 16:19:30 +07:00
|
|
|
const u32 *data = frame;
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
2012-05-05 03:18:17 +07:00
|
|
|
u32 val = I915_READ(reg);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
int i;
|
2011-07-09 01:31:57 +07:00
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
|
|
|
|
|
2011-09-22 12:46:00 +07:00
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_index(type);
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2012-05-05 03:18:21 +07:00
|
|
|
/* The DIP control register spec says that we need to update the AVI
|
|
|
|
* infoframe without clearing its enable bit */
|
2013-08-07 02:32:18 +07:00
|
|
|
if (type != HDMI_INFOFRAME_TYPE_AVI)
|
|
|
|
val &= ~g4x_infoframe_enable(type);
|
2012-05-05 03:18:21 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(reg, val);
|
2011-08-03 23:22:55 +07:00
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4) {
|
2011-07-09 01:31:57 +07:00
|
|
|
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
|
|
|
|
data++;
|
|
|
|
}
|
2012-09-25 23:23:34 +07:00
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
|
|
|
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
|
|
|
|
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
|
2011-07-09 01:31:57 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_enable(type);
|
2012-05-05 03:18:22 +07:00
|
|
|
val &= ~VIDEO_DIP_FREQ_MASK;
|
2012-05-08 19:41:00 +07:00
|
|
|
val |= VIDEO_DIP_FREQ_VSYNC;
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2011-08-03 23:22:55 +07:00
|
|
|
}
|
2012-03-29 03:39:32 +07:00
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
static void cpt_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
u32 val, *data = frame;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
|
|
|
|
|
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
|
|
|
val |= g4x_infoframe_index(type);
|
|
|
|
|
|
|
|
I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4)
|
|
|
|
*data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
|
2015-11-26 23:27:07 +07:00
|
|
|
const struct intel_crtc_state *pipe_config)
|
2014-11-06 05:26:08 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-11-26 23:27:07 +07:00
|
|
|
enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
|
|
|
|
u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
|
2014-11-06 05:26:08 +07:00
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
if ((val & VIDEO_DIP_ENABLE) == 0)
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-05-05 21:06:25 +07:00
|
|
|
|
|
|
|
return val & (VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2014-11-06 05:26:08 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void vlv_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2013-12-10 20:19:08 +07:00
|
|
|
const void *frame, ssize_t len)
|
2012-03-29 03:39:32 +07:00
|
|
|
{
|
2018-06-12 16:19:30 +07:00
|
|
|
const u32 *data = frame;
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
2012-05-05 03:18:17 +07:00
|
|
|
u32 val = I915_READ(reg);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
int i;
|
2012-03-29 03:39:32 +07:00
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
|
|
|
|
|
2012-03-29 03:39:32 +07:00
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_index(type);
|
2012-05-05 03:18:17 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val &= ~g4x_infoframe_enable(type);
|
2012-03-29 03:39:32 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-03-29 03:39:32 +07:00
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4) {
|
|
|
|
I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
|
|
|
|
data++;
|
|
|
|
}
|
2012-09-25 23:23:34 +07:00
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
|
|
|
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
|
|
|
|
I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
|
2012-03-29 03:39:32 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= g4x_infoframe_enable(type);
|
2012-05-05 03:18:22 +07:00
|
|
|
val &= ~VIDEO_DIP_FREQ_MASK;
|
2012-05-08 19:41:00 +07:00
|
|
|
val |= VIDEO_DIP_FREQ_VSYNC;
|
2012-03-29 03:39:32 +07:00
|
|
|
|
2012-05-05 03:18:17 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-03-29 03:39:32 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
static void vlv_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
u32 val, *data = frame;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
|
|
|
|
|
|
|
|
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
|
|
|
|
val |= g4x_infoframe_index(type);
|
|
|
|
|
|
|
|
I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4)
|
|
|
|
*data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
|
2015-11-26 23:27:07 +07:00
|
|
|
const struct intel_crtc_state *pipe_config)
|
2014-11-06 05:26:08 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-11-26 23:27:07 +07:00
|
|
|
enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
|
|
|
|
u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
|
2014-11-06 05:26:08 +07:00
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
if ((val & VIDEO_DIP_ENABLE) == 0)
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-05-05 21:06:25 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
|
2019-02-26 00:40:59 +07:00
|
|
|
return 0;
|
2015-04-16 06:52:29 +07:00
|
|
|
|
2015-05-05 21:06:25 +07:00
|
|
|
return val & (VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2014-11-06 05:26:08 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void hsw_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2013-12-10 20:19:08 +07:00
|
|
|
const void *frame, ssize_t len)
|
2012-05-10 20:18:02 +07:00
|
|
|
{
|
2018-06-12 16:19:30 +07:00
|
|
|
const u32 *data = frame;
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
|
2018-11-29 03:26:20 +07:00
|
|
|
int data_size;
|
2013-08-07 02:32:18 +07:00
|
|
|
int i;
|
2012-05-15 03:12:51 +07:00
|
|
|
u32 val = I915_READ(ctl_reg);
|
2012-05-10 20:18:02 +07:00
|
|
|
|
2019-09-20 02:53:09 +07:00
|
|
|
data_size = hsw_dip_data_size(dev_priv, type);
|
|
|
|
|
|
|
|
WARN_ON(len > data_size);
|
2018-11-29 03:26:20 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val &= ~hsw_infoframe_enable(type);
|
2012-05-15 03:12:51 +07:00
|
|
|
I915_WRITE(ctl_reg, val);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4) {
|
2015-09-19 00:03:37 +07:00
|
|
|
I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
|
|
|
|
type, i >> 2), *data);
|
2012-05-15 03:12:51 +07:00
|
|
|
data++;
|
|
|
|
}
|
2012-09-25 23:23:34 +07:00
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
2017-10-14 02:40:51 +07:00
|
|
|
for (; i < data_size; i += 4)
|
2015-09-19 00:03:37 +07:00
|
|
|
I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
|
|
|
|
type, i >> 2), 0);
|
2012-05-10 20:18:02 +07:00
|
|
|
|
2013-08-07 02:32:18 +07:00
|
|
|
val |= hsw_infoframe_enable(type);
|
2012-05-15 03:12:51 +07:00
|
|
|
I915_WRITE(ctl_reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(ctl_reg);
|
2012-05-10 20:18:02 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
static void hsw_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
unsigned int type,
|
|
|
|
void *frame, ssize_t len)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
|
|
|
u32 val, *data = frame;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
|
|
|
|
|
|
|
|
for (i = 0; i < len; i += 4)
|
|
|
|
*data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
|
|
|
|
type, i >> 2));
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
|
2015-11-26 23:27:07 +07:00
|
|
|
const struct intel_crtc_state *pipe_config)
|
2014-11-06 05:26:08 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-11-26 23:27:07 +07:00
|
|
|
u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
|
2019-05-17 23:22:25 +07:00
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
|
|
|
|
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
|
|
|
|
VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
|
|
|
mask |= VIDEO_DIP_ENABLE_DRM_GLK;
|
2014-11-06 05:26:08 +07:00
|
|
|
|
2019-05-17 23:22:25 +07:00
|
|
|
return val & mask;
|
2014-11-06 05:26:08 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
static const u8 infoframe_type_to_idx[] = {
|
|
|
|
HDMI_PACKET_TYPE_GENERAL_CONTROL,
|
|
|
|
HDMI_PACKET_TYPE_GAMUT_METADATA,
|
|
|
|
DP_SDP_VSC,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
2019-05-18 17:39:27 +07:00
|
|
|
HDMI_INFOFRAME_TYPE_DRM,
|
2019-02-26 00:40:59 +07:00
|
|
|
};
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
u32 intel_hdmi_infoframe_enable(unsigned int type)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
|
|
|
|
if (infoframe_type_to_idx[i] == type)
|
|
|
|
return BIT(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:40:59 +07:00
|
|
|
u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
|
|
|
|
u32 val, ret = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
val = dig_port->infoframes_enabled(encoder, crtc_state);
|
|
|
|
|
|
|
|
/* map from hardware bits to dip idx */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
|
|
|
|
unsigned int type = infoframe_type_to_idx[i];
|
|
|
|
|
|
|
|
if (HAS_DDI(dev_priv)) {
|
|
|
|
if (val & hsw_infoframe_enable(type))
|
|
|
|
ret |= BIT(i);
|
|
|
|
} else {
|
|
|
|
if (val & g4x_infoframe_enable(type))
|
|
|
|
ret |= BIT(i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-07 02:32:19 +07:00
|
|
|
/*
|
|
|
|
* The data we write to the DIP data buffer registers is 1 byte bigger than the
|
|
|
|
* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
|
|
|
|
* at 0). It's also a byte used by DisplayPort so the same DIP registers can be
|
|
|
|
* used for both technologies.
|
|
|
|
*
|
|
|
|
* DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
|
|
|
|
* DW1: DB3 | DB2 | DB1 | DB0
|
|
|
|
* DW2: DB7 | DB6 | DB5 | DB4
|
|
|
|
* DW3: ...
|
|
|
|
*
|
|
|
|
* (HB is Header Byte, DB is Data Byte)
|
|
|
|
*
|
|
|
|
* The hdmi pack() functions don't know about that hardware specific hole so we
|
|
|
|
* trick them by giving an offset into the buffer and moving back the header
|
|
|
|
* bytes by one.
|
|
|
|
*/
|
2018-09-21 01:51:36 +07:00
|
|
|
static void intel_write_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2019-02-26 00:41:01 +07:00
|
|
|
enum hdmi_infoframe_type type,
|
|
|
|
const union hdmi_infoframe *frame)
|
2011-08-03 23:22:55 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
|
2018-06-12 16:19:30 +07:00
|
|
|
u8 buffer[VIDEO_DIP_DATA_SIZE];
|
2013-08-07 02:32:19 +07:00
|
|
|
ssize_t len;
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
if ((crtc_state->infoframes.enable &
|
|
|
|
intel_hdmi_infoframe_enable(type)) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (WARN_ON(frame->any.type != type))
|
|
|
|
return;
|
|
|
|
|
2013-08-07 02:32:19 +07:00
|
|
|
/* see comment above for the reason for this offset */
|
2019-02-26 00:41:01 +07:00
|
|
|
len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
|
|
|
|
if (WARN_ON(len < 0))
|
2013-08-07 02:32:19 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* Insert the 'hole' (see big comment above) at position 3 */
|
2018-09-21 01:51:35 +07:00
|
|
|
memmove(&buffer[0], &buffer[1], 3);
|
2013-08-07 02:32:19 +07:00
|
|
|
buffer[3] = 0;
|
|
|
|
len++;
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
|
2011-08-03 23:22:55 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
void intel_read_infoframe(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
enum hdmi_infoframe_type type,
|
|
|
|
union hdmi_infoframe *frame)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
|
|
|
|
u8 buffer[VIDEO_DIP_DATA_SIZE];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if ((crtc_state->infoframes.enable &
|
|
|
|
intel_hdmi_infoframe_enable(type)) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_dig_port->read_infoframe(encoder, crtc_state,
|
|
|
|
type, buffer, sizeof(buffer));
|
|
|
|
|
|
|
|
/* Fill the 'hole' (see big comment above) at position 3 */
|
|
|
|
memmove(&buffer[1], &buffer[0], 3);
|
|
|
|
|
|
|
|
/* see comment above for the reason for this offset */
|
|
|
|
ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
|
|
|
|
if (ret) {
|
|
|
|
DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (frame->any.type != type)
|
|
|
|
DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
|
|
|
|
frame->any.type, type);
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
2011-08-03 23:22:55 +07:00
|
|
|
{
|
2019-02-26 00:41:01 +07:00
|
|
|
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
|
2017-01-11 19:57:24 +07:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc_state->base.adjusted_mode;
|
2019-02-26 00:41:01 +07:00
|
|
|
struct drm_connector *connector = conn_state->connector;
|
2013-08-07 02:32:19 +07:00
|
|
|
int ret;
|
2011-08-03 23:22:55 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
if (!crtc_state->has_infoframe)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
crtc_state->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
|
|
|
|
|
|
|
|
ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
|
2019-01-09 00:28:25 +07:00
|
|
|
adjusted_mode);
|
2019-02-26 00:41:01 +07:00
|
|
|
if (ret)
|
|
|
|
return false;
|
2012-04-14 02:31:41 +07:00
|
|
|
|
2018-10-12 13:23:08 +07:00
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
|
2019-02-26 00:41:01 +07:00
|
|
|
frame->colorspace = HDMI_COLORSPACE_YUV420;
|
2018-10-12 13:23:09 +07:00
|
|
|
else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
|
2019-02-26 00:41:01 +07:00
|
|
|
frame->colorspace = HDMI_COLORSPACE_YUV444;
|
2017-07-21 22:25:08 +07:00
|
|
|
else
|
2019-02-26 00:41:01 +07:00
|
|
|
frame->colorspace = HDMI_COLORSPACE_RGB;
|
2017-07-21 22:25:08 +07:00
|
|
|
|
2019-03-27 23:23:53 +07:00
|
|
|
drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
|
2017-07-21 22:25:08 +07:00
|
|
|
|
2019-07-18 23:45:23 +07:00
|
|
|
/* nonsense combination */
|
|
|
|
WARN_ON(crtc_state->limited_color_range &&
|
|
|
|
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
|
|
|
|
|
2019-07-18 21:50:44 +07:00
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
|
|
|
|
drm_hdmi_avi_infoframe_quant_range(frame, connector,
|
|
|
|
adjusted_mode,
|
|
|
|
crtc_state->limited_color_range ?
|
|
|
|
HDMI_QUANTIZATION_RANGE_LIMITED :
|
|
|
|
HDMI_QUANTIZATION_RANGE_FULL);
|
|
|
|
} else {
|
|
|
|
frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
|
|
|
|
frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
|
|
|
|
}
|
2013-01-17 21:31:31 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
drm_hdmi_avi_infoframe_content_type(frame, conn_state);
|
2018-05-15 20:59:28 +07:00
|
|
|
|
2017-07-21 22:25:08 +07:00
|
|
|
/* TODO: handle pixel repetition for YCBCR420 outputs */
|
2019-02-26 00:41:01 +07:00
|
|
|
|
|
|
|
ret = hdmi_avi_infoframe_check(frame);
|
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
2011-07-09 01:31:57 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
2011-08-03 23:22:56 +07:00
|
|
|
{
|
2019-02-26 00:41:01 +07:00
|
|
|
struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
|
2013-08-07 02:32:19 +07:00
|
|
|
int ret;
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
if (!crtc_state->has_infoframe)
|
|
|
|
return true;
|
2011-08-03 23:22:56 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
crtc_state->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
|
2011-08-03 23:22:56 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
|
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
frame->sdi = HDMI_SPD_SDI_PC;
|
|
|
|
|
|
|
|
ret = hdmi_spd_infoframe_check(frame);
|
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
2011-08-03 23:22:56 +07:00
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct hdmi_vendor_infoframe *frame =
|
|
|
|
&crtc_state->infoframes.hdmi.vendor.hdmi;
|
|
|
|
const struct drm_display_info *info =
|
|
|
|
&conn_state->connector->display_info;
|
2013-08-19 22:59:04 +07:00
|
|
|
int ret;
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
crtc_state->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
|
|
|
|
|
|
|
|
ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
|
2017-11-14 00:04:19 +07:00
|
|
|
conn_state->connector,
|
2016-11-23 21:57:00 +07:00
|
|
|
&crtc_state->base.adjusted_mode);
|
2019-02-26 00:41:01 +07:00
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
2013-08-19 22:59:04 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
ret = hdmi_vendor_infoframe_check(frame);
|
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
2013-08-19 22:59:04 +07:00
|
|
|
}
|
|
|
|
|
2019-05-18 17:39:27 +07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (!crtc_state->has_infoframe)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (!conn_state->hdr_output_metadata)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
crtc_state->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
|
|
|
|
|
|
|
|
ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
|
|
|
|
if (ret < 0) {
|
|
|
|
DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hdmi_drm_infoframe_check(frame);
|
|
|
|
if (WARN_ON(ret))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void g4x_set_infoframes(struct intel_encoder *encoder,
|
2014-04-25 04:54:47 +07:00
|
|
|
bool enable,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-29 02:42:48 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
|
2013-01-24 20:29:26 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = VIDEO_DIP_CTL;
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
u32 val = I915_READ(reg);
|
2018-09-21 01:51:36 +07:00
|
|
|
u32 port = VIDEO_DIP_PORT(encoder->port);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
|
2012-06-12 21:36:45 +07:00
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
/* If the registers were not initialized yet, they might be zeroes,
|
|
|
|
* which means we're selecting the AVI DIP and we're setting its
|
|
|
|
* frequency to once. This seems to really confuse the HW and make
|
|
|
|
* things stop working (the register spec says the AVI always needs to
|
|
|
|
* be sent every VSync). So here we avoid writing to the register more
|
|
|
|
* than we need and also explicitly select the AVI DIP and explicitly
|
|
|
|
* set its frequency to every VSync. Avoiding to write it twice seems to
|
|
|
|
* be enough to solve the problem, but being defensive shouldn't hurt us
|
|
|
|
* either. */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (!enable) {
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
2015-05-05 21:06:24 +07:00
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
|
|
|
DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
|
|
|
|
(val & VIDEO_DIP_PORT_MASK) >> 29);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:54 +07:00
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
|
|
|
if (val & VIDEO_DIP_ENABLE) {
|
2015-05-05 21:06:24 +07:00
|
|
|
DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
|
|
|
|
(val & VIDEO_DIP_PORT_MASK) >> 29);
|
|
|
|
return;
|
2012-05-29 02:42:54 +07:00
|
|
|
}
|
|
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
|
|
val |= port;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2012-05-29 02:42:50 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-29 02:42:50 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&crtc_state->infoframes.avi);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&crtc_state->infoframes.spd);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&crtc_state->infoframes.hdmi);
|
2012-05-29 02:42:48 +07:00
|
|
|
}
|
|
|
|
|
2015-05-05 21:06:21 +07:00
|
|
|
/*
|
|
|
|
* Determine if default_phase=1 can be indicated in the GCP infoframe.
|
|
|
|
*
|
|
|
|
* From HDMI specification 1.4a:
|
|
|
|
* - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
|
|
|
|
* - The first pixel following each Video Data Period shall have a pixel packing phase of 0
|
|
|
|
* - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
|
|
|
|
* - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
|
|
|
|
* phase of 0
|
|
|
|
*/
|
|
|
|
static bool gcp_default_phase_possible(int pipe_bpp,
|
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
unsigned int pixels_per_group;
|
|
|
|
|
|
|
|
switch (pipe_bpp) {
|
|
|
|
case 30:
|
|
|
|
/* 4 pixels in 5 clocks */
|
|
|
|
pixels_per_group = 4;
|
|
|
|
break;
|
|
|
|
case 36:
|
|
|
|
/* 2 pixels in 3 clocks */
|
|
|
|
pixels_per_group = 2;
|
|
|
|
break;
|
|
|
|
case 48:
|
|
|
|
/* 1 pixel in 2 clocks */
|
|
|
|
pixels_per_group = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* phase information not relevant for 8bpc */
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return mode->crtc_hdisplay % pixels_per_group == 0 &&
|
|
|
|
mode->crtc_htotal % pixels_per_group == 0 &&
|
|
|
|
mode->crtc_hblank_start % pixels_per_group == 0 &&
|
|
|
|
mode->crtc_hblank_end % pixels_per_group == 0 &&
|
|
|
|
mode->crtc_hsync_start % pixels_per_group == 0 &&
|
|
|
|
mode->crtc_hsync_end % pixels_per_group == 0 &&
|
|
|
|
((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
|
|
|
|
mode->crtc_htotal/2 % pixels_per_group == 0);
|
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2015-05-05 21:06:20 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg;
|
2019-02-26 00:41:01 +07:00
|
|
|
|
|
|
|
if ((crtc_state->infoframes.enable &
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
|
|
|
|
return false;
|
2015-05-05 21:06:20 +07:00
|
|
|
|
|
|
|
if (HAS_DDI(dev_priv))
|
2016-11-23 21:57:00 +07:00
|
|
|
reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
|
2015-12-10 03:29:35 +07:00
|
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2015-05-05 21:06:20 +07:00
|
|
|
reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
|
2016-04-07 15:08:05 +07:00
|
|
|
else if (HAS_PCH_SPLIT(dev_priv))
|
2015-05-05 21:06:20 +07:00
|
|
|
reg = TVIDEO_DIP_GCP(crtc->pipe);
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
I915_WRITE(reg, crtc_state->infoframes.gcp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:02 +07:00
|
|
|
void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
i915_reg_t reg;
|
|
|
|
|
|
|
|
if ((crtc_state->infoframes.enable &
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (HAS_DDI(dev_priv))
|
|
|
|
reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
|
|
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
|
|
reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
|
|
|
|
else if (HAS_PCH_SPLIT(dev_priv))
|
|
|
|
reg = TVIDEO_DIP_GCP(crtc->pipe);
|
|
|
|
else
|
|
|
|
return;
|
|
|
|
|
|
|
|
crtc_state->infoframes.gcp = I915_READ(reg);
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
|
|
|
if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
|
|
|
|
return;
|
|
|
|
|
|
|
|
crtc_state->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
|
|
|
|
|
2019-04-30 06:08:11 +07:00
|
|
|
/* Indicate color indication for deep color mode */
|
|
|
|
if (crtc_state->pipe_bpp > 24)
|
2019-02-26 00:41:01 +07:00
|
|
|
crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
|
2015-05-05 21:06:20 +07:00
|
|
|
|
2015-05-05 21:06:21 +07:00
|
|
|
/* Enable default_phase whenever the display mode is suitably aligned */
|
2016-11-23 21:57:00 +07:00
|
|
|
if (gcp_default_phase_possible(crtc_state->pipe_bpp,
|
|
|
|
&crtc_state->base.adjusted_mode))
|
2019-02-26 00:41:01 +07:00
|
|
|
crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
|
2015-05-05 21:06:20 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void ibx_set_infoframes(struct intel_encoder *encoder,
|
2014-04-25 04:54:47 +07:00
|
|
|
bool enable,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-29 02:42:48 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
2018-09-21 01:51:36 +07:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
|
2013-01-24 20:29:26 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
u32 val = I915_READ(reg);
|
2018-09-21 01:51:36 +07:00
|
|
|
u32 port = VIDEO_DIP_PORT(encoder->port);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
|
2012-06-12 21:36:45 +07:00
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (!enable) {
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:54 +07:00
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
2015-05-05 21:06:24 +07:00
|
|
|
WARN(val & VIDEO_DIP_ENABLE,
|
|
|
|
"DIP already enabled on port %c\n",
|
|
|
|
(val & VIDEO_DIP_PORT_MASK) >> 29);
|
2012-05-29 02:42:54 +07:00
|
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
|
|
val |= port;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
|
2015-05-05 21:06:20 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE_GCP;
|
|
|
|
|
2012-05-29 02:42:50 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-29 02:42:50 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&crtc_state->infoframes.avi);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&crtc_state->infoframes.spd);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&crtc_state->infoframes.hdmi);
|
2012-05-29 02:42:48 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void cpt_set_infoframes(struct intel_encoder *encoder,
|
2014-04-25 04:54:47 +07:00
|
|
|
bool enable,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-29 02:42:48 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
2018-09-21 01:51:36 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
|
2012-06-12 21:36:45 +07:00
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (!enable) {
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
/* Set both together, unset both together: see the spec. */
|
|
|
|
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
|
2012-05-29 02:42:53 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
2015-05-05 21:06:24 +07:00
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
|
2015-05-05 21:06:20 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE_GCP;
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&crtc_state->infoframes.avi);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&crtc_state->infoframes.spd);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&crtc_state->infoframes.hdmi);
|
2012-05-29 02:42:48 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void vlv_set_infoframes(struct intel_encoder *encoder,
|
2014-04-25 04:54:47 +07:00
|
|
|
bool enable,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-29 02:42:48 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
|
2018-09-21 01:51:36 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
u32 val = I915_READ(reg);
|
2018-09-21 01:51:36 +07:00
|
|
|
u32 port = VIDEO_DIP_PORT(encoder->port);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
|
2012-06-12 21:36:45 +07:00
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (!enable) {
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-04-03 00:08:51 +07:00
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
2015-05-05 21:06:24 +07:00
|
|
|
WARN(val & VIDEO_DIP_ENABLE,
|
|
|
|
"DIP already enabled on port %c\n",
|
|
|
|
(val & VIDEO_DIP_PORT_MASK) >> 29);
|
2014-04-03 00:08:51 +07:00
|
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
|
|
val |= port;
|
|
|
|
}
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE;
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE_AVI |
|
|
|
|
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
|
2015-05-05 21:06:20 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE_GCP;
|
|
|
|
|
2012-05-29 02:42:51 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-29 02:42:51 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&crtc_state->infoframes.avi);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&crtc_state->infoframes.spd);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&crtc_state->infoframes.hdmi);
|
2012-05-29 02:42:48 +07:00
|
|
|
}
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
static void hsw_set_infoframes(struct intel_encoder *encoder,
|
2014-04-25 04:54:47 +07:00
|
|
|
bool enable,
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-29 02:42:48 +07:00
|
|
|
{
|
2018-09-21 01:51:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
|
2012-05-29 02:42:53 +07:00
|
|
|
u32 val = I915_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
|
2018-06-14 00:07:08 +07:00
|
|
|
assert_hdmi_transcoder_func_disabled(dev_priv,
|
|
|
|
crtc_state->cpu_transcoder);
|
2012-06-12 21:36:45 +07:00
|
|
|
|
2015-05-05 21:06:24 +07:00
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
|
|
|
|
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
|
2019-05-17 23:22:25 +07:00
|
|
|
VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
|
|
|
|
VIDEO_DIP_ENABLE_DRM_GLK);
|
2015-05-05 21:06:24 +07:00
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (!enable) {
|
2015-05-05 21:06:24 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
drm/i915: properly alternate between DVI and HDMI
This solves problems that happen when you alternate between HDMI and
DVI on the same port. I can reproduce these problems using DP->HDMI
and DP->DVI adapters on a DP port.
When you first plug HDMI and then plug DVI, you need to stop sending
DIPs, even if the port is in DVI mode (see the HDMI register spec). If
you don't stop sending DIPs, you'll see a pink vertical line on the
left side of the screen, some modes will give you a black screen, some
modes won't work correctly.
When you first plug DVI and then plug HDMI, you need to properly
enable the DIPs, otherwise the HW won't send them. After spending a
lot of time investigating this, I concluded that if the DIPs are
disabled, we should not write to the DIP register again because when
we do this, we also set the AVI InfoFrame frequency to "once", and
this seems to really confuse our hardware. Since this problem was not
exactly easy to debug, I'm adopting the defensive behavior and not
just avoing the "disable twice" sequence, but also explicitly
selecting the AVI InfoFrame and setting its frequency to a correct
one.
Also, move the "is_dvi" check from intel_set_infoframe to the
set_infoframes functions since now they're going to be the first ones
to deal with the DIP registers.
This patch adds the code to fix the problem, but it depends on the
removal of some code that can't be removed right now and will come
later in the patch series. The patch that we need is:
- drm/i915: don't write 0 to DIP control at HDMI init
[danvet: Paulo clarified that this additional patch is only required
to make the fix complete, this patch here alone doesn't introduce a
regression but only partially solves the problem of randomly clearing
the dip registers.]
V2: Be even more defensive by selecting AVI and setting its frequency
outside the "is_dvi" check.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-05-29 02:42:49 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
|
2015-05-05 21:06:20 +07:00
|
|
|
val |= VIDEO_DIP_ENABLE_GCP_HSW;
|
|
|
|
|
2012-05-29 02:42:53 +07:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-29 02:43:00 +07:00
|
|
|
POSTING_READ(reg);
|
2012-05-29 02:42:53 +07:00
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&crtc_state->infoframes.avi);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&crtc_state->infoframes.spd);
|
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&crtc_state->infoframes.hdmi);
|
2019-05-18 17:39:27 +07:00
|
|
|
intel_write_infoframe(encoder, crtc_state,
|
|
|
|
HDMI_INFOFRAME_TYPE_DRM,
|
|
|
|
&crtc_state->infoframes.drm);
|
2012-05-29 02:42:48 +07:00
|
|
|
}
|
|
|
|
|
2016-05-03 02:08:24 +07:00
|
|
|
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
|
|
|
|
struct i2c_adapter *adapter =
|
|
|
|
intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
|
|
|
|
|
|
|
|
if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
|
|
|
|
enable ? "Enabling" : "Disabling");
|
|
|
|
|
|
|
|
drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
|
|
|
|
adapter, enable);
|
|
|
|
}
|
|
|
|
|
2018-01-09 02:55:42 +07:00
|
|
|
static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
|
|
|
|
unsigned int offset, void *buffer, size_t size)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
intel_dig_port->base.base.dev->dev_private;
|
|
|
|
struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
|
|
|
|
hdmi->ddc_bus);
|
|
|
|
int ret;
|
|
|
|
u8 start = offset & 0xff;
|
|
|
|
struct i2c_msg msgs[] = {
|
|
|
|
{
|
|
|
|
.addr = DRM_HDCP_DDC_ADDR,
|
|
|
|
.flags = 0,
|
|
|
|
.len = 1,
|
|
|
|
.buf = &start,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.addr = DRM_HDCP_DDC_ADDR,
|
|
|
|
.flags = I2C_M_RD,
|
|
|
|
.len = size,
|
|
|
|
.buf = buffer
|
|
|
|
}
|
|
|
|
};
|
|
|
|
ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
|
|
|
|
if (ret == ARRAY_SIZE(msgs))
|
|
|
|
return 0;
|
|
|
|
return ret >= 0 ? -EIO : ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
|
|
|
|
unsigned int offset, void *buffer, size_t size)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
intel_dig_port->base.base.dev->dev_private;
|
|
|
|
struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
|
|
|
|
hdmi->ddc_bus);
|
|
|
|
int ret;
|
|
|
|
u8 *write_buf;
|
|
|
|
struct i2c_msg msg;
|
|
|
|
|
|
|
|
write_buf = kzalloc(size + 1, GFP_KERNEL);
|
|
|
|
if (!write_buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
write_buf[0] = offset & 0xff;
|
|
|
|
memcpy(&write_buf[1], buffer, size);
|
|
|
|
|
|
|
|
msg.addr = DRM_HDCP_DDC_ADDR;
|
|
|
|
msg.flags = 0,
|
|
|
|
msg.len = size + 1,
|
|
|
|
msg.buf = write_buf;
|
|
|
|
|
|
|
|
ret = i2c_transfer(adapter, &msg, 1);
|
|
|
|
if (ret == 1)
|
2018-08-24 03:51:36 +07:00
|
|
|
ret = 0;
|
|
|
|
else if (ret >= 0)
|
|
|
|
ret = -EIO;
|
|
|
|
|
|
|
|
kfree(write_buf);
|
|
|
|
return ret;
|
2018-01-09 02:55:42 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 *an)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
intel_dig_port->base.base.dev->dev_private;
|
|
|
|
struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
|
|
|
|
hdmi->ddc_bus);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
|
|
|
|
DRM_HDCP_AN_LEN);
|
|
|
|
if (ret) {
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = intel_gmbus_output_aksv(adapter);
|
|
|
|
if (ret < 0) {
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 *bksv)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
|
|
|
|
DRM_HDCP_KSV_LEN);
|
|
|
|
if (ret)
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 *bstatus)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
|
|
|
|
bstatus, DRM_HDCP_BSTATUS_LEN);
|
|
|
|
if (ret)
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *repeater_present)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
|
|
|
|
if (ret) {
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 *ri_prime)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
|
|
|
|
ri_prime, DRM_HDCP_RI_LEN);
|
|
|
|
if (ret)
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *ksv_ready)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
|
|
|
|
if (ret) {
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
|
|
|
|
int num_downstream, u8 *ksv_fifo)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
|
|
|
|
ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
|
|
|
|
if (ret) {
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
|
|
|
|
int i, u32 *part)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
|
|
|
|
part, DRM_HDCP_V_PRIME_PART_LEN);
|
|
|
|
if (ret)
|
2018-10-23 17:41:28 +07:00
|
|
|
DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
|
2018-01-09 02:55:42 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-02-17 00:37:03 +07:00
|
|
|
static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
|
|
|
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
|
|
|
|
struct drm_crtc *crtc = connector->base.state->crtc;
|
|
|
|
struct intel_crtc *intel_crtc = container_of(crtc,
|
|
|
|
struct intel_crtc, base);
|
|
|
|
u32 scanline;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
|
|
|
|
if (scanline > 100 && scanline < 200)
|
|
|
|
break;
|
|
|
|
usleep_range(25, 50);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-09 02:55:42 +07:00
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool enable)
|
|
|
|
{
|
2019-02-17 00:37:03 +07:00
|
|
|
struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct intel_connector *connector = hdmi->attached_connector;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
2018-01-09 02:55:42 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!enable)
|
|
|
|
usleep_range(6, 60); /* Bspec says >= 6us */
|
|
|
|
|
|
|
|
ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("%s HDCP signalling failed (%d)\n",
|
|
|
|
enable ? "Enable" : "Disable", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2019-02-17 00:37:03 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* WA: To fix incorrect positioning of the window of
|
|
|
|
* opportunity and enc_en signalling in KABYLAKE.
|
|
|
|
*/
|
|
|
|
if (IS_KABYLAKE(dev_priv) && enable)
|
|
|
|
return kbl_repositioning_enc_en_signal(connector);
|
|
|
|
|
2018-01-09 02:55:42 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
intel_dig_port->base.base.dev->dev_private;
|
2019-08-28 23:42:16 +07:00
|
|
|
struct intel_connector *connector =
|
|
|
|
intel_dig_port->hdmi.attached_connector;
|
2018-01-09 02:55:42 +07:00
|
|
|
enum port port = intel_dig_port->base.port;
|
2019-08-28 23:42:16 +07:00
|
|
|
enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
|
2018-01-09 02:55:42 +07:00
|
|
|
int ret;
|
|
|
|
union {
|
|
|
|
u32 reg;
|
|
|
|
u8 shim[DRM_HDCP_RI_LEN];
|
|
|
|
} ri;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
|
|
|
|
if (ret)
|
|
|
|
return false;
|
|
|
|
|
2019-08-28 23:42:16 +07:00
|
|
|
I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
|
2018-01-09 02:55:42 +07:00
|
|
|
|
|
|
|
/* Wait for Ri prime match */
|
2019-08-28 23:42:16 +07:00
|
|
|
if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
|
2018-01-09 02:55:42 +07:00
|
|
|
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
|
|
|
|
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
|
2019-08-28 23:42:16 +07:00
|
|
|
I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
|
|
|
|
port)));
|
2018-01-09 02:55:42 +07:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-10-10 21:51:24 +07:00
|
|
|
struct hdcp2_hdmi_msg_timeout {
|
2019-02-17 00:37:01 +07:00
|
|
|
u8 msg_id;
|
2019-10-10 21:51:27 +07:00
|
|
|
u16 timeout;
|
2019-08-20 20:40:18 +07:00
|
|
|
};
|
|
|
|
|
2019-10-10 21:51:24 +07:00
|
|
|
static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
|
2019-10-10 21:51:26 +07:00
|
|
|
{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
|
|
|
|
{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
|
|
|
|
{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
|
|
|
|
{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
|
|
|
|
{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
|
2019-08-20 20:40:18 +07:00
|
|
|
};
|
2019-02-17 00:37:01 +07:00
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
|
2019-03-18 23:00:19 +07:00
|
|
|
u8 *rx_status)
|
2019-02-17 00:37:01 +07:00
|
|
|
{
|
|
|
|
return intel_hdmi_hdcp_read(intel_dig_port,
|
|
|
|
HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
|
|
|
|
rx_status,
|
|
|
|
HDCP_2_2_HDMI_RXSTATUS_LEN);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2019-10-10 21:51:26 +07:00
|
|
|
if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
|
|
|
|
if (is_paired)
|
|
|
|
return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
|
|
|
|
else
|
|
|
|
return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
|
|
|
|
if (hdcp2_msg_timeout[i].msg_id == msg_id)
|
2019-10-10 21:51:24 +07:00
|
|
|
return hdcp2_msg_timeout[i].timeout;
|
2019-10-10 21:51:26 +07:00
|
|
|
}
|
2019-02-17 00:37:01 +07:00
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline
|
|
|
|
int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
|
|
|
|
u8 msg_id, bool *msg_ready,
|
|
|
|
ssize_t *msg_sz)
|
|
|
|
{
|
|
|
|
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
|
|
|
|
if (ret < 0) {
|
|
|
|
DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
*msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
|
|
|
|
rx_status[0]);
|
|
|
|
|
|
|
|
if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
|
|
|
|
*msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
|
|
|
|
*msg_sz);
|
|
|
|
else
|
|
|
|
*msg_ready = *msg_sz;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t
|
|
|
|
intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 msg_id, bool paired)
|
|
|
|
{
|
|
|
|
bool msg_ready = false;
|
|
|
|
int timeout, ret;
|
|
|
|
ssize_t msg_sz = 0;
|
|
|
|
|
|
|
|
timeout = get_hdcp2_msg_timeout(msg_id, paired);
|
|
|
|
if (timeout < 0)
|
|
|
|
return timeout;
|
|
|
|
|
|
|
|
ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
|
|
|
|
msg_id, &msg_ready,
|
|
|
|
&msg_sz),
|
|
|
|
!ret && msg_ready && msg_sz, timeout * 1000,
|
|
|
|
1000, 5 * 1000);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
|
|
|
|
msg_id, ret, timeout);
|
|
|
|
|
|
|
|
return ret ? ret : msg_sz;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
|
|
|
|
void *buf, size_t size)
|
|
|
|
{
|
|
|
|
unsigned int offset;
|
|
|
|
|
|
|
|
offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
|
|
|
|
return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
|
|
|
|
u8 msg_id, void *buf, size_t size)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
|
|
|
|
unsigned int offset;
|
|
|
|
ssize_t ret;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
|
|
|
|
hdcp->is_paired);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Available msg size should be equal to or lesser than the
|
|
|
|
* available buffer.
|
|
|
|
*/
|
|
|
|
if (ret > size) {
|
|
|
|
DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
|
|
|
|
ret, size);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Re-auth request and Link Integrity Failures are represented by
|
|
|
|
* same bit. i.e reauth_req.
|
|
|
|
*/
|
|
|
|
if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
|
|
|
|
ret = HDCP_REAUTH_REQUEST;
|
|
|
|
else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
|
|
|
|
ret = HDCP_TOPOLOGY_CHANGE;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static
|
|
|
|
int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool *capable)
|
|
|
|
{
|
|
|
|
u8 hdcp2_version;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*capable = false;
|
|
|
|
ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
|
|
|
|
&hdcp2_version, sizeof(hdcp2_version));
|
|
|
|
if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
|
|
|
|
*capable = true;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline
|
|
|
|
enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
|
|
|
|
{
|
|
|
|
return HDCP_PROTOCOL_HDMI;
|
|
|
|
}
|
|
|
|
|
2018-01-09 02:55:42 +07:00
|
|
|
static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
|
|
|
|
.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
|
|
|
|
.read_bksv = intel_hdmi_hdcp_read_bksv,
|
|
|
|
.read_bstatus = intel_hdmi_hdcp_read_bstatus,
|
|
|
|
.repeater_present = intel_hdmi_hdcp_repeater_present,
|
|
|
|
.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
|
|
|
|
.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
|
|
|
|
.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
|
|
|
|
.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
|
|
|
|
.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
|
|
|
|
.check_link = intel_hdmi_hdcp_check_link,
|
2019-02-17 00:37:01 +07:00
|
|
|
.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
|
|
|
|
.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
|
|
|
|
.check_2_2_link = intel_hdmi_hdcp2_check_link,
|
|
|
|
.hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
|
|
|
|
.protocol = HDCP_PROTOCOL_HDMI,
|
2018-01-09 02:55:42 +07:00
|
|
|
};
|
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
static void intel_hdmi_prepare(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2013-07-22 02:37:04 +07:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
2013-07-22 02:37:04 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2016-11-23 21:57:00 +07:00
|
|
|
const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
|
2013-02-19 05:00:26 +07:00
|
|
|
u32 hdmi_val;
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2016-05-03 02:08:24 +07:00
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
|
|
|
|
|
2013-02-19 05:00:26 +07:00
|
|
|
hdmi_val = SDVO_ENCODING_HDMI;
|
2016-11-23 21:57:00 +07:00
|
|
|
if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
|
2015-07-06 19:10:00 +07:00
|
|
|
hdmi_val |= HDMI_COLOR_RANGE_16_235;
|
2010-07-17 01:46:31 +07:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
2013-02-19 05:00:26 +07:00
|
|
|
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
|
2010-07-17 01:46:31 +07:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
2013-02-19 05:00:26 +07:00
|
|
|
hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (crtc_state->pipe_bpp > 24)
|
2013-02-20 02:21:47 +07:00
|
|
|
hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
|
2011-06-25 02:19:25 +07:00
|
|
|
else
|
2013-02-20 02:21:47 +07:00
|
|
|
hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
|
2011-06-25 02:19:25 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
if (crtc_state->has_hdmi_sink)
|
2013-02-20 02:21:46 +07:00
|
|
|
hdmi_val |= HDMI_MODE_SELECT_HDMI;
|
2010-09-10 09:39:40 +07:00
|
|
|
|
2016-10-13 17:02:53 +07:00
|
|
|
if (HAS_PCH_CPT(dev_priv))
|
2013-07-22 02:37:04 +07:00
|
|
|
hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
|
2016-10-14 16:13:44 +07:00
|
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
2014-04-09 17:28:21 +07:00
|
|
|
hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
|
2013-02-20 02:21:46 +07:00
|
|
|
else
|
2013-07-22 02:37:04 +07:00
|
|
|
hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2013-02-19 05:00:26 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2012-07-02 18:27:29 +07:00
|
|
|
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2018-05-15 00:24:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2012-07-02 18:27:29 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_wakeref_t wakeref;
|
2016-02-12 23:55:20 +07:00
|
|
|
bool ret;
|
2012-07-02 18:27:29 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
encoder->power_domain);
|
|
|
|
if (!wakeref)
|
2014-03-05 21:20:54 +07:00
|
|
|
return false;
|
|
|
|
|
2018-05-15 00:24:21 +07:00
|
|
|
ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
|
2016-02-12 23:55:20 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
|
2016-02-12 23:55:20 +07:00
|
|
|
|
|
|
|
return ret;
|
2012-07-02 18:27:29 +07:00
|
|
|
}
|
|
|
|
|
2013-05-15 07:08:26 +07:00
|
|
|
static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2013-05-15 07:08:26 +07:00
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2014-09-12 19:46:29 +07:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-05-15 07:08:26 +07:00
|
|
|
u32 tmp, flags = 0;
|
2013-09-13 20:00:08 +07:00
|
|
|
int dotclock;
|
2013-05-15 07:08:26 +07:00
|
|
|
|
2017-10-28 02:31:23 +07:00
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
|
|
|
|
|
2013-05-15 07:08:26 +07:00
|
|
|
tmp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
|
|
|
if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
|
|
|
|
if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
if (tmp & HDMI_MODE_SELECT_HDMI)
|
|
|
|
pipe_config->has_hdmi_sink = true;
|
|
|
|
|
2019-02-26 00:41:00 +07:00
|
|
|
pipe_config->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframes_enabled(encoder, pipe_config);
|
|
|
|
|
|
|
|
if (pipe_config->infoframes.enable)
|
2014-11-06 05:26:08 +07:00
|
|
|
pipe_config->has_infoframe = true;
|
|
|
|
|
2019-04-09 21:40:50 +07:00
|
|
|
if (tmp & HDMI_AUDIO_ENABLE)
|
2014-04-25 04:54:52 +07:00
|
|
|
pipe_config->has_audio = true;
|
|
|
|
|
2016-10-13 17:02:53 +07:00
|
|
|
if (!HAS_PCH_SPLIT(dev_priv) &&
|
2014-09-12 19:46:29 +07:00
|
|
|
tmp & HDMI_COLOR_RANGE_16_235)
|
|
|
|
pipe_config->limited_color_range = true;
|
|
|
|
|
2015-01-15 19:55:22 +07:00
|
|
|
pipe_config->base.adjusted_mode.flags |= flags;
|
2013-09-13 20:00:08 +07:00
|
|
|
|
|
|
|
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
|
|
|
|
dotclock = pipe_config->port_clock * 2 / 3;
|
|
|
|
else
|
|
|
|
dotclock = pipe_config->port_clock;
|
|
|
|
|
2015-05-05 21:06:26 +07:00
|
|
|
if (pipe_config->pixel_multiplier)
|
|
|
|
dotclock /= pipe_config->pixel_multiplier;
|
|
|
|
|
2015-01-15 19:55:22 +07:00
|
|
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
2016-04-27 19:44:16 +07:00
|
|
|
|
|
|
|
pipe_config->lane_count = 4;
|
2019-02-26 00:41:02 +07:00
|
|
|
|
|
|
|
intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
|
|
|
|
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&pipe_config->infoframes.avi);
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&pipe_config->infoframes.spd);
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&pipe_config->infoframes.hdmi);
|
2013-05-15 07:08:26 +07:00
|
|
|
}
|
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2015-05-05 21:06:19 +07:00
|
|
|
{
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
2015-05-05 21:06:19 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
WARN_ON(!pipe_config->has_hdmi_sink);
|
2015-05-05 21:06:19 +07:00
|
|
|
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
|
|
|
|
pipe_name(crtc->pipe));
|
2016-11-08 19:55:38 +07:00
|
|
|
intel_audio_codec_enable(encoder, pipe_config, conn_state);
|
2015-05-05 21:06:19 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void g4x_enable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2012-06-30 13:59:56 +07:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-06-30 13:59:56 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2009-01-03 04:33:00 +07:00
|
|
|
u32 temp;
|
|
|
|
|
2013-02-19 05:00:26 +07:00
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
2009-11-02 14:52:30 +07:00
|
|
|
|
2015-05-05 21:06:23 +07:00
|
|
|
temp |= SDVO_ENABLE;
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->has_audio)
|
2019-04-09 21:40:50 +07:00
|
|
|
temp |= HDMI_AUDIO_ENABLE;
|
2012-06-05 16:03:39 +07:00
|
|
|
|
2015-05-05 21:06:23 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->has_audio)
|
|
|
|
intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
|
2015-05-05 21:06:23 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void ibx_enable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2015-05-05 21:06:23 +07:00
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-05-05 21:06:23 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
u32 temp;
|
|
|
|
|
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
2009-11-02 14:52:30 +07:00
|
|
|
|
2015-05-05 21:06:23 +07:00
|
|
|
temp |= SDVO_ENABLE;
|
2016-11-23 21:57:00 +07:00
|
|
|
if (pipe_config->has_audio)
|
2019-04-09 21:40:50 +07:00
|
|
|
temp |= HDMI_AUDIO_ENABLE;
|
2012-06-30 13:59:56 +07:00
|
|
|
|
2015-05-05 21:06:23 +07:00
|
|
|
/*
|
|
|
|
* HW workaround, need to write this twice for issue
|
|
|
|
* that may result in first write getting masked.
|
|
|
|
*/
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2013-02-19 05:00:26 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2012-06-30 13:59:56 +07:00
|
|
|
|
2015-05-05 21:06:23 +07:00
|
|
|
/*
|
|
|
|
* HW workaround, need to toggle enable bit off and on
|
|
|
|
* for 12bpc with pixel repeat.
|
|
|
|
*
|
|
|
|
* FIXME: BSpec says this should be done at the end of
|
|
|
|
* of the modeset sequence, so not sure if this isn't too soon.
|
2012-06-30 13:59:56 +07:00
|
|
|
*/
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->pipe_bpp > 24 &&
|
|
|
|
pipe_config->pixel_multiplier > 1) {
|
2015-05-05 21:06:23 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* HW workaround, need to write this twice for issue
|
|
|
|
* that may result in first write getting masked.
|
|
|
|
*/
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2013-02-19 05:00:26 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
2014-10-27 21:26:56 +07:00
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->has_audio)
|
|
|
|
intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
|
2015-05-05 21:06:19 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void cpt_enable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2015-05-05 21:06:19 +07:00
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
|
2015-05-05 21:06:19 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
u32 temp;
|
|
|
|
|
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
|
|
|
temp |= SDVO_ENABLE;
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->has_audio)
|
2019-04-09 21:40:50 +07:00
|
|
|
temp |= HDMI_AUDIO_ENABLE;
|
2015-05-05 21:06:19 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* WaEnableHDMI8bpcBefore12bpc:snb,ivb
|
|
|
|
*
|
|
|
|
* The procedure for 12bpc is as follows:
|
|
|
|
* 1. disable HDMI clock gating
|
|
|
|
* 2. enable HDMI with 8bpc
|
|
|
|
* 3. enable HDMI with 12bpc
|
|
|
|
* 4. enable HDMI clock gating
|
|
|
|
*/
|
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->pipe_bpp > 24) {
|
2015-05-05 21:06:19 +07:00
|
|
|
I915_WRITE(TRANS_CHICKEN1(pipe),
|
|
|
|
I915_READ(TRANS_CHICKEN1(pipe)) |
|
|
|
|
TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
|
|
|
|
|
|
|
|
temp &= ~SDVO_COLOR_FORMAT_MASK;
|
|
|
|
temp |= SDVO_COLOR_FORMAT_8bpc;
|
2014-10-27 21:26:56 +07:00
|
|
|
}
|
2015-05-05 21:06:19 +07:00
|
|
|
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->pipe_bpp > 24) {
|
2015-05-05 21:06:19 +07:00
|
|
|
temp &= ~SDVO_COLOR_FORMAT_MASK;
|
|
|
|
temp |= HDMI_COLOR_FORMAT_12bpc;
|
|
|
|
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
|
|
|
I915_WRITE(TRANS_CHICKEN1(pipe),
|
|
|
|
I915_READ(TRANS_CHICKEN1(pipe)) &
|
|
|
|
~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
|
|
|
|
}
|
|
|
|
|
2016-11-08 19:55:37 +07:00
|
|
|
if (pipe_config->has_audio)
|
|
|
|
intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
|
2013-07-30 16:20:31 +07:00
|
|
|
}
|
2013-04-19 04:51:36 +07:00
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void vlv_enable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2013-07-30 16:20:31 +07:00
|
|
|
{
|
2012-06-30 13:59:56 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void intel_disable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2012-06-30 13:59:56 +07:00
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-06-30 13:59:56 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2017-08-18 20:49:54 +07:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
hdmi_to_dig_port(intel_hdmi);
|
2016-11-23 21:57:00 +07:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
|
2012-06-30 13:59:56 +07:00
|
|
|
u32 temp;
|
|
|
|
|
2013-02-19 05:00:26 +07:00
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
2012-06-30 13:59:56 +07:00
|
|
|
|
2019-04-09 21:40:50 +07:00
|
|
|
temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
|
2013-02-19 05:00:26 +07:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2015-05-05 21:17:34 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* HW workaround for IBX, we need to move the port
|
|
|
|
* to transcoder A after disabling it to allow the
|
|
|
|
* matching DP port to be enabled on transcoder A.
|
|
|
|
*/
|
2016-10-13 17:02:53 +07:00
|
|
|
if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
|
2015-10-31 00:23:22 +07:00
|
|
|
/*
|
|
|
|
* We get CPU/PCH FIFO underruns on the other pipe when
|
|
|
|
* doing the workaround. Sweep them under the rug.
|
|
|
|
*/
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
|
|
|
|
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
|
|
|
|
|
2018-05-15 00:24:21 +07:00
|
|
|
temp &= ~SDVO_PIPE_SEL_MASK;
|
|
|
|
temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
|
2015-05-05 21:17:34 +07:00
|
|
|
/*
|
|
|
|
* HW workaround, need to write this twice for issue
|
|
|
|
* that may result in first write getting masked.
|
|
|
|
*/
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
|
|
|
|
temp &= ~SDVO_ENABLE;
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2015-10-31 00:23:22 +07:00
|
|
|
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
|
2015-10-31 00:23:22 +07:00
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
|
|
|
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
2015-05-05 21:17:34 +07:00
|
|
|
}
|
2015-05-05 21:06:20 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
intel_dig_port->set_infoframes(encoder,
|
|
|
|
false,
|
2017-08-18 20:49:54 +07:00
|
|
|
old_crtc_state, old_conn_state);
|
2016-05-03 02:08:24 +07:00
|
|
|
|
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void g4x_disable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2015-05-05 21:17:35 +07:00
|
|
|
{
|
2016-11-08 19:55:37 +07:00
|
|
|
if (old_crtc_state->has_audio)
|
2017-10-31 01:46:53 +07:00
|
|
|
intel_audio_codec_disable(encoder,
|
|
|
|
old_crtc_state, old_conn_state);
|
2015-05-05 21:17:35 +07:00
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
|
2015-05-05 21:17:35 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void pch_disable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2015-05-05 21:17:35 +07:00
|
|
|
{
|
2016-11-08 19:55:37 +07:00
|
|
|
if (old_crtc_state->has_audio)
|
2017-10-31 01:46:53 +07:00
|
|
|
intel_audio_codec_disable(encoder,
|
|
|
|
old_crtc_state, old_conn_state);
|
2015-05-05 21:17:35 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void pch_post_disable_hdmi(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2015-05-05 21:17:35 +07:00
|
|
|
{
|
2016-08-09 22:04:04 +07:00
|
|
|
intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
|
2015-05-05 21:17:35 +07:00
|
|
|
}
|
|
|
|
|
2017-10-30 21:57:02 +07:00
|
|
|
static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
|
2013-07-22 23:02:39 +07:00
|
|
|
{
|
2017-10-30 21:57:02 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
const struct ddi_vbt_port_info *info =
|
|
|
|
&dev_priv->vbt.ddi_port_info[encoder->port];
|
|
|
|
int max_tmds_clock;
|
|
|
|
|
2017-11-16 01:42:05 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
2017-10-30 21:57:02 +07:00
|
|
|
max_tmds_clock = 594000;
|
|
|
|
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
|
|
|
|
max_tmds_clock = 300000;
|
|
|
|
else if (INTEL_GEN(dev_priv) >= 5)
|
|
|
|
max_tmds_clock = 225000;
|
2013-07-22 23:02:39 +07:00
|
|
|
else
|
2017-10-30 21:57:02 +07:00
|
|
|
max_tmds_clock = 165000;
|
|
|
|
|
|
|
|
if (info->max_tmds_clock)
|
|
|
|
max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
|
|
|
|
|
|
|
|
return max_tmds_clock;
|
2013-07-22 23:02:39 +07:00
|
|
|
}
|
|
|
|
|
2016-05-03 02:08:23 +07:00
|
|
|
static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
|
2017-05-01 20:38:02 +07:00
|
|
|
bool respect_downstream_limits,
|
|
|
|
bool force_dvi)
|
2016-05-03 02:08:23 +07:00
|
|
|
{
|
2017-10-30 21:57:02 +07:00
|
|
|
struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
|
|
|
|
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
|
2016-05-03 02:08:23 +07:00
|
|
|
|
|
|
|
if (respect_downstream_limits) {
|
2016-09-28 20:51:43 +07:00
|
|
|
struct intel_connector *connector = hdmi->attached_connector;
|
|
|
|
const struct drm_display_info *info = &connector->base.display_info;
|
|
|
|
|
2016-05-03 02:08:23 +07:00
|
|
|
if (hdmi->dp_dual_mode.max_tmds_clock)
|
|
|
|
max_tmds_clock = min(max_tmds_clock,
|
|
|
|
hdmi->dp_dual_mode.max_tmds_clock);
|
2016-09-28 20:51:43 +07:00
|
|
|
|
|
|
|
if (info->max_tmds_clock)
|
|
|
|
max_tmds_clock = min(max_tmds_clock,
|
|
|
|
info->max_tmds_clock);
|
2017-05-01 20:38:02 +07:00
|
|
|
else if (!hdmi->has_hdmi_sink || force_dvi)
|
2016-05-03 02:08:23 +07:00
|
|
|
max_tmds_clock = min(max_tmds_clock, 165000);
|
|
|
|
}
|
|
|
|
|
|
|
|
return max_tmds_clock;
|
|
|
|
}
|
|
|
|
|
2015-06-30 23:23:59 +07:00
|
|
|
static enum drm_mode_status
|
|
|
|
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
|
2017-05-01 20:38:02 +07:00
|
|
|
int clock, bool respect_downstream_limits,
|
|
|
|
bool force_dvi)
|
2015-06-30 23:23:59 +07:00
|
|
|
{
|
2016-10-13 17:03:04 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
|
2015-06-30 23:23:59 +07:00
|
|
|
|
|
|
|
if (clock < 25000)
|
|
|
|
return MODE_CLOCK_LOW;
|
2017-05-01 20:38:02 +07:00
|
|
|
if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
|
2015-06-30 23:23:59 +07:00
|
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
|
2015-07-06 18:44:11 +07:00
|
|
|
/* BXT DPLL can't generate 223-240 MHz */
|
2016-12-02 15:23:49 +07:00
|
|
|
if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
|
2015-07-06 18:44:11 +07:00
|
|
|
return MODE_CLOCK_RANGE;
|
|
|
|
|
|
|
|
/* CHV DPLL can't generate 216-240 MHz */
|
2016-10-13 17:03:04 +07:00
|
|
|
if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
|
2015-06-30 23:23:59 +07:00
|
|
|
return MODE_CLOCK_RANGE;
|
|
|
|
|
|
|
|
return MODE_OK;
|
|
|
|
}
|
|
|
|
|
2013-11-28 22:29:18 +07:00
|
|
|
static enum drm_mode_status
|
|
|
|
intel_hdmi_mode_valid(struct drm_connector *connector,
|
|
|
|
struct drm_display_mode *mode)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2015-06-30 23:23:59 +07:00
|
|
|
struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
|
|
|
|
struct drm_device *dev = intel_hdmi_to_dev(hdmi);
|
2016-10-13 17:02:54 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-06-30 23:23:59 +07:00
|
|
|
enum drm_mode_status status;
|
|
|
|
int clock;
|
2016-02-02 20:16:39 +07:00
|
|
|
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
|
2017-05-01 20:38:02 +07:00
|
|
|
bool force_dvi =
|
|
|
|
READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
|
2015-06-30 23:23:59 +07:00
|
|
|
|
2018-05-24 19:54:03 +07:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
|
|
return MODE_NO_DBLESCAN;
|
|
|
|
|
2015-06-30 23:23:59 +07:00
|
|
|
clock = mode->clock;
|
2016-02-02 20:16:39 +07:00
|
|
|
|
|
|
|
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
|
|
|
|
clock *= 2;
|
|
|
|
|
|
|
|
if (clock > max_dotclk)
|
|
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
|
2014-09-03 07:03:36 +07:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
|
|
|
clock *= 2;
|
|
|
|
|
2017-07-24 20:49:32 +07:00
|
|
|
if (drm_mode_is_420_only(&connector->display_info, mode))
|
|
|
|
clock /= 2;
|
|
|
|
|
2015-06-30 23:23:59 +07:00
|
|
|
/* check if we can do 8bpc */
|
2017-05-01 20:38:02 +07:00
|
|
|
status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2018-05-22 07:25:51 +07:00
|
|
|
if (hdmi->has_hdmi_sink && !force_dvi) {
|
|
|
|
/* if we can't do 8bpc we may still be able to do 12bpc */
|
2019-02-05 05:25:38 +07:00
|
|
|
if (status != MODE_OK && !HAS_GMCH(dev_priv))
|
2018-05-22 07:25:51 +07:00
|
|
|
status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
|
|
|
|
true, force_dvi);
|
|
|
|
|
|
|
|
/* if we can't do 8,12bpc we may still be able to do 10bpc */
|
|
|
|
if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
|
|
|
|
status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
|
|
|
|
true, force_dvi);
|
|
|
|
}
|
2019-09-18 22:07:07 +07:00
|
|
|
if (status != MODE_OK)
|
|
|
|
return status;
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2019-09-18 22:07:07 +07:00
|
|
|
return intel_mode_valid_max_plane_size(dev_priv, mode);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2018-05-22 07:25:51 +07:00
|
|
|
static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
|
|
|
|
int bpc)
|
2014-03-03 21:15:29 +07:00
|
|
|
{
|
2017-02-14 00:58:18 +07:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
to_i915(crtc_state->base.crtc->dev);
|
|
|
|
struct drm_atomic_state *state = crtc_state->base.state;
|
|
|
|
struct drm_connector_state *connector_state;
|
|
|
|
struct drm_connector *connector;
|
2018-10-30 15:45:02 +07:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc_state->base.adjusted_mode;
|
2017-02-14 00:58:18 +07:00
|
|
|
int i;
|
2014-03-03 21:15:29 +07:00
|
|
|
|
2019-02-05 05:25:38 +07:00
|
|
|
if (HAS_GMCH(dev_priv))
|
2014-03-03 21:15:29 +07:00
|
|
|
return false;
|
|
|
|
|
2018-05-22 07:25:51 +07:00
|
|
|
if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
|
|
|
|
return false;
|
|
|
|
|
2019-05-08 01:18:56 +07:00
|
|
|
if (crtc_state->pipe_bpp < bpc * 3)
|
2017-10-26 22:14:04 +07:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!crtc_state->has_hdmi_sink)
|
|
|
|
return false;
|
|
|
|
|
2014-03-03 21:15:29 +07:00
|
|
|
/*
|
2018-05-22 07:25:51 +07:00
|
|
|
* HDMI deep color affects the clocks, so it's only possible
|
2014-03-03 21:15:29 +07:00
|
|
|
* when not cloning with other encoder types.
|
|
|
|
*/
|
2017-02-14 00:58:18 +07:00
|
|
|
if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
|
|
|
|
return false;
|
|
|
|
|
2017-07-12 15:13:34 +07:00
|
|
|
for_each_new_connector_in_state(state, connector, connector_state, i) {
|
2017-02-14 00:58:18 +07:00
|
|
|
const struct drm_display_info *info = &connector->display_info;
|
|
|
|
|
|
|
|
if (connector_state->crtc != crtc_state->base.crtc)
|
|
|
|
continue;
|
|
|
|
|
2018-10-12 13:23:08 +07:00
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
|
2017-07-21 22:25:04 +07:00
|
|
|
const struct drm_hdmi_info *hdmi = &info->hdmi;
|
|
|
|
|
2018-05-22 07:25:51 +07:00
|
|
|
if (bpc == 12 && !(hdmi->y420_dc_modes &
|
|
|
|
DRM_EDID_YCBCR420_DC_36))
|
|
|
|
return false;
|
|
|
|
else if (bpc == 10 && !(hdmi->y420_dc_modes &
|
|
|
|
DRM_EDID_YCBCR420_DC_30))
|
2017-07-21 22:25:04 +07:00
|
|
|
return false;
|
|
|
|
} else {
|
2018-05-22 07:25:51 +07:00
|
|
|
if (bpc == 12 && !(info->edid_hdmi_dc_modes &
|
|
|
|
DRM_EDID_HDMI_DC_36))
|
|
|
|
return false;
|
|
|
|
else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
|
|
|
|
DRM_EDID_HDMI_DC_30))
|
2017-07-21 22:25:04 +07:00
|
|
|
return false;
|
|
|
|
}
|
2017-02-14 00:58:18 +07:00
|
|
|
}
|
|
|
|
|
2017-12-06 02:01:18 +07:00
|
|
|
/* Display WA #1139: glk */
|
2018-05-22 07:25:51 +07:00
|
|
|
if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
|
2018-10-30 15:45:02 +07:00
|
|
|
adjusted_mode->htotal > 5460)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Display Wa_1405510057:icl */
|
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
|
2019-03-09 04:42:58 +07:00
|
|
|
bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
|
2018-10-30 15:45:02 +07:00
|
|
|
(adjusted_mode->crtc_hblank_end -
|
|
|
|
adjusted_mode->crtc_hblank_start) % 8 == 2)
|
2017-04-24 17:47:18 +07:00
|
|
|
return false;
|
|
|
|
|
2017-02-14 00:58:18 +07:00
|
|
|
return true;
|
2014-03-03 21:15:29 +07:00
|
|
|
}
|
|
|
|
|
2017-07-21 22:25:04 +07:00
|
|
|
static bool
|
|
|
|
intel_hdmi_ycbcr420_config(struct drm_connector *connector,
|
2019-08-29 01:34:24 +07:00
|
|
|
struct intel_crtc_state *config)
|
2017-07-21 22:25:04 +07:00
|
|
|
{
|
2017-07-21 22:25:05 +07:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
|
|
|
|
|
2017-07-21 22:25:04 +07:00
|
|
|
if (!connector->ycbcr_420_allowed) {
|
|
|
|
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-10-12 13:23:08 +07:00
|
|
|
config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
|
2017-07-21 22:25:05 +07:00
|
|
|
|
|
|
|
/* YCBCR 420 output conversion needs a scaler */
|
|
|
|
if (skl_update_scaler_crtc(config)) {
|
|
|
|
DRM_DEBUG_KMS("Scaler allocation for output failed\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_pch_panel_fitting(intel_crtc, config,
|
|
|
|
DRM_MODE_SCALE_FULLSCREEN);
|
|
|
|
|
2017-07-21 22:25:04 +07:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-08-29 01:34:24 +07:00
|
|
|
static int intel_hdmi_port_clock(int clock, int bpc)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Need to adjust the port link by:
|
|
|
|
* 1.5x for 12bpc
|
|
|
|
* 1.25x for 10bpc
|
|
|
|
*/
|
|
|
|
return clock * bpc / 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
int clock, bool force_dvi)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
int bpc;
|
|
|
|
|
|
|
|
for (bpc = 12; bpc >= 10; bpc -= 2) {
|
|
|
|
if (hdmi_deep_color_possible(crtc_state, bpc) &&
|
|
|
|
hdmi_port_clock_valid(intel_hdmi,
|
|
|
|
intel_hdmi_port_clock(clock, bpc),
|
|
|
|
true, force_dvi) == MODE_OK)
|
|
|
|
return bpc;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 8;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
bool force_dvi)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc_state->base.adjusted_mode;
|
|
|
|
int bpc, clock = adjusted_mode->crtc_clock;
|
|
|
|
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
|
|
|
clock *= 2;
|
|
|
|
|
|
|
|
/* YCBCR420 TMDS rate requirement is half the pixel clock */
|
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
|
|
|
|
clock /= 2;
|
|
|
|
|
|
|
|
bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
|
|
|
|
clock, force_dvi);
|
|
|
|
|
|
|
|
crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* pipe_bpp could already be below 8bpc due to
|
|
|
|
* FDI bandwidth constraints. We shouldn't bump it
|
|
|
|
* back up to 8bpc in that case.
|
|
|
|
*/
|
|
|
|
if (crtc_state->pipe_bpp > bpc * 3)
|
|
|
|
crtc_state->pipe_bpp = bpc * 3;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
|
|
|
|
bpc, crtc_state->pipe_bpp);
|
|
|
|
|
|
|
|
if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
|
|
|
|
false, force_dvi) != MODE_OK) {
|
|
|
|
DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
|
|
|
|
crtc_state->port_clock);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-07-18 21:50:45 +07:00
|
|
|
static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
const struct intel_digital_connector_state *intel_conn_state =
|
|
|
|
to_intel_digital_connector_state(conn_state);
|
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc_state->base.adjusted_mode;
|
|
|
|
|
2019-07-18 23:45:23 +07:00
|
|
|
/*
|
|
|
|
* Our YCbCr output is always limited range.
|
|
|
|
* crtc_state->limited_color_range only applies to RGB,
|
|
|
|
* and it must never be set for YCbCr or we risk setting
|
|
|
|
* some conflicting bits in PIPECONF which will mess up
|
|
|
|
* the colors on the monitor.
|
|
|
|
*/
|
|
|
|
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
|
|
|
|
return false;
|
|
|
|
|
2019-07-18 21:50:45 +07:00
|
|
|
if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
|
|
|
|
/* See CEA-861-E - 5.1 Default Encoding Parameters */
|
|
|
|
return crtc_state->has_hdmi_sink &&
|
|
|
|
drm_default_rgb_quant_range(adjusted_mode) ==
|
|
|
|
HDMI_QUANTIZATION_RANGE_LIMITED;
|
|
|
|
} else {
|
|
|
|
return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-01-16 03:08:00 +07:00
|
|
|
int intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2013-03-27 06:44:55 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2016-10-13 17:02:52 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-01-15 19:55:22 +07:00
|
|
|
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
|
2017-07-21 22:25:04 +07:00
|
|
|
struct drm_connector *connector = conn_state->connector;
|
|
|
|
struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
|
2017-05-01 20:38:02 +07:00
|
|
|
struct intel_digital_connector_state *intel_conn_state =
|
|
|
|
to_intel_digital_connector_state(conn_state);
|
|
|
|
bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
|
2019-08-29 01:34:24 +07:00
|
|
|
int ret;
|
2013-01-17 21:31:28 +07:00
|
|
|
|
2018-05-24 19:54:03 +07:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
2019-01-16 03:08:00 +07:00
|
|
|
return -EINVAL;
|
2018-05-24 19:54:03 +07:00
|
|
|
|
2018-10-12 13:23:07 +07:00
|
|
|
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
|
2017-05-01 20:38:02 +07:00
|
|
|
pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
|
2014-04-25 04:54:47 +07:00
|
|
|
|
2014-11-06 05:26:08 +07:00
|
|
|
if (pipe_config->has_hdmi_sink)
|
|
|
|
pipe_config->has_infoframe = true;
|
|
|
|
|
2019-08-29 01:34:24 +07:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
2014-09-03 07:03:36 +07:00
|
|
|
pipe_config->pixel_multiplier = 2;
|
|
|
|
|
2017-07-21 22:25:04 +07:00
|
|
|
if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
|
2019-08-29 01:34:24 +07:00
|
|
|
if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
|
2017-07-21 22:25:04 +07:00
|
|
|
DRM_ERROR("Can't support YCBCR420 output\n");
|
2019-01-16 03:08:00 +07:00
|
|
|
return -EINVAL;
|
2017-07-21 22:25:04 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-18 23:45:23 +07:00
|
|
|
pipe_config->limited_color_range =
|
|
|
|
intel_hdmi_limited_color_range(pipe_config, conn_state);
|
|
|
|
|
2016-10-13 17:02:52 +07:00
|
|
|
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
|
2013-03-27 06:44:55 +07:00
|
|
|
pipe_config->has_pch_encoder = true;
|
|
|
|
|
2017-05-01 20:38:02 +07:00
|
|
|
if (pipe_config->has_hdmi_sink) {
|
|
|
|
if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
|
|
|
|
pipe_config->has_audio = intel_hdmi->has_audio;
|
|
|
|
else
|
|
|
|
pipe_config->has_audio =
|
|
|
|
intel_conn_state->force_audio == HDMI_AUDIO_ON;
|
|
|
|
}
|
2014-04-25 04:54:52 +07:00
|
|
|
|
2019-08-29 01:34:24 +07:00
|
|
|
ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-04-19 16:24:33 +07:00
|
|
|
|
2015-09-08 17:40:48 +07:00
|
|
|
/* Set user selected PAR to incoming mode's member */
|
2017-05-01 20:37:53 +07:00
|
|
|
adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
|
2015-09-08 17:40:48 +07:00
|
|
|
|
2016-04-27 19:44:16 +07:00
|
|
|
pipe_config->lane_count = 4;
|
|
|
|
|
2017-11-16 01:42:05 +07:00
|
|
|
if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
|
|
|
|
IS_GEMINILAKE(dev_priv))) {
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
if (scdc->scrambling.low_rates)
|
|
|
|
pipe_config->hdmi_scrambling = true;
|
|
|
|
|
|
|
|
if (pipe_config->port_clock > 340000) {
|
|
|
|
pipe_config->hdmi_scrambling = true;
|
|
|
|
pipe_config->hdmi_high_tmds_clock_ratio = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-26 00:41:01 +07:00
|
|
|
intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
|
|
|
|
|
|
|
|
if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
|
|
|
|
DRM_DEBUG_KMS("bad AVI infoframe\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
|
|
|
|
DRM_DEBUG_KMS("bad SPD infoframe\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
|
|
|
|
DRM_DEBUG_KMS("bad HDMI infoframe\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-05-18 17:39:27 +07:00
|
|
|
if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
|
|
|
|
DRM_DEBUG_KMS("bad DRM infoframe\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-08-28 23:42:15 +07:00
|
|
|
intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
|
|
|
|
pipe_config->cpu_transcoder);
|
|
|
|
|
2019-01-16 03:08:00 +07:00
|
|
|
return 0;
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
static void
|
|
|
|
intel_hdmi_unset_edid(struct drm_connector *connector)
|
2009-04-02 12:13:26 +07:00
|
|
|
{
|
2010-09-09 22:20:55 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2009-04-02 12:13:26 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
intel_hdmi->has_hdmi_sink = false;
|
|
|
|
intel_hdmi->has_audio = false;
|
|
|
|
|
2016-05-03 02:08:23 +07:00
|
|
|
intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
|
|
|
|
intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
|
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
kfree(to_intel_connector(connector)->detect_edid);
|
|
|
|
to_intel_connector(connector)->detect_edid = NULL;
|
|
|
|
}
|
|
|
|
|
2016-05-03 02:08:23 +07:00
|
|
|
static void
|
2016-05-04 18:45:22 +07:00
|
|
|
intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
|
2016-05-03 02:08:23 +07:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->dev);
|
|
|
|
struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
|
2017-11-09 22:24:34 +07:00
|
|
|
enum port port = hdmi_to_dig_port(hdmi)->base.port;
|
2016-05-03 02:08:23 +07:00
|
|
|
struct i2c_adapter *adapter =
|
|
|
|
intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
|
|
|
|
enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
|
|
|
|
|
2016-05-04 18:45:22 +07:00
|
|
|
/*
|
|
|
|
* Type 1 DVI adaptors are not required to implement any
|
|
|
|
* registers, so we can't always detect their presence.
|
|
|
|
* Ideally we should be able to check the state of the
|
|
|
|
* CONFIG1 pin, but no such luck on our hardware.
|
|
|
|
*
|
|
|
|
* The only method left to us is to check the VBT to see
|
|
|
|
* if the port is a dual mode capable DP port. But let's
|
|
|
|
* only do that when we sucesfully read the EDID, to avoid
|
|
|
|
* confusing log messages about DP dual mode adaptors when
|
|
|
|
* there's nothing connected to the port.
|
|
|
|
*/
|
|
|
|
if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
|
2017-12-15 17:20:55 +07:00
|
|
|
/* An overridden EDID imply that we want this port for testing.
|
|
|
|
* Make sure not to set limits for that port.
|
|
|
|
*/
|
|
|
|
if (has_edid && !connector->override_edid &&
|
2016-05-04 18:45:22 +07:00
|
|
|
intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
|
|
|
|
DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
|
|
|
|
type = DRM_DP_DUAL_MODE_TYPE1_DVI;
|
|
|
|
} else {
|
|
|
|
type = DRM_DP_DUAL_MODE_NONE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (type == DRM_DP_DUAL_MODE_NONE)
|
2016-05-03 02:08:23 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
hdmi->dp_dual_mode.type = type;
|
|
|
|
hdmi->dp_dual_mode.max_tmds_clock =
|
|
|
|
drm_dp_dual_mode_max_tmds_clock(type, adapter);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
|
|
|
|
drm_dp_get_dual_mode_type_name(type),
|
|
|
|
hdmi->dp_dual_mode.max_tmds_clock);
|
|
|
|
}
|
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
static bool
|
2016-08-17 19:47:48 +07:00
|
|
|
intel_hdmi_set_edid(struct drm_connector *connector)
|
2014-09-03 02:04:01 +07:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->dev);
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_wakeref_t wakeref;
|
2016-08-17 19:47:48 +07:00
|
|
|
struct edid *edid;
|
2014-09-03 02:04:01 +07:00
|
|
|
bool connected = false;
|
2018-01-01 05:34:54 +07:00
|
|
|
struct i2c_adapter *i2c;
|
2013-07-21 02:27:08 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2018-01-01 05:34:54 +07:00
|
|
|
i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
|
|
|
|
|
|
|
|
edid = drm_get_edid(connector, i2c);
|
|
|
|
|
|
|
|
if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
|
|
|
|
DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
|
|
|
|
intel_gmbus_force_bit(i2c, true);
|
|
|
|
edid = drm_get_edid(connector, i2c);
|
|
|
|
intel_gmbus_force_bit(i2c, false);
|
|
|
|
}
|
drm/i915: hdmi detection according by reading edid
According to investigations from windows team ,hw team,
and our test results on all 4x platofrms available
(gm45, g45b, q45, g45a, g45c, g41a, and g41), we find
currently Hot plug live status and Hot plug interrupt
detection are not reliable, sometime the results from
the two approaches are contradicts. So we chose edid
detection for hdmi output.
Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16 16:23:09 +07:00
|
|
|
|
2016-08-17 19:47:48 +07:00
|
|
|
intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
|
2016-05-03 02:08:23 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
|
2009-06-05 14:38:43 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
to_intel_connector(connector)->detect_edid = edid;
|
|
|
|
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
|
|
|
|
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
|
2017-05-01 20:38:02 +07:00
|
|
|
intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
|
2014-09-03 02:04:01 +07:00
|
|
|
|
|
|
|
connected = true;
|
2010-09-19 15:29:33 +07:00
|
|
|
}
|
|
|
|
|
2018-07-04 22:08:17 +07:00
|
|
|
cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
|
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
return connected;
|
|
|
|
}
|
|
|
|
|
2015-10-09 02:50:57 +07:00
|
|
|
static enum drm_connector_status
|
|
|
|
intel_hdmi_detect(struct drm_connector *connector, bool force)
|
2014-09-03 02:04:01 +07:00
|
|
|
{
|
2018-08-02 00:34:41 +07:00
|
|
|
enum drm_connector_status status = connector_status_disconnected;
|
2015-10-09 02:50:57 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->dev);
|
2018-07-04 22:08:17 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2018-08-02 00:34:41 +07:00
|
|
|
struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_wakeref_t wakeref;
|
2014-09-03 02:04:01 +07:00
|
|
|
|
2015-10-09 02:50:57 +07:00
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
|
|
|
|
connector->base.id, connector->name);
|
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
2015-11-20 01:55:01 +07:00
|
|
|
|
2019-03-09 04:42:58 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 11 &&
|
2018-08-02 00:34:41 +07:00
|
|
|
!intel_digital_port_connected(encoder))
|
|
|
|
goto out;
|
|
|
|
|
2015-10-09 02:50:57 +07:00
|
|
|
intel_hdmi_unset_edid(connector);
|
drm/i915: Add hot_plug hook for hdmi encoder
This patch adds a separate probe function for HDMI
EDID read over DDC channel. This function has been
registered as a .hot_plug handler for HDMI encoder.
The current implementation of hdmi_detect()
function re-sets the cached HDMI edid (in connector->detect_edid) in
every detect call.This function gets called many times, sometimes
directly from userspace probes, forcing drivers to read EDID every
detect function call.This causes several problems like:
1. Race conditions in multiple hot_plug / unplug cases, between
interrupts bottom halves and userspace detections.
2. Many Un-necessary EDID reads for single hotplug/unplug
3. HDMI complaince failures which expects only one EDID read per hotplug
This function will be serving the purpose of really reading the EDID
by really probing the DDC channel, and updating the cached EDID.
The plan is to:
1. i915 IRQ handler bottom half function already calls
intel_encoder->hotplug() function. Adding This probe function which
will read the EDID only in case of a hotplug / unplug.
2. During init_connector this probe will be called to read the edid
3. Reuse the cached EDID in hdmi_detect() function.
The "< gen7" check is there because this was tested only for >=gen7
platforms. For older platforms the hotplug/reading edid path remains same.
v2: Calling set_edid instead of hdmi_probe during init.
Also, for platforms having DDI, intel_encoder for DP and HDMI is same
(taken from intel_dig_port), so for DP also, hot_plug function gets called
which is not intended here. So, check for HDMI in intel_hdmi_probe
Rely on HPD for updating edid only for platforms gen > 8 and also for VLV.
v3: Dropping the gen < 8 || !VLV check. Now all platforms should rely on
hotplug or init for updating the edid.(Daniel)
Also, calling hdmi_probe in init instead of set_edid
v4: Renaming intel_hdmi_probe to intel_hdmi_hot_plug.
Also calling this hotplug handler from intel_hpd_init to take care of init
resume scenarios.
v5: Moved the call to encoder hotplug during init to separate patch(Daniel)
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
[danvet: Mark intel_hdmi_hot_plug as static.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-05 18:13:15 +07:00
|
|
|
|
2017-10-28 02:31:24 +07:00
|
|
|
if (intel_hdmi_set_edid(connector))
|
2014-09-03 02:04:01 +07:00
|
|
|
status = connector_status_connected;
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2018-08-02 00:34:41 +07:00
|
|
|
out:
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
|
2015-11-20 01:55:01 +07:00
|
|
|
|
2018-07-04 22:08:17 +07:00
|
|
|
if (status != connector_status_connected)
|
|
|
|
cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
|
|
|
|
|
2019-10-29 01:15:17 +07:00
|
|
|
/*
|
|
|
|
* Make sure the refs for power wells enabled during detect are
|
|
|
|
* dropped to avoid a new detect cycle triggered by HPD polling.
|
|
|
|
*/
|
|
|
|
intel_display_power_flush_work(dev_priv);
|
|
|
|
|
drm/i915: hdmi detection according by reading edid
According to investigations from windows team ,hw team,
and our test results on all 4x platofrms available
(gm45, g45b, q45, g45a, g45c, g41a, and g41), we find
currently Hot plug live status and Hot plug interrupt
detection are not reliable, sometime the results from
the two approaches are contradicts. So we chose edid
detection for hdmi output.
Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-16 16:23:09 +07:00
|
|
|
return status;
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
static void
|
|
|
|
intel_hdmi_force(struct drm_connector *connector)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2014-09-03 02:04:01 +07:00
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
|
|
|
|
connector->base.id, connector->name);
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
intel_hdmi_unset_edid(connector);
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
if (connector->status != connector_status_connected)
|
|
|
|
return;
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2016-08-17 19:47:48 +07:00
|
|
|
intel_hdmi_set_edid(connector);
|
2014-09-03 02:04:01 +07:00
|
|
|
}
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
static int intel_hdmi_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct edid *edid;
|
|
|
|
|
|
|
|
edid = to_intel_connector(connector)->detect_edid;
|
|
|
|
if (edid == NULL)
|
|
|
|
return 0;
|
2014-03-05 21:20:53 +07:00
|
|
|
|
2014-09-03 02:04:01 +07:00
|
|
|
return intel_connector_update_modes(connector, edid);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2014-04-06 01:51:35 +07:00
|
|
|
{
|
2017-08-18 20:49:54 +07:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
enc_to_dig_port(&encoder->base);
|
2014-04-06 01:51:35 +07:00
|
|
|
|
2016-11-23 21:57:00 +07:00
|
|
|
intel_hdmi_prepare(encoder, pipe_config);
|
2014-04-25 04:54:56 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
intel_dig_port->set_infoframes(encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
pipe_config->has_infoframe,
|
|
|
|
pipe_config, conn_state);
|
2014-04-06 01:51:35 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2013-04-19 04:51:36 +07:00
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
2017-11-01 03:51:18 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-04-27 19:44:24 +07:00
|
|
|
|
2017-11-01 03:51:18 +07:00
|
|
|
vlv_phy_pre_encoder_enable(encoder, pipe_config);
|
2013-07-30 16:20:31 +07:00
|
|
|
|
2016-04-27 19:44:22 +07:00
|
|
|
/* HDMI 1.0V-2dB */
|
|
|
|
vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
|
|
|
|
0x2b247878);
|
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
dport->set_infoframes(encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
pipe_config->has_infoframe,
|
|
|
|
pipe_config, conn_state);
|
2014-04-06 01:51:35 +07:00
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
g4x_enable_hdmi(encoder, pipe_config, conn_state);
|
2013-07-30 16:20:31 +07:00
|
|
|
|
2015-04-10 22:21:31 +07:00
|
|
|
vlv_wait_port_ready(dev_priv, dport, 0x0);
|
2013-04-19 04:51:36 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2013-04-19 04:51:36 +07:00
|
|
|
{
|
2016-11-23 21:57:00 +07:00
|
|
|
intel_hdmi_prepare(encoder, pipe_config);
|
2014-04-25 04:54:56 +07:00
|
|
|
|
2017-11-01 03:51:18 +07:00
|
|
|
vlv_phy_pre_pll_enable(encoder, pipe_config);
|
2013-04-19 04:51:36 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2014-04-09 17:29:05 +07:00
|
|
|
{
|
2016-11-23 21:57:00 +07:00
|
|
|
intel_hdmi_prepare(encoder, pipe_config);
|
2014-06-28 06:04:02 +07:00
|
|
|
|
2017-11-01 03:51:18 +07:00
|
|
|
chv_phy_pre_pll_enable(encoder, pipe_config);
|
2014-04-09 17:29:05 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2015-07-09 03:45:49 +07:00
|
|
|
{
|
2017-11-01 03:51:18 +07:00
|
|
|
chv_phy_post_pll_disable(encoder, old_crtc_state);
|
2015-07-09 03:45:49 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2013-04-19 04:51:36 +07:00
|
|
|
{
|
|
|
|
/* Reset lanes to avoid HDMI flicker (VLV w/a) */
|
2017-11-01 03:51:18 +07:00
|
|
|
vlv_phy_reset_lanes(encoder, old_crtc_state);
|
2013-04-19 04:51:36 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void chv_hdmi_post_disable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2014-04-09 17:29:00 +07:00
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2014-04-09 17:29:00 +07:00
|
|
|
|
2019-04-26 15:17:19 +07:00
|
|
|
vlv_dpio_get(dev_priv);
|
2014-04-09 17:29:00 +07:00
|
|
|
|
2015-07-10 00:14:11 +07:00
|
|
|
/* Assert data lane reset */
|
2017-11-01 03:51:18 +07:00
|
|
|
chv_data_lane_soft_reset(encoder, old_crtc_state, true);
|
2014-04-09 17:29:00 +07:00
|
|
|
|
2019-04-26 15:17:19 +07:00
|
|
|
vlv_dpio_put(dev_priv);
|
2014-04-09 17:29:00 +07:00
|
|
|
}
|
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *pipe_config,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2014-04-09 17:28:20 +07:00
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-04-10 22:21:27 +07:00
|
|
|
|
2017-11-01 03:51:18 +07:00
|
|
|
chv_phy_pre_encoder_enable(encoder, pipe_config);
|
2014-08-18 18:42:45 +07:00
|
|
|
|
2014-04-09 17:28:20 +07:00
|
|
|
/* FIXME: Program the support xxx V-dB */
|
|
|
|
/* Use 800mV-0dB */
|
2016-04-27 19:44:17 +07:00
|
|
|
chv_set_phy_signal_level(encoder, 128, 102, false);
|
2014-04-09 17:28:20 +07:00
|
|
|
|
2018-09-21 01:51:36 +07:00
|
|
|
dport->set_infoframes(encoder,
|
2017-08-18 20:49:54 +07:00
|
|
|
pipe_config->has_infoframe,
|
|
|
|
pipe_config, conn_state);
|
2014-11-22 02:13:02 +07:00
|
|
|
|
2016-08-09 22:04:04 +07:00
|
|
|
g4x_enable_hdmi(encoder, pipe_config, conn_state);
|
2014-04-09 17:28:20 +07:00
|
|
|
|
2015-04-10 22:21:31 +07:00
|
|
|
vlv_wait_port_ready(dev_priv, dport, 0x0);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 03:45:55 +07:00
|
|
|
|
|
|
|
/* Second common lane will stay alive on its own now */
|
2016-04-27 19:44:20 +07:00
|
|
|
chv_phy_release_cl2_override(encoder);
|
2014-04-09 17:28:20 +07:00
|
|
|
}
|
|
|
|
|
2019-05-20 22:06:42 +07:00
|
|
|
static struct i2c_adapter *
|
|
|
|
intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->dev);
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
|
|
|
|
|
|
return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
|
|
|
|
struct kobject *i2c_kobj = &adapter->dev.kobj;
|
|
|
|
struct kobject *connector_kobj = &connector->kdev->kobj;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
|
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
|
|
|
|
struct kobject *i2c_kobj = &adapter->dev.kobj;
|
|
|
|
struct kobject *connector_kobj = &connector->kdev->kobj;
|
|
|
|
|
|
|
|
sysfs_remove_link(connector_kobj, i2c_kobj->name);
|
|
|
|
}
|
|
|
|
|
2018-10-23 16:22:29 +07:00
|
|
|
static int
|
|
|
|
intel_hdmi_connector_register(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = intel_connector_register(connector);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
i915_debugfs_connector_add(connector);
|
|
|
|
|
2019-05-20 22:06:42 +07:00
|
|
|
intel_hdmi_create_i2c_symlink(connector);
|
|
|
|
|
2018-10-23 16:22:29 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-01-03 04:33:00 +07:00
|
|
|
static void intel_hdmi_destroy(struct drm_connector *connector)
|
|
|
|
{
|
2019-08-14 17:45:00 +07:00
|
|
|
struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier;
|
|
|
|
|
|
|
|
cec_notifier_conn_unregister(n);
|
2018-10-09 21:11:03 +07:00
|
|
|
|
|
|
|
intel_connector_destroy(connector);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|
|
|
|
|
2019-05-20 22:06:42 +07:00
|
|
|
static void intel_hdmi_connector_unregister(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
intel_hdmi_remove_i2c_symlink(connector);
|
|
|
|
|
|
|
|
intel_connector_unregister(connector);
|
|
|
|
}
|
|
|
|
|
2009-01-03 04:33:00 +07:00
|
|
|
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
|
|
|
|
.detect = intel_hdmi_detect,
|
2014-09-03 02:04:01 +07:00
|
|
|
.force = intel_hdmi_force,
|
2009-01-03 04:33:00 +07:00
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
2017-05-01 20:38:02 +07:00
|
|
|
.atomic_get_property = intel_digital_connector_atomic_get_property,
|
|
|
|
.atomic_set_property = intel_digital_connector_atomic_set_property,
|
2018-10-23 16:22:29 +07:00
|
|
|
.late_register = intel_hdmi_connector_register,
|
2019-05-20 22:06:42 +07:00
|
|
|
.early_unregister = intel_hdmi_connector_unregister,
|
2009-01-03 04:33:00 +07:00
|
|
|
.destroy = intel_hdmi_destroy,
|
2015-01-23 07:50:32 +07:00
|
|
|
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
|
2017-05-01 20:38:02 +07:00
|
|
|
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
|
2009-01-03 04:33:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
|
|
|
|
.get_modes = intel_hdmi_get_modes,
|
|
|
|
.mode_valid = intel_hdmi_mode_valid,
|
2017-05-01 20:38:02 +07:00
|
|
|
.atomic_check = intel_digital_connector_atomic_check,
|
2009-01-03 04:33:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
|
2010-08-04 19:50:23 +07:00
|
|
|
.destroy = intel_encoder_destroy,
|
2009-01-03 04:33:00 +07:00
|
|
|
};
|
|
|
|
|
2010-09-19 15:29:33 +07:00
|
|
|
static void
|
|
|
|
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
|
|
|
|
{
|
2018-10-23 08:44:00 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(connector->dev);
|
2019-02-20 00:13:01 +07:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
hdmi_to_dig_port(intel_hdmi);
|
2018-10-23 08:44:00 +07:00
|
|
|
|
2011-05-13 04:17:24 +07:00
|
|
|
intel_attach_force_audio_property(connector);
|
2011-02-22 05:23:52 +07:00
|
|
|
intel_attach_broadcast_rgb_property(connector);
|
2014-06-11 12:36:01 +07:00
|
|
|
intel_attach_aspect_ratio_property(connector);
|
2019-02-20 00:13:01 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach Colorspace property for Non LSPCON based device
|
|
|
|
* ToDo: This needs to be extended for LSPCON implementation
|
|
|
|
* as well. Will be implemented separately.
|
|
|
|
*/
|
|
|
|
if (!intel_dig_port->lspcon.active)
|
|
|
|
intel_attach_colorspace_property(connector);
|
|
|
|
|
2018-05-15 20:59:28 +07:00
|
|
|
drm_connector_attach_content_type_property(connector);
|
2017-05-01 20:37:53 +07:00
|
|
|
connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
|
2018-10-23 08:44:00 +07:00
|
|
|
|
2019-05-17 23:19:09 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
|
|
|
drm_object_attach_property(&connector->base,
|
|
|
|
connector->dev->mode_config.hdr_output_metadata_property, 0);
|
|
|
|
|
2019-02-05 05:25:38 +07:00
|
|
|
if (!HAS_GMCH(dev_priv))
|
2018-10-23 08:44:00 +07:00
|
|
|
drm_connector_attach_max_bpc_property(connector, 8, 12);
|
2010-09-19 15:29:33 +07:00
|
|
|
}
|
|
|
|
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
/*
|
|
|
|
* intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
|
|
|
|
* @encoder: intel_encoder
|
|
|
|
* @connector: drm_connector
|
|
|
|
* @high_tmds_clock_ratio = bool to indicate if the function needs to set
|
|
|
|
* or reset the high tmds clock ratio for scrambling
|
|
|
|
* @scrambling: bool to Indicate if the function needs to set or reset
|
|
|
|
* sink scrambling
|
|
|
|
*
|
|
|
|
* This function handles scrambling on HDMI 2.0 capable sinks.
|
|
|
|
* If required clock rate is > 340 Mhz && scrambling is supported by sink
|
|
|
|
* it enables scrambling. This should be called before enabling the HDMI
|
|
|
|
* 2.0 port, as the sink can choose to disable the scrambling if it doesn't
|
|
|
|
* detect a scrambled clock within 100 ms.
|
2018-03-22 22:47:07 +07:00
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* True on success, false on failure.
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
*/
|
2018-03-22 22:47:07 +07:00
|
|
|
bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
struct drm_connector *connector,
|
|
|
|
bool high_tmds_clock_ratio,
|
|
|
|
bool scrambling)
|
|
|
|
{
|
2018-03-22 22:47:07 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
struct drm_scrambling *sink_scrambling =
|
2018-03-22 22:47:07 +07:00
|
|
|
&connector->display_info.hdmi.scdc.scrambling;
|
|
|
|
struct i2c_adapter *adapter =
|
|
|
|
intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
|
|
|
|
if (!sink_scrambling->supported)
|
2018-03-22 22:47:07 +07:00
|
|
|
return true;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
|
2018-03-22 22:47:07 +07:00
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
|
|
|
|
connector->base.id, connector->name,
|
|
|
|
yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
|
2018-03-22 22:47:07 +07:00
|
|
|
/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
|
|
|
|
return drm_scdc_set_high_tmds_clock_ratio(adapter,
|
|
|
|
high_tmds_clock_ratio) &&
|
|
|
|
drm_scdc_set_scrambling(adapter, scrambling);
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
}
|
|
|
|
|
2017-08-17 06:45:14 +07:00
|
|
|
static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
|
2016-10-12 00:52:46 +07:00
|
|
|
{
|
|
|
|
u8 ddc_pin;
|
|
|
|
|
2017-08-17 06:45:14 +07:00
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
|
|
|
ddc_pin = GMBUS_PIN_DPB;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
ddc_pin = GMBUS_PIN_DPC;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
ddc_pin = GMBUS_PIN_DPD_CHV;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(port);
|
|
|
|
ddc_pin = GMBUS_PIN_DPB;
|
|
|
|
break;
|
2016-10-12 00:52:46 +07:00
|
|
|
}
|
2017-08-17 06:45:14 +07:00
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
|
|
|
|
{
|
|
|
|
u8 ddc_pin;
|
2016-10-12 00:52:46 +07:00
|
|
|
|
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
2017-08-17 06:45:14 +07:00
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
2016-10-12 00:52:46 +07:00
|
|
|
break;
|
|
|
|
case PORT_C:
|
2017-08-17 06:45:14 +07:00
|
|
|
ddc_pin = GMBUS_PIN_2_BXT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(port);
|
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
u8 ddc_pin;
|
|
|
|
|
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
ddc_pin = GMBUS_PIN_2_BXT;
|
2016-10-12 00:52:46 +07:00
|
|
|
break;
|
|
|
|
case PORT_D:
|
2017-08-17 06:45:14 +07:00
|
|
|
ddc_pin = GMBUS_PIN_4_CNP;
|
|
|
|
break;
|
2018-01-30 06:22:19 +07:00
|
|
|
case PORT_F:
|
|
|
|
ddc_pin = GMBUS_PIN_3_BXT;
|
|
|
|
break;
|
2017-08-17 06:45:14 +07:00
|
|
|
default:
|
|
|
|
MISSING_CASE(port);
|
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
2018-01-12 01:00:09 +07:00
|
|
|
static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
|
|
|
|
{
|
2019-07-12 00:31:12 +07:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, port);
|
2018-01-12 01:00:09 +07:00
|
|
|
|
2019-07-12 00:31:12 +07:00
|
|
|
if (intel_phy_is_combo(dev_priv, phy))
|
|
|
|
return GMBUS_PIN_1_BXT + port;
|
|
|
|
else if (intel_phy_is_tc(dev_priv, phy))
|
|
|
|
return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
|
|
|
|
|
|
|
|
WARN(1, "Unknown port:%c\n", port_name(port));
|
|
|
|
return GMBUS_PIN_2_BXT;
|
2018-01-12 01:00:09 +07:00
|
|
|
}
|
|
|
|
|
2019-06-15 07:42:10 +07:00
|
|
|
static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
|
|
|
|
{
|
2019-07-13 05:16:41 +07:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, port);
|
2019-06-15 07:42:10 +07:00
|
|
|
u8 ddc_pin;
|
|
|
|
|
2019-07-13 05:16:41 +07:00
|
|
|
switch (phy) {
|
|
|
|
case PHY_A:
|
2019-06-15 07:42:10 +07:00
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
|
|
|
break;
|
2019-07-13 05:16:41 +07:00
|
|
|
case PHY_B:
|
2019-06-15 07:42:10 +07:00
|
|
|
ddc_pin = GMBUS_PIN_2_BXT;
|
|
|
|
break;
|
2019-07-13 05:16:41 +07:00
|
|
|
case PHY_C:
|
2019-06-15 07:42:10 +07:00
|
|
|
ddc_pin = GMBUS_PIN_9_TC1_ICP;
|
|
|
|
break;
|
|
|
|
default:
|
2019-07-13 05:16:41 +07:00
|
|
|
MISSING_CASE(phy);
|
2019-06-15 07:42:10 +07:00
|
|
|
ddc_pin = GMBUS_PIN_1_BXT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
2017-08-17 06:45:14 +07:00
|
|
|
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
u8 ddc_pin;
|
|
|
|
|
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
|
|
|
ddc_pin = GMBUS_PIN_DPB;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
ddc_pin = GMBUS_PIN_DPC;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
ddc_pin = GMBUS_PIN_DPD;
|
2016-10-12 00:52:46 +07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(port);
|
|
|
|
ddc_pin = GMBUS_PIN_DPB;
|
|
|
|
break;
|
|
|
|
}
|
2017-08-17 06:45:14 +07:00
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
const struct ddi_vbt_port_info *info =
|
|
|
|
&dev_priv->vbt.ddi_port_info[port];
|
|
|
|
u8 ddc_pin;
|
|
|
|
|
|
|
|
if (info->alternate_ddc_pin) {
|
|
|
|
DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
|
|
|
|
info->alternate_ddc_pin, port_name(port));
|
|
|
|
return info->alternate_ddc_pin;
|
|
|
|
}
|
|
|
|
|
2019-06-15 07:42:10 +07:00
|
|
|
if (HAS_PCH_MCC(dev_priv))
|
|
|
|
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
|
2019-09-19 06:56:25 +07:00
|
|
|
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
|
2019-02-22 04:44:30 +07:00
|
|
|
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
|
2017-08-17 06:45:14 +07:00
|
|
|
else if (HAS_PCH_CNP(dev_priv))
|
|
|
|
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
|
2019-02-22 04:44:30 +07:00
|
|
|
else if (IS_GEN9_LP(dev_priv))
|
|
|
|
ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
|
|
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
|
|
|
ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
|
2017-08-17 06:45:14 +07:00
|
|
|
else
|
|
|
|
ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
|
2016-10-12 00:52:46 +07:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
|
|
|
|
ddc_pin, port_name(port));
|
|
|
|
|
|
|
|
return ddc_pin;
|
|
|
|
}
|
|
|
|
|
2017-08-18 20:49:55 +07:00
|
|
|
void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
to_i915(intel_dig_port->base.base.dev);
|
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
intel_dig_port->write_infoframe = vlv_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = vlv_read_infoframe;
|
2017-08-18 20:49:55 +07:00
|
|
|
intel_dig_port->set_infoframes = vlv_set_infoframes;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
|
2017-08-18 20:49:55 +07:00
|
|
|
} else if (IS_G4X(dev_priv)) {
|
|
|
|
intel_dig_port->write_infoframe = g4x_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = g4x_read_infoframe;
|
2017-08-18 20:49:55 +07:00
|
|
|
intel_dig_port->set_infoframes = g4x_set_infoframes;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
|
2017-08-18 20:49:55 +07:00
|
|
|
} else if (HAS_DDI(dev_priv)) {
|
2018-10-12 13:23:11 +07:00
|
|
|
if (intel_dig_port->lspcon.active) {
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->write_infoframe = lspcon_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = lspcon_read_infoframe;
|
2018-10-12 13:23:11 +07:00
|
|
|
intel_dig_port->set_infoframes = lspcon_set_infoframes;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
|
2018-10-12 13:23:11 +07:00
|
|
|
} else {
|
|
|
|
intel_dig_port->write_infoframe = hsw_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = hsw_read_infoframe;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->set_infoframes = hsw_set_infoframes;
|
|
|
|
intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
|
2018-10-12 13:23:11 +07:00
|
|
|
}
|
2017-08-18 20:49:55 +07:00
|
|
|
} else if (HAS_PCH_IBX(dev_priv)) {
|
|
|
|
intel_dig_port->write_infoframe = ibx_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = ibx_read_infoframe;
|
2017-08-18 20:49:55 +07:00
|
|
|
intel_dig_port->set_infoframes = ibx_set_infoframes;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
|
2017-08-18 20:49:55 +07:00
|
|
|
} else {
|
|
|
|
intel_dig_port->write_infoframe = cpt_write_infoframe;
|
2019-02-26 00:41:02 +07:00
|
|
|
intel_dig_port->read_infoframe = cpt_read_infoframe;
|
2017-08-18 20:49:55 +07:00
|
|
|
intel_dig_port->set_infoframes = cpt_set_infoframes;
|
2019-02-26 00:40:59 +07:00
|
|
|
intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
|
2017-08-18 20:49:55 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:52 +07:00
|
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector)
|
2009-01-03 04:33:00 +07:00
|
|
|
{
|
2012-10-27 04:05:47 +07:00
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2017-11-09 22:24:34 +07:00
|
|
|
enum port port = intel_encoder->port;
|
2019-08-14 17:45:00 +07:00
|
|
|
struct cec_connector_info conn_info;
|
2010-09-15 18:03:59 +07:00
|
|
|
|
2019-08-31 01:27:19 +07:00
|
|
|
DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
|
|
|
|
intel_encoder->base.base.id, intel_encoder->base.name);
|
2016-06-03 16:17:43 +07:00
|
|
|
|
2015-12-09 00:59:38 +07:00
|
|
|
if (WARN(intel_dig_port->max_lanes < 4,
|
2019-08-31 01:27:19 +07:00
|
|
|
"Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
|
|
|
|
intel_dig_port->max_lanes, intel_encoder->base.base.id,
|
|
|
|
intel_encoder->base.name))
|
2015-12-09 00:59:38 +07:00
|
|
|
return;
|
|
|
|
|
2009-01-03 04:33:00 +07:00
|
|
|
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
|
2009-09-24 02:08:29 +07:00
|
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
2009-01-03 04:33:00 +07:00
|
|
|
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
|
|
|
|
|
2012-01-28 20:49:26 +07:00
|
|
|
connector->interlace_allowed = 1;
|
2009-01-03 04:33:00 +07:00
|
|
|
connector->doublescan_allowed = 0;
|
2013-09-25 22:45:40 +07:00
|
|
|
connector->stereo_allowed = 1;
|
2012-07-13 01:08:18 +07:00
|
|
|
|
2017-11-16 01:42:05 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
2017-07-21 22:25:09 +07:00
|
|
|
connector->ycbcr_420_allowed = true;
|
|
|
|
|
2016-10-12 00:52:46 +07:00
|
|
|
intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
|
|
|
|
|
2017-08-12 01:26:50 +07:00
|
|
|
if (WARN_ON(port == PORT_A))
|
2016-10-12 00:52:46 +07:00
|
|
|
return;
|
2018-01-30 06:22:21 +07:00
|
|
|
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2016-10-13 17:02:52 +07:00
|
|
|
if (HAS_DDI(dev_priv))
|
2012-10-27 04:05:51 +07:00
|
|
|
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
|
|
|
|
else
|
|
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
2012-10-27 04:05:47 +07:00
|
|
|
|
|
|
|
intel_hdmi_add_properties(intel_hdmi, connector);
|
|
|
|
|
2019-02-17 00:36:50 +07:00
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
|
|
intel_hdmi->attached_connector = intel_connector;
|
|
|
|
|
2018-01-18 12:48:05 +07:00
|
|
|
if (is_hdcp_supported(dev_priv, port)) {
|
2018-01-09 02:55:42 +07:00
|
|
|
int ret = intel_hdcp_init(intel_connector,
|
|
|
|
&intel_hdmi_hdcp_shim);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:47 +07:00
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
|
|
* generated on the port when a cable is not attached.
|
|
|
|
*/
|
2018-06-15 01:05:00 +07:00
|
|
|
if (IS_G45(dev_priv)) {
|
2012-10-27 04:05:47 +07:00
|
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
|
|
}
|
2018-07-04 22:08:17 +07:00
|
|
|
|
2019-08-14 17:45:00 +07:00
|
|
|
cec_fill_conn_info_from_drm(&conn_info, connector);
|
|
|
|
|
|
|
|
intel_hdmi->cec_notifier =
|
|
|
|
cec_notifier_conn_register(dev->dev, port_identifier(port),
|
|
|
|
&conn_info);
|
2018-07-04 22:08:17 +07:00
|
|
|
if (!intel_hdmi->cec_notifier)
|
|
|
|
DRM_DEBUG_KMS("CEC notifier get failed\n");
|
2012-10-27 04:05:47 +07:00
|
|
|
}
|
|
|
|
|
2019-07-12 07:53:43 +07:00
|
|
|
static enum intel_hotplug_state
|
|
|
|
intel_hdmi_hotplug(struct intel_encoder *encoder,
|
|
|
|
struct intel_connector *connector, bool irq_received)
|
|
|
|
{
|
|
|
|
enum intel_hotplug_state state;
|
|
|
|
|
|
|
|
state = intel_encoder_hotplug(encoder, connector, irq_received);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On many platforms the HDMI live state signal is known to be
|
|
|
|
* unreliable, so we can't use it to detect if a sink is connected or
|
|
|
|
* not. Instead we detect if it's connected based on whether we can
|
|
|
|
* read the EDID or not. That in turn has a problem during disconnect,
|
|
|
|
* since the HPD interrupt may be raised before the DDC lines get
|
|
|
|
* disconnected (due to how the required length of DDC vs. HPD
|
|
|
|
* connector pins are specified) and so we'll still be able to get a
|
|
|
|
* valid EDID. To solve this schedule another detection cycle if this
|
|
|
|
* time around we didn't detect any change in the sink's connection
|
|
|
|
* status.
|
|
|
|
*/
|
|
|
|
if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
|
|
|
|
state = INTEL_HOTPLUG_RETRY;
|
|
|
|
|
|
|
|
return state;
|
|
|
|
}
|
|
|
|
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_hdmi_init(struct drm_i915_private *dev_priv,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t hdmi_reg, enum port port)
|
2012-10-27 04:05:47 +07:00
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
|
2013-09-19 17:18:32 +07:00
|
|
|
intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
|
2012-10-27 04:05:47 +07:00
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
2015-04-10 14:59:10 +07:00
|
|
|
intel_connector = intel_connector_alloc();
|
2012-10-27 04:05:47 +07:00
|
|
|
if (!intel_connector) {
|
|
|
|
kfree(intel_dig_port);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
|
2016-11-23 21:21:44 +07:00
|
|
|
drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
|
|
|
|
&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
|
|
|
|
"HDMI %c", port_name(port));
|
2012-10-27 04:05:52 +07:00
|
|
|
|
2019-07-12 07:53:43 +07:00
|
|
|
intel_encoder->hotplug = intel_hdmi_hotplug;
|
2013-03-27 06:44:55 +07:00
|
|
|
intel_encoder->compute_config = intel_hdmi_compute_config;
|
2016-10-13 17:02:53 +07:00
|
|
|
if (HAS_PCH_SPLIT(dev_priv)) {
|
2015-05-05 21:17:35 +07:00
|
|
|
intel_encoder->disable = pch_disable_hdmi;
|
|
|
|
intel_encoder->post_disable = pch_post_disable_hdmi;
|
|
|
|
} else {
|
|
|
|
intel_encoder->disable = g4x_disable_hdmi;
|
|
|
|
}
|
2012-10-27 04:05:52 +07:00
|
|
|
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
|
2013-05-15 07:08:26 +07:00
|
|
|
intel_encoder->get_config = intel_hdmi_get_config;
|
2016-10-14 16:13:44 +07:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
2014-04-09 17:29:05 +07:00
|
|
|
intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
|
2014-04-09 17:28:20 +07:00
|
|
|
intel_encoder->pre_enable = chv_hdmi_pre_enable;
|
|
|
|
intel_encoder->enable = vlv_enable_hdmi;
|
2014-04-09 17:29:00 +07:00
|
|
|
intel_encoder->post_disable = chv_hdmi_post_disable;
|
2015-07-09 03:45:49 +07:00
|
|
|
intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
|
2016-10-13 17:03:08 +07:00
|
|
|
} else if (IS_VALLEYVIEW(dev_priv)) {
|
2013-10-16 16:07:41 +07:00
|
|
|
intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
|
|
|
|
intel_encoder->pre_enable = vlv_hdmi_pre_enable;
|
2013-07-30 16:20:31 +07:00
|
|
|
intel_encoder->enable = vlv_enable_hdmi;
|
2013-10-16 16:07:41 +07:00
|
|
|
intel_encoder->post_disable = vlv_hdmi_post_disable;
|
2013-07-30 16:20:31 +07:00
|
|
|
} else {
|
2014-04-06 01:51:35 +07:00
|
|
|
intel_encoder->pre_enable = intel_hdmi_pre_enable;
|
2016-10-13 17:02:53 +07:00
|
|
|
if (HAS_PCH_CPT(dev_priv))
|
2015-05-05 21:06:19 +07:00
|
|
|
intel_encoder->enable = cpt_enable_hdmi;
|
2016-10-13 17:02:53 +07:00
|
|
|
else if (HAS_PCH_IBX(dev_priv))
|
2015-05-05 21:06:23 +07:00
|
|
|
intel_encoder->enable = ibx_enable_hdmi;
|
2015-05-05 21:06:19 +07:00
|
|
|
else
|
2015-05-05 21:06:23 +07:00
|
|
|
intel_encoder->enable = g4x_enable_hdmi;
|
2013-04-19 04:51:36 +07:00
|
|
|
}
|
2012-06-30 13:59:56 +07:00
|
|
|
|
2012-10-27 04:05:47 +07:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
2017-02-22 13:34:27 +07:00
|
|
|
intel_encoder->power_domain = intel_port_to_power_domain(port);
|
2016-09-20 08:24:38 +07:00
|
|
|
intel_encoder->port = port;
|
2016-10-14 16:13:44 +07:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
2014-04-28 18:07:43 +07:00
|
|
|
if (port == PORT_D)
|
2019-10-02 23:25:02 +07:00
|
|
|
intel_encoder->pipe_mask = BIT(PIPE_C);
|
2014-04-28 18:07:43 +07:00
|
|
|
else
|
2019-10-02 23:25:02 +07:00
|
|
|
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
|
2014-04-28 18:07:43 +07:00
|
|
|
} else {
|
2019-10-02 23:25:02 +07:00
|
|
|
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
|
2014-04-28 18:07:43 +07:00
|
|
|
}
|
2014-03-03 21:15:30 +07:00
|
|
|
intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
|
2014-03-03 21:15:31 +07:00
|
|
|
/*
|
|
|
|
* BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
|
|
|
|
* to work on real hardware. And since g4x can send infoframes to
|
|
|
|
* only one port anyway, nothing is lost by allowing it.
|
|
|
|
*/
|
2016-10-13 17:03:06 +07:00
|
|
|
if (IS_G4X(dev_priv))
|
2014-03-03 21:15:31 +07:00
|
|
|
intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
|
2009-01-03 04:33:00 +07:00
|
|
|
|
2013-02-19 05:00:26 +07:00
|
|
|
intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
|
2015-12-09 00:59:38 +07:00
|
|
|
intel_dig_port->max_lanes = 4;
|
2010-09-19 15:29:33 +07:00
|
|
|
|
2017-08-18 20:49:55 +07:00
|
|
|
intel_infoframe_init(intel_dig_port);
|
|
|
|
|
2018-11-15 17:52:35 +07:00
|
|
|
intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
|
2012-10-27 04:05:47 +07:00
|
|
|
intel_hdmi_init_connector(intel_dig_port, intel_connector);
|
2009-01-03 04:33:00 +07:00
|
|
|
}
|