2005-04-17 05:20:36 +07:00
|
|
|
#ifndef __ASM_SH_PCI_H
|
|
|
|
#define __ASM_SH_PCI_H
|
|
|
|
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
|
|
|
|
/* Can be used to override the logic in pci_scan_bus for skipping
|
|
|
|
already-configured bus numbers - to be used for buggy BIOSes
|
|
|
|
or architectures with incomplete PCI setup by the loader */
|
|
|
|
|
|
|
|
#define pcibios_assign_all_busses() 1
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A board can define one or more PCI channels that represent built-in (or
|
|
|
|
* external) PCI controllers.
|
|
|
|
*/
|
|
|
|
struct pci_channel {
|
2009-04-20 16:29:22 +07:00
|
|
|
struct pci_channel *next;
|
2010-01-29 20:38:13 +07:00
|
|
|
struct pci_bus *bus;
|
2009-04-20 16:29:22 +07:00
|
|
|
|
|
|
|
struct pci_ops *pci_ops;
|
2010-02-01 18:01:50 +07:00
|
|
|
|
|
|
|
struct resource *resources;
|
|
|
|
unsigned int nr_resources;
|
2009-04-20 16:29:22 +07:00
|
|
|
|
2009-04-20 16:42:00 +07:00
|
|
|
unsigned long io_offset;
|
|
|
|
unsigned long mem_offset;
|
|
|
|
|
2009-04-20 16:29:22 +07:00
|
|
|
unsigned long reg_base;
|
|
|
|
unsigned long io_map_base;
|
2010-01-29 20:38:13 +07:00
|
|
|
|
|
|
|
unsigned int index;
|
|
|
|
unsigned int need_domain_info;
|
2010-02-01 14:39:46 +07:00
|
|
|
|
|
|
|
/* Optional error handling */
|
|
|
|
struct timer_list err_timer, serr_timer;
|
|
|
|
unsigned int err_irq, serr_irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2010-02-01 14:39:46 +07:00
|
|
|
/* arch/sh/drivers/pci/pci.c */
|
2010-09-20 16:56:13 +07:00
|
|
|
extern raw_spinlock_t pci_config_lock;
|
|
|
|
|
2010-02-01 11:11:25 +07:00
|
|
|
extern int register_pci_controller(struct pci_channel *hose);
|
2010-02-01 14:39:46 +07:00
|
|
|
extern void pcibios_report_status(unsigned int status_mask, int warn);
|
|
|
|
|
|
|
|
/* arch/sh/drivers/pci/common.c */
|
2010-02-03 14:46:20 +07:00
|
|
|
extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u8 *value);
|
|
|
|
extern int early_read_config_word(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u16 *value);
|
|
|
|
extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u32 *value);
|
|
|
|
extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u8 value);
|
|
|
|
extern int early_write_config_word(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u16 value);
|
|
|
|
extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
|
|
|
|
int bus, int devfn, int offset, u32 value);
|
2010-02-01 14:39:46 +07:00
|
|
|
extern void pcibios_enable_timers(struct pci_channel *hose);
|
|
|
|
extern unsigned int pcibios_handle_status_errors(unsigned long addr,
|
|
|
|
unsigned int status, struct pci_channel *hose);
|
2010-02-01 11:01:42 +07:00
|
|
|
extern int pci_is_66mhz_capable(struct pci_channel *hose,
|
|
|
|
int top_bus, int current_bus);
|
2009-04-20 16:29:22 +07:00
|
|
|
|
2009-04-20 14:14:29 +07:00
|
|
|
extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
struct pci_dev;
|
|
|
|
|
2009-04-20 13:51:45 +07:00
|
|
|
#define HAVE_PCI_MMAP
|
|
|
|
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
|
|
enum pci_mmap_state mmap_state, int write_combine);
|
2005-04-17 05:20:36 +07:00
|
|
|
extern void pcibios_set_master(struct pci_dev *dev);
|
|
|
|
|
|
|
|
/* Dynamic DMA mapping stuff.
|
|
|
|
* SuperH has everything mapped statically like x86.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* The PCI address space does equal the physical memory
|
|
|
|
* address space. The networking and block device layers use
|
|
|
|
* this boolean for bounce buffer decisions.
|
|
|
|
*/
|
2009-10-20 10:55:56 +07:00
|
|
|
#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-04-24 13:39:39 +07:00
|
|
|
#ifdef CONFIG_PCI
|
2009-05-26 21:13:13 +07:00
|
|
|
/*
|
|
|
|
* None of the SH PCI controllers support MWI, it is always treated as a
|
|
|
|
* direct memory write.
|
|
|
|
*/
|
|
|
|
#define PCI_DISABLE_MWI
|
|
|
|
|
2005-06-03 02:55:50 +07:00
|
|
|
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
|
|
|
|
enum pci_dma_burst_strategy *strat,
|
|
|
|
unsigned long *strategy_parameter)
|
|
|
|
{
|
2009-05-26 21:13:13 +07:00
|
|
|
unsigned long cacheline_size;
|
|
|
|
u8 byte;
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
|
|
|
|
|
|
|
|
if (byte == 0)
|
|
|
|
cacheline_size = L1_CACHE_BYTES;
|
|
|
|
else
|
|
|
|
cacheline_size = byte << 2;
|
|
|
|
|
|
|
|
*strat = PCI_DMA_BURST_MULTIPLE;
|
|
|
|
*strategy_parameter = cacheline_size;
|
2005-06-03 02:55:50 +07:00
|
|
|
}
|
2009-04-24 13:39:39 +07:00
|
|
|
#endif
|
2008-02-19 19:35:22 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Board-specific fixup routines. */
|
2011-06-10 21:30:21 +07:00
|
|
|
int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-01-29 20:38:13 +07:00
|
|
|
#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
|
|
|
|
|
|
|
|
static inline int pci_proc_domain(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
struct pci_channel *hose = bus->sysdata;
|
|
|
|
return hose->need_domain_info;
|
|
|
|
}
|
|
|
|
|
2009-04-20 13:38:25 +07:00
|
|
|
/* Chances are this interrupt is wired PC-style ... */
|
|
|
|
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
|
|
|
{
|
|
|
|
return channel ? 15 : 14;
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* generic DMA-mapping stuff */
|
|
|
|
#include <asm-generic/pci-dma-compat.h>
|
|
|
|
|
2009-04-20 13:38:25 +07:00
|
|
|
#endif /* __KERNEL__ */
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif /* __ASM_SH_PCI_H */
|
|
|
|
|