mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:06:45 +07:00
sh: Hook up ERR/PERR/SERR detection for SH7780 PCI host controllers.
These were never handled before, so implement some common infrastructure to support them, then make use of that in the SH7780-specific code. In practice there is little here that can not be generalized for SH4 parts, which will be an incremental change as the 7780/7751 code is gradually unified. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
bcf39352eb
commit
ef407beefb
@ -1,4 +1,6 @@
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/kernel.h>
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static int __init
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@ -62,3 +64,80 @@ int __init pci_is_66mhz_capable(struct pci_channel *hose,
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return cap66 > 0;
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}
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static void pcibios_enable_err(unsigned long __data)
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{
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struct pci_channel *hose = (struct pci_channel *)__data;
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del_timer(&hose->err_timer);
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printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
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enable_irq(hose->err_irq);
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}
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static void pcibios_enable_serr(unsigned long __data)
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{
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struct pci_channel *hose = (struct pci_channel *)__data;
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del_timer(&hose->serr_timer);
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printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
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enable_irq(hose->serr_irq);
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}
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void pcibios_enable_timers(struct pci_channel *hose)
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{
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if (hose->err_irq) {
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init_timer(&hose->err_timer);
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hose->err_timer.data = (unsigned long)hose;
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hose->err_timer.function = pcibios_enable_err;
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}
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if (hose->serr_irq) {
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init_timer(&hose->serr_timer);
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hose->serr_timer.data = (unsigned long)hose;
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hose->serr_timer.function = pcibios_enable_serr;
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}
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}
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/*
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* A simple handler for the regular PCI status errors, called from IRQ
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* context.
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*/
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unsigned int pcibios_handle_status_errors(unsigned long addr,
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unsigned int status,
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struct pci_channel *hose)
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{
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unsigned int cmd = 0;
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if (status & PCI_STATUS_REC_MASTER_ABORT) {
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printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
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cmd |= PCI_STATUS_REC_MASTER_ABORT;
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}
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if (status & PCI_STATUS_REC_TARGET_ABORT) {
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printk(KERN_DEBUG "PCI: target abort: ");
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pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT, 1);
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printk("\n");
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cmd |= PCI_STATUS_REC_TARGET_ABORT;
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}
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if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
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printk(KERN_DEBUG "PCI: parity error detected: ");
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pcibios_report_status(PCI_STATUS_PARITY |
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PCI_STATUS_DETECTED_PARITY, 1);
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printk("\n");
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cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
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/* Now back off of the IRQ for awhile */
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if (hose->err_irq) {
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disable_irq(hose->err_irq);
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hose->err_timer.expires = jiffies + HZ;
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add_timer(&hose->err_timer);
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}
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}
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return cmd;
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}
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@ -16,7 +16,7 @@
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* Direct access to PCI hardware...
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*/
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#define CONFIG_CMD(bus, devfn, where) \
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(P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
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(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
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static DEFINE_SPINLOCK(sh4_pci_lock);
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@ -11,6 +11,9 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/log2.h>
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@ -39,8 +42,165 @@ static struct pci_channel sh7780_pci_controller = {
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.io_resource = &sh7785_io_resource,
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.io_offset = 0x00000000,
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.io_map_base = SH7780_PCI_IO_BASE,
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.serr_irq = evt2irq(0xa00),
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.err_irq = evt2irq(0xaa0),
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};
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struct pci_errors {
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unsigned int mask;
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const char *str;
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} pci_arbiter_errors[] = {
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{ SH4_PCIAINT_MBKN, "master broken" },
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{ SH4_PCIAINT_TBTO, "target bus time out" },
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{ SH4_PCIAINT_MBTO, "master bus time out" },
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{ SH4_PCIAINT_TABT, "target abort" },
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{ SH4_PCIAINT_MABT, "master abort" },
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{ SH4_PCIAINT_RDPE, "read data parity error" },
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{ SH4_PCIAINT_WDPE, "write data parity error" },
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}, pci_interrupt_errors[] = {
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{ SH4_PCIINT_MLCK, "master lock error" },
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{ SH4_PCIINT_TABT, "target-target abort" },
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{ SH4_PCIINT_TRET, "target retry time out" },
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{ SH4_PCIINT_MFDE, "master function disable erorr" },
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{ SH4_PCIINT_PRTY, "address parity error" },
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{ SH4_PCIINT_SERR, "SERR" },
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{ SH4_PCIINT_TWDP, "data parity error for target write" },
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{ SH4_PCIINT_TRDP, "PERR detected for target read" },
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{ SH4_PCIINT_MTABT, "target abort for master" },
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{ SH4_PCIINT_MMABT, "master abort for master" },
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{ SH4_PCIINT_MWPD, "master write data parity error" },
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{ SH4_PCIINT_MRPD, "master read data parity error" },
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};
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static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
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{
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struct pci_channel *hose = dev_id;
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unsigned long addr;
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unsigned int status;
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unsigned int cmd;
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int i;
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addr = __raw_readl(hose->reg_base + SH4_PCIALR);
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/*
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* Handle status errors.
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*/
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status = __raw_readw(hose->reg_base + PCI_STATUS);
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if (status & (PCI_STATUS_PARITY |
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PCI_STATUS_DETECTED_PARITY |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT)) {
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cmd = pcibios_handle_status_errors(addr, status, hose);
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if (likely(cmd))
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__raw_writew(cmd, hose->reg_base + PCI_STATUS);
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}
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/*
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* Handle arbiter errors.
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*/
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status = __raw_readl(hose->reg_base + SH4_PCIAINT);
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for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
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if (status & pci_arbiter_errors[i].mask) {
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printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
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pci_arbiter_errors[i].str, addr);
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cmd |= pci_arbiter_errors[i].mask;
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}
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}
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__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
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/*
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* Handle the remaining PCI errors.
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*/
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status = __raw_readl(hose->reg_base + SH4_PCIINT);
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for (i = cmd = 0; i < ARRAY_SIZE(pci_interrupt_errors); i++) {
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if (status & pci_interrupt_errors[i].mask) {
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printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
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pci_interrupt_errors[i].str, addr);
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cmd |= pci_interrupt_errors[i].mask;
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}
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}
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__raw_writel(cmd, hose->reg_base + SH4_PCIINT);
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return IRQ_HANDLED;
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}
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static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id)
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{
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struct pci_channel *hose = dev_id;
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printk(KERN_DEBUG "PCI: system error received: ");
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pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
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printk("\n");
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/* Deassert SERR */
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__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
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/* Back off the IRQ for awhile */
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disable_irq(irq);
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hose->serr_timer.expires = jiffies + HZ;
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add_timer(&hose->serr_timer);
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return IRQ_HANDLED;
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}
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static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
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{
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int ret;
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/* Clear out PCI arbiter IRQs */
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__raw_writel(0, hose->reg_base + SH4_PCIAINT);
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/* Clear all error conditions */
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__raw_writew(PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_SIG_TARGET_ABORT | \
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PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
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ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, IRQF_DISABLED,
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"PCI SERR interrupt", hose);
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if (unlikely(ret)) {
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printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n");
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return ret;
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}
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/*
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* The PCI ERR IRQ needs to be IRQF_SHARED since all of the power
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* down IRQ vectors are routed through the ERR IRQ vector. We
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* only request_irq() once as there is only a single masking
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* source for multiple events.
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*/
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ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
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"PCI ERR interrupt", hose);
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if (unlikely(ret)) {
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free_irq(hose->serr_irq, hose);
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return ret;
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}
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/* Unmask all of the arbiter IRQs. */
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__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
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SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
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SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
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/* Unmask all of the PCI IRQs */
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__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
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SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
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SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
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SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
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SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
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SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
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return ret;
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}
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static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
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{
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free_irq(hose->err_irq, hose);
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free_irq(hose->serr_irq, hose);
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}
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static void __init sh7780_pci66_init(struct pci_channel *hose)
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{
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unsigned int tmp;
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@ -149,33 +309,12 @@ static int __init sh7780_pci_init(void)
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__raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
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chan->reg_base + SH4_PCILSR0);
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/* Clear out PCI arbiter IRQs */
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__raw_writel(0, chan->reg_base + SH4_PCIAINT);
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/* Unmask all of the arbiter IRQs. */
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__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
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SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
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SH4_PCIAINT_WDPE, chan->reg_base + SH4_PCIAINTM);
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/* Clear all error conditions */
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__raw_writew(PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_SIG_TARGET_ABORT | \
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PCI_STATUS_PARITY, chan->reg_base + PCI_STATUS);
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__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
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PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
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PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
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/* Unmask all of the PCI IRQs */
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__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
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SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
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SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
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SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
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SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
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SH4_PCIINTM_MRDPEIM, chan->reg_base + SH4_PCIINTM);
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/*
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* Hook up the ERR and SERR IRQs.
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*/
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ret = sh7780_pci_setup_irqs(chan);
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if (unlikely(ret))
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return ret;
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/*
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* Disable the cache snoop controller for non-coherent DMA.
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@ -191,6 +330,10 @@ static int __init sh7780_pci_init(void)
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
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__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
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__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
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PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
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PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
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/*
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* Initialization mode complete, release the control register and
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* enable round robin mode to stop device overruns/starvation.
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@ -200,7 +343,7 @@ static int __init sh7780_pci_init(void)
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ret = register_pci_controller(chan);
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if (unlikely(ret))
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return ret;
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goto err;
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sh7780_pci66_init(chan);
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@ -209,5 +352,9 @@ static int __init sh7780_pci_init(void)
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66 : 33);
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return 0;
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err:
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sh7780_pci_teardown_irqs(chan);
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return ret;
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}
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arch_initcall(sh7780_pci_init);
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@ -78,6 +78,11 @@ int __devinit register_pci_controller(struct pci_channel *hose)
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"registering PCI controller with io_map_base unset\n");
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}
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/*
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* Setup the ERR/PERR and SERR timers, if available.
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*/
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pcibios_enable_timers(hose);
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/*
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* Scan the bus if it is register after the PCI subsystem
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* initialization.
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@ -289,6 +294,52 @@ char * __devinit pcibios_setup(char *str)
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return str;
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}
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/*
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* We can't use pci_find_device() here since we are
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* called from interrupt context.
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*/
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static void pcibios_bus_report_status(struct pci_bus *bus,
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unsigned int status_mask, int warn)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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/*
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* ignore host bridge - we handle
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* that separately
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*/
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if (dev->bus->number == 0 && dev->devfn == 0)
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continue;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (status == 0xffff)
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continue;
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if ((status & status_mask) == 0)
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continue;
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/* clear the status errors */
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pci_write_config_word(dev, PCI_STATUS, status & status_mask);
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if (warn)
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printk("(%s: %04X) ", pci_name(dev), status);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->subordinate)
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pcibios_bus_report_status(dev->subordinate, status_mask, warn);
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}
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void pcibios_report_status(unsigned int status_mask, int warn)
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{
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struct pci_channel *hose;
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for (hose = hose_head; hose; hose = hose->next)
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pcibios_bus_report_status(hose->bus, status_mask, warn);
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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@ -29,9 +29,20 @@ struct pci_channel {
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unsigned int index;
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unsigned int need_domain_info;
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/* Optional error handling */
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struct timer_list err_timer, serr_timer;
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unsigned int err_irq, serr_irq;
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};
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/* arch/sh/drivers/pci/pci.c */
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extern int register_pci_controller(struct pci_channel *hose);
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extern void pcibios_report_status(unsigned int status_mask, int warn);
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/* arch/sh/drivers/pci/common.c */
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extern void pcibios_enable_timers(struct pci_channel *hose);
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extern unsigned int pcibios_handle_status_errors(unsigned long addr,
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unsigned int status, struct pci_channel *hose);
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extern int pci_is_66mhz_capable(struct pci_channel *hose,
|
||||
int top_bus, int current_bus);
|
||||
|
||||
|
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Reference in New Issue
Block a user