2005-04-17 05:20:36 +07:00
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/*
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* arch/sh/mm/cache-sh4.c
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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2009-09-09 14:06:39 +07:00
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* Copyright (C) 2001 - 2009 Paul Mundt
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2005-04-17 05:20:36 +07:00
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* Copyright (C) 2003 Richard Curnow
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2008-07-02 13:17:11 +07:00
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* Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
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2005-04-17 05:20:36 +07:00
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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2006-11-21 09:09:41 +07:00
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#include <linux/io.h>
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#include <linux/mutex.h>
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2009-07-22 17:20:49 +07:00
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#include <linux/fs.h>
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2009-09-09 14:06:39 +07:00
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#include <linux/highmem.h>
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#include <asm/pgtable.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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2006-09-27 16:30:07 +07:00
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/*
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* The maximum number of pages we support up to when doing ranged dcache
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* flushing. Anything exceeding this will simply flush the dcache in its
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* entirety.
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*/
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2008-07-02 13:17:11 +07:00
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#define MAX_ICACHE_PAGES 32
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2006-09-27 16:30:07 +07:00
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2009-10-16 12:15:38 +07:00
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static void __flush_cache_one(unsigned long addr, unsigned long phys,
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2006-09-27 09:29:55 +07:00
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unsigned long exec_offset);
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2006-09-27 12:09:26 +07:00
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2005-04-17 05:20:36 +07:00
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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2008-07-02 13:17:11 +07:00
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* Called from kernel/module.c:sys_init_module and routine for a.out format,
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* signal handler code and kprobes code
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2005-04-17 05:20:36 +07:00
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*/
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2010-01-21 14:05:25 +07:00
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static void sh4_flush_icache_range(void *args)
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2005-04-17 05:20:36 +07:00
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{
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2009-08-21 15:23:14 +07:00
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struct flusher_data *data = args;
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unsigned long start, end;
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2009-09-01 19:12:55 +07:00
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unsigned long flags, v;
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2005-04-17 05:20:36 +07:00
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int i;
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2009-08-21 15:23:14 +07:00
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start = data->addr1;
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end = data->addr2;
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2009-09-09 11:19:46 +07:00
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/* If there are too many pages then just blow away the caches */
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if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
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local_flush_cache_all(NULL);
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return;
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}
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/*
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* Selectively flush d-cache then invalidate the i-cache.
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* This is inefficient, so only use this for small ranges.
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*/
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start &= ~(L1_CACHE_BYTES-1);
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end += L1_CACHE_BYTES-1;
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end &= ~(L1_CACHE_BYTES-1);
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2009-09-01 19:12:55 +07:00
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2009-09-09 11:19:46 +07:00
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local_irq_save(flags);
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jump_to_uncached();
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2009-09-01 19:12:55 +07:00
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2009-09-09 11:19:46 +07:00
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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unsigned long icacheaddr;
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2009-11-06 06:14:39 +07:00
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int j, n;
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2009-09-01 19:12:55 +07:00
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2009-09-09 11:19:46 +07:00
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__ocbwb(v);
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2009-09-01 19:12:55 +07:00
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2009-09-09 11:19:46 +07:00
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icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v &
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cpu_data->icache.entry_mask);
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2008-07-02 13:17:11 +07:00
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2009-09-09 11:19:46 +07:00
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/* Clear i-cache line valid-bit */
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2009-11-06 06:14:39 +07:00
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n = boot_cpu_data.icache.n_aliases;
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2009-09-09 11:19:46 +07:00
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for (i = 0; i < cpu_data->icache.ways; i++) {
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2009-11-06 06:14:39 +07:00
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for (j = 0; j < n; j++)
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__raw_writel(0, icacheaddr + (j * PAGE_SIZE));
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2009-09-09 11:19:46 +07:00
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icacheaddr += cpu_data->icache.way_incr;
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}
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2008-07-02 13:17:11 +07:00
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}
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2009-09-09 11:19:46 +07:00
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back_to_cached();
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local_irq_restore(flags);
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2005-04-17 05:20:36 +07:00
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}
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2009-10-16 12:15:38 +07:00
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static inline void flush_cache_one(unsigned long start, unsigned long phys)
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2005-04-17 05:20:36 +07:00
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{
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2009-09-01 19:12:55 +07:00
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unsigned long flags, exec_offset = 0;
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2006-09-27 16:37:30 +07:00
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2005-04-17 05:20:36 +07:00
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/*
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2009-10-07 04:22:25 +07:00
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* All types of SH-4 require PC to be uncached to operate on the I-cache.
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* Some types of SH-4 require PC to be uncached to operate on the D-cache.
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2005-04-17 05:20:36 +07:00
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*/
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2007-09-21 16:05:20 +07:00
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if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
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2006-09-27 16:37:30 +07:00
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(start < CACHE_OC_ADDRESS_ARRAY))
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2009-10-07 04:22:25 +07:00
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exec_offset = cached_to_uncached;
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2006-09-27 16:37:30 +07:00
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2009-09-01 19:12:55 +07:00
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local_irq_save(flags);
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2009-12-04 14:18:11 +07:00
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__flush_cache_one(start, phys, exec_offset);
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2009-09-01 19:12:55 +07:00
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local_irq_restore(flags);
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2005-04-17 05:20:36 +07:00
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}
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*/
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2009-08-27 09:31:16 +07:00
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static void sh4_flush_dcache_page(void *arg)
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2005-04-17 05:20:36 +07:00
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{
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2009-08-27 09:31:16 +07:00
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struct page *page = arg;
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2009-12-25 05:17:35 +07:00
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unsigned long addr = (unsigned long)page_address(page);
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2009-08-20 13:24:41 +07:00
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#ifndef CONFIG_SMP
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2009-07-22 17:20:49 +07:00
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struct address_space *mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping))
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2010-12-01 13:39:51 +07:00
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clear_bit(PG_dcache_clean, &page->flags);
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2009-07-22 17:20:49 +07:00
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else
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#endif
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2009-12-25 05:17:35 +07:00
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flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
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(addr & shm_align_mask), page_to_phys(page));
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2006-09-27 12:05:52 +07:00
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wmb();
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2005-04-17 05:20:36 +07:00
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}
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2006-09-27 16:30:07 +07:00
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/* TODO: Selective icache invalidation through IC address array.. */
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2010-01-21 14:05:25 +07:00
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static void flush_icache_all(void)
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2005-04-17 05:20:36 +07:00
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{
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2009-09-01 19:12:55 +07:00
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unsigned long flags, ccr;
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2005-04-17 05:20:36 +07:00
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2009-09-01 19:12:55 +07:00
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local_irq_save(flags);
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2007-11-30 15:06:36 +07:00
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jump_to_uncached();
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2005-04-17 05:20:36 +07:00
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/* Flush I-cache */
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2010-01-26 10:58:40 +07:00
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ccr = __raw_readl(CCR);
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2005-04-17 05:20:36 +07:00
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ccr |= CCR_CACHE_ICI;
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2010-01-26 10:58:40 +07:00
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__raw_writel(ccr, CCR);
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2005-04-17 05:20:36 +07:00
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2006-09-27 12:57:44 +07:00
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/*
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2007-11-30 15:06:36 +07:00
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* back_to_cached() will take care of the barrier for us, don't add
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2006-09-27 12:57:44 +07:00
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* another one!
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*/
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2009-09-01 19:12:55 +07:00
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2007-11-30 15:06:36 +07:00
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back_to_cached();
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2009-09-01 19:12:55 +07:00
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local_irq_restore(flags);
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2005-04-17 05:20:36 +07:00
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}
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2009-09-09 12:22:15 +07:00
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static void flush_dcache_all(void)
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2005-04-17 05:20:36 +07:00
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{
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2009-09-09 12:22:15 +07:00
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unsigned long addr, end_addr, entry_offset;
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end_addr = CACHE_OC_ADDRESS_ARRAY +
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(current_cpu_data.dcache.sets <<
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current_cpu_data.dcache.entry_shift) *
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current_cpu_data.dcache.ways;
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entry_offset = 1 << current_cpu_data.dcache.entry_shift;
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for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) {
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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__raw_writel(0, addr); addr += entry_offset;
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}
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2006-09-27 09:29:55 +07:00
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}
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2009-08-21 15:23:14 +07:00
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static void sh4_flush_cache_all(void *unused)
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2006-09-27 09:29:55 +07:00
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{
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flush_dcache_all();
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2005-04-17 05:20:36 +07:00
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flush_icache_all();
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}
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2006-09-27 16:30:07 +07:00
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/*
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* Note : (RPC) since the caches are physically tagged, the only point
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* of flush_cache_mm for SH-4 is to get rid of aliases from the
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* D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
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* lines can stay resident so long as the virtual address they were
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* accessed with (hence cache set) is in accord with the physical
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sh: sh4_flush_cache_mm() optimizations.
The i-cache flush in the case of VM_EXEC was added way back when as a
sanity measure, and in practice we only care about evicting aliases from
the d-cache. As a result, it's possible to drop the i-cache flush
completely here.
After careful profiling it's also come up that all of the work associated
with hunting down aliases and doing ranged flushing ends up generating
more overhead than simply blasting away the entire dcache, particularly
if there are many mm's that need to be iterated over. As a result of
that, just move back to flush_dcache_all() in these cases, which restores
the old behaviour, and vastly simplifies the path.
Additionally, on platforms without aliases at all, this can simply be
nopped out. Presently we have the alias check in the SH-4 specific
version, but this is true for all of the platforms, so move the check up
to a generic location. This cuts down quite a bit on superfluous cacheop
IPIs.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-09 12:04:06 +07:00
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* address (i.e. tag). It's no different here.
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2006-09-27 16:30:07 +07:00
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*
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* Caller takes mm->mmap_sem.
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*/
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2009-08-21 15:23:14 +07:00
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static void sh4_flush_cache_mm(void *arg)
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2005-04-17 05:20:36 +07:00
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{
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2009-08-21 15:23:14 +07:00
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struct mm_struct *mm = arg;
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2009-08-15 00:21:16 +07:00
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if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)
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return;
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|
|
|
sh: sh4_flush_cache_mm() optimizations.
The i-cache flush in the case of VM_EXEC was added way back when as a
sanity measure, and in practice we only care about evicting aliases from
the d-cache. As a result, it's possible to drop the i-cache flush
completely here.
After careful profiling it's also come up that all of the work associated
with hunting down aliases and doing ranged flushing ends up generating
more overhead than simply blasting away the entire dcache, particularly
if there are many mm's that need to be iterated over. As a result of
that, just move back to flush_dcache_all() in these cases, which restores
the old behaviour, and vastly simplifies the path.
Additionally, on platforms without aliases at all, this can simply be
nopped out. Presently we have the alias check in the SH-4 specific
version, but this is true for all of the platforms, so move the check up
to a generic location. This cuts down quite a bit on superfluous cacheop
IPIs.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-09 12:04:06 +07:00
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flush_dcache_all();
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2005-04-17 05:20:36 +07:00
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}
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/*
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* Write back and invalidate I/D-caches for the page.
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*
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* ADDR: Virtual Address (U0 address)
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* PFN: Physical page number
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*/
|
2009-08-21 15:23:14 +07:00
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static void sh4_flush_cache_page(void *args)
|
2005-04-17 05:20:36 +07:00
|
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{
|
2009-08-21 15:23:14 +07:00
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struct flusher_data *data = args;
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struct vm_area_struct *vma;
|
2009-09-09 14:06:39 +07:00
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struct page *page;
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2009-08-21 15:23:14 +07:00
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unsigned long address, pfn, phys;
|
2009-09-09 14:06:39 +07:00
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int map_coherent = 0;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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void *vaddr;
|
2006-09-27 12:09:26 +07:00
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2009-08-21 15:23:14 +07:00
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vma = data->vma;
|
2009-10-16 13:14:50 +07:00
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address = data->addr1 & PAGE_MASK;
|
2009-08-21 15:23:14 +07:00
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pfn = data->addr2;
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phys = pfn << PAGE_SHIFT;
|
2009-09-09 14:06:39 +07:00
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page = pfn_to_page(pfn);
|
2009-08-21 15:23:14 +07:00
|
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|
2009-08-15 00:21:16 +07:00
|
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if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
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return;
|
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|
2009-09-09 14:06:39 +07:00
|
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pgd = pgd_offset(vma->vm_mm, address);
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pud = pud_offset(pgd, address);
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pmd = pmd_offset(pud, address);
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pte = pte_offset_kernel(pmd, address);
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/* If the page isn't present, there is nothing to do here. */
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if (!(pte_val(*pte) & _PAGE_PRESENT))
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return;
|
2005-04-17 05:20:36 +07:00
|
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|
2009-09-09 14:06:39 +07:00
|
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|
if ((vma->vm_mm == current->active_mm))
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vaddr = NULL;
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else {
|
2006-09-27 12:09:26 +07:00
|
|
|
/*
|
2009-09-09 14:06:39 +07:00
|
|
|
* Use kmap_coherent or kmap_atomic to do flushes for
|
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* another ASID than the current one.
|
2006-09-27 12:09:26 +07:00
|
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|
*/
|
2009-09-09 14:06:39 +07:00
|
|
|
map_coherent = (current_cpu_data.dcache.n_aliases &&
|
2010-12-01 13:39:51 +07:00
|
|
|
test_bit(PG_dcache_clean, &page->flags) &&
|
2009-09-09 14:06:39 +07:00
|
|
|
page_mapped(page));
|
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|
|
if (map_coherent)
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|
|
vaddr = kmap_coherent(page, address);
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|
|
else
|
2011-11-25 22:14:16 +07:00
|
|
|
vaddr = kmap_atomic(page);
|
2009-09-09 14:06:39 +07:00
|
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|
address = (unsigned long)vaddr;
|
|
|
|
}
|
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|
|
|
2009-12-08 21:23:11 +07:00
|
|
|
flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
|
2009-09-09 14:06:39 +07:00
|
|
|
(address & shm_align_mask), phys);
|
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|
|
if (vma->vm_flags & VM_EXEC)
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|
|
|
flush_icache_all();
|
|
|
|
|
|
|
|
if (vaddr) {
|
|
|
|
if (map_coherent)
|
|
|
|
kunmap_coherent(vaddr);
|
|
|
|
else
|
2011-11-25 22:14:16 +07:00
|
|
|
kunmap_atomic(vaddr);
|
2006-09-27 12:09:26 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write back and invalidate D-caches.
|
|
|
|
*
|
|
|
|
* START, END: Virtual Address (U0 address)
|
|
|
|
*
|
|
|
|
* NOTE: We need to flush the _physical_ page entry.
|
|
|
|
* Flushing the cache lines for U0 only isn't enough.
|
|
|
|
* We need to flush for P1 too, which may contain aliases.
|
|
|
|
*/
|
2009-08-21 15:23:14 +07:00
|
|
|
static void sh4_flush_cache_range(void *args)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2009-08-21 15:23:14 +07:00
|
|
|
struct flusher_data *data = args;
|
|
|
|
struct vm_area_struct *vma;
|
|
|
|
unsigned long start, end;
|
|
|
|
|
|
|
|
vma = data->vma;
|
|
|
|
start = data->addr1;
|
|
|
|
end = data->addr2;
|
|
|
|
|
2009-08-15 00:21:16 +07:00
|
|
|
if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
|
|
|
|
return;
|
|
|
|
|
2006-09-27 12:09:26 +07:00
|
|
|
/*
|
|
|
|
* If cache is only 4k-per-way, there are never any 'aliases'. Since
|
|
|
|
* the cache is physically tagged, the data can just be left in there.
|
|
|
|
*/
|
2007-09-21 16:05:20 +07:00
|
|
|
if (boot_cpu_data.dcache.n_aliases == 0)
|
2006-09-27 12:09:26 +07:00
|
|
|
return;
|
|
|
|
|
sh: sh4_flush_cache_mm() optimizations.
The i-cache flush in the case of VM_EXEC was added way back when as a
sanity measure, and in practice we only care about evicting aliases from
the d-cache. As a result, it's possible to drop the i-cache flush
completely here.
After careful profiling it's also come up that all of the work associated
with hunting down aliases and doing ranged flushing ends up generating
more overhead than simply blasting away the entire dcache, particularly
if there are many mm's that need to be iterated over. As a result of
that, just move back to flush_dcache_all() in these cases, which restores
the old behaviour, and vastly simplifies the path.
Additionally, on platforms without aliases at all, this can simply be
nopped out. Presently we have the alias check in the SH-4 specific
version, but this is true for all of the platforms, so move the check up
to a generic location. This cuts down quite a bit on superfluous cacheop
IPIs.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-09 12:04:06 +07:00
|
|
|
flush_dcache_all();
|
2006-09-27 12:09:26 +07:00
|
|
|
|
sh: sh4_flush_cache_mm() optimizations.
The i-cache flush in the case of VM_EXEC was added way back when as a
sanity measure, and in practice we only care about evicting aliases from
the d-cache. As a result, it's possible to drop the i-cache flush
completely here.
After careful profiling it's also come up that all of the work associated
with hunting down aliases and doing ranged flushing ends up generating
more overhead than simply blasting away the entire dcache, particularly
if there are many mm's that need to be iterated over. As a result of
that, just move back to flush_dcache_all() in these cases, which restores
the old behaviour, and vastly simplifies the path.
Additionally, on platforms without aliases at all, this can simply be
nopped out. Presently we have the alias check in the SH-4 specific
version, but this is true for all of the platforms, so move the check up
to a generic location. This cuts down quite a bit on superfluous cacheop
IPIs.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-09 12:04:06 +07:00
|
|
|
if (vma->vm_flags & VM_EXEC)
|
2005-04-17 05:20:36 +07:00
|
|
|
flush_icache_all();
|
|
|
|
}
|
|
|
|
|
2006-09-27 12:09:26 +07:00
|
|
|
/**
|
2009-10-16 12:15:38 +07:00
|
|
|
* __flush_cache_one
|
2006-09-27 12:09:26 +07:00
|
|
|
*
|
|
|
|
* @addr: address in memory mapped cache array
|
|
|
|
* @phys: P1 address to flush (has to match tags if addr has 'A' bit
|
|
|
|
* set i.e. associative write)
|
|
|
|
* @exec_offset: set to 0x20000000 if flush has to be executed from P2
|
|
|
|
* region else 0x0
|
|
|
|
*
|
|
|
|
* The offset into the cache array implied by 'addr' selects the
|
|
|
|
* 'colour' of the virtual address range that will be flushed. The
|
|
|
|
* operation (purge/write-back) is selected by the lower 2 bits of
|
|
|
|
* 'phys'.
|
|
|
|
*/
|
2009-10-16 12:15:38 +07:00
|
|
|
static void __flush_cache_one(unsigned long addr, unsigned long phys,
|
2006-09-27 12:09:26 +07:00
|
|
|
unsigned long exec_offset)
|
|
|
|
{
|
|
|
|
int way_count;
|
|
|
|
unsigned long base_addr = addr;
|
|
|
|
struct cache_info *dcache;
|
|
|
|
unsigned long way_incr;
|
|
|
|
unsigned long a, ea, p;
|
|
|
|
unsigned long temp_pc;
|
|
|
|
|
2007-09-21 16:05:20 +07:00
|
|
|
dcache = &boot_cpu_data.dcache;
|
2006-09-27 12:09:26 +07:00
|
|
|
/* Write this way for better assembly. */
|
|
|
|
way_count = dcache->ways;
|
|
|
|
way_incr = dcache->way_incr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Apply exec_offset (i.e. branch to P2 if required.).
|
|
|
|
*
|
|
|
|
* FIXME:
|
|
|
|
*
|
|
|
|
* If I write "=r" for the (temp_pc), it puts this in r6 hence
|
|
|
|
* trashing exec_offset before it's been added on - why? Hence
|
|
|
|
* "=&r" as a 'workaround'
|
|
|
|
*/
|
|
|
|
asm volatile("mov.l 1f, %0\n\t"
|
|
|
|
"add %1, %0\n\t"
|
|
|
|
"jmp @%0\n\t"
|
|
|
|
"nop\n\t"
|
|
|
|
".balign 4\n\t"
|
|
|
|
"1: .long 2f\n\t"
|
|
|
|
"2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We know there will be >=1 iteration, so write as do-while to avoid
|
|
|
|
* pointless nead-of-loop check for 0 iterations.
|
|
|
|
*/
|
|
|
|
do {
|
|
|
|
ea = base_addr + PAGE_SIZE;
|
|
|
|
a = base_addr;
|
|
|
|
p = phys;
|
|
|
|
|
|
|
|
do {
|
|
|
|
*(volatile unsigned long *)a = p;
|
|
|
|
/*
|
|
|
|
* Next line: intentionally not p+32, saves an add, p
|
|
|
|
* will do since only the cache tag bits need to
|
|
|
|
* match.
|
|
|
|
*/
|
|
|
|
*(volatile unsigned long *)(a+32) = p;
|
|
|
|
a += 64;
|
|
|
|
p += 64;
|
|
|
|
} while (a < ea);
|
|
|
|
|
|
|
|
base_addr += way_incr;
|
|
|
|
} while (--way_count != 0);
|
|
|
|
}
|
|
|
|
|
2009-08-15 10:29:49 +07:00
|
|
|
extern void __weak sh4__flush_region_init(void);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* SH-4 has virtually indexed and physically tagged cache.
|
|
|
|
*/
|
|
|
|
void __init sh4_cache_init(void)
|
|
|
|
{
|
|
|
|
printk("PVR=%08x CVR=%08x PRR=%08x\n",
|
2010-01-26 10:58:40 +07:00
|
|
|
__raw_readl(CCN_PVR),
|
|
|
|
__raw_readl(CCN_CVR),
|
|
|
|
__raw_readl(CCN_PRR));
|
2009-08-15 10:29:49 +07:00
|
|
|
|
2009-08-21 15:23:14 +07:00
|
|
|
local_flush_icache_range = sh4_flush_icache_range;
|
|
|
|
local_flush_dcache_page = sh4_flush_dcache_page;
|
|
|
|
local_flush_cache_all = sh4_flush_cache_all;
|
|
|
|
local_flush_cache_mm = sh4_flush_cache_mm;
|
|
|
|
local_flush_cache_dup_mm = sh4_flush_cache_mm;
|
|
|
|
local_flush_cache_page = sh4_flush_cache_page;
|
|
|
|
local_flush_cache_range = sh4_flush_cache_range;
|
2009-08-15 10:29:49 +07:00
|
|
|
|
|
|
|
sh4__flush_region_init();
|
|
|
|
}
|