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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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sh: Avoid smp_processor_id() in cache desc paths.
current_cpu_data uses smp_processor_id() in order to find the corresponding cpu_data. As the cache descs are all currently identical, just have this look at probed results from the boot CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
2d4a73d5b9
commit
7ec9d6f8c0
@ -54,21 +54,21 @@ static void __init emit_cache_params(void)
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ctrl_inl(CCN_CVR),
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ctrl_inl(CCN_PRR));
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printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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current_cpu_data.icache.ways,
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current_cpu_data.icache.sets,
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current_cpu_data.icache.way_incr);
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boot_cpu_data.icache.ways,
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boot_cpu_data.icache.sets,
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boot_cpu_data.icache.way_incr);
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printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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current_cpu_data.icache.entry_mask,
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current_cpu_data.icache.alias_mask,
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current_cpu_data.icache.n_aliases);
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boot_cpu_data.icache.entry_mask,
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boot_cpu_data.icache.alias_mask,
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boot_cpu_data.icache.n_aliases);
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printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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current_cpu_data.dcache.ways,
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current_cpu_data.dcache.sets,
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current_cpu_data.dcache.way_incr);
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boot_cpu_data.dcache.ways,
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boot_cpu_data.dcache.sets,
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boot_cpu_data.dcache.way_incr);
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printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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current_cpu_data.dcache.entry_mask,
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current_cpu_data.dcache.alias_mask,
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current_cpu_data.dcache.n_aliases);
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boot_cpu_data.dcache.entry_mask,
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boot_cpu_data.dcache.alias_mask,
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boot_cpu_data.dcache.n_aliases);
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if (!__flush_dcache_segment_fn)
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panic("unknown number of cache ways\n");
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@ -79,10 +79,10 @@ static void __init emit_cache_params(void)
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*/
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void __init p3_cache_init(void)
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{
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compute_alias(¤t_cpu_data.icache);
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compute_alias(¤t_cpu_data.dcache);
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compute_alias(&boot_cpu_data.icache);
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compute_alias(&boot_cpu_data.dcache);
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switch (current_cpu_data.dcache.ways) {
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switch (boot_cpu_data.dcache.ways) {
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case 1:
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__flush_dcache_segment_fn = __flush_dcache_segment_1way;
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break;
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@ -187,13 +187,13 @@ void flush_cache_sigtramp(unsigned long addr)
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: "m" (__m(v)));
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index = CACHE_IC_ADDRESS_ARRAY |
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(v & current_cpu_data.icache.entry_mask);
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(v & boot_cpu_data.icache.entry_mask);
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local_irq_save(flags);
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jump_to_P2();
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for (i = 0; i < current_cpu_data.icache.ways;
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i++, index += current_cpu_data.icache.way_incr)
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for (i = 0; i < boot_cpu_data.icache.ways;
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i++, index += boot_cpu_data.icache.way_incr)
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ctrl_outl(0, index); /* Clear out Valid-bit */
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back_to_P1();
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@ -210,7 +210,7 @@ static inline void flush_cache_4096(unsigned long start,
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* All types of SH-4 require PC to be in P2 to operate on the I-cache.
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* Some types of SH-4 require PC to be in P2 to operate on the D-cache.
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*/
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if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
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if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
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(start < CACHE_OC_ADDRESS_ARRAY))
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exec_offset = 0x20000000;
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@ -232,7 +232,7 @@ void flush_dcache_page(struct page *page)
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int i, n;
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/* Loop all the D-cache */
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n = current_cpu_data.dcache.n_aliases;
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n = boot_cpu_data.dcache.n_aliases;
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for (i = 0; i < n; i++, addr += 4096)
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flush_cache_4096(addr, phys);
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}
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@ -264,7 +264,7 @@ static inline void flush_icache_all(void)
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void flush_dcache_all(void)
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{
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(*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size);
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(*__flush_dcache_segment_fn)(0UL, boot_cpu_data.dcache.way_size);
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wmb();
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}
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@ -278,8 +278,8 @@ static void __flush_cache_mm(struct mm_struct *mm, unsigned long start,
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unsigned long end)
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{
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unsigned long d = 0, p = start & PAGE_MASK;
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unsigned long alias_mask = current_cpu_data.dcache.alias_mask;
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unsigned long n_aliases = current_cpu_data.dcache.n_aliases;
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unsigned long alias_mask = boot_cpu_data.dcache.alias_mask;
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unsigned long n_aliases = boot_cpu_data.dcache.n_aliases;
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unsigned long select_bit;
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unsigned long all_aliases_mask;
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unsigned long addr_offset;
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@ -366,7 +366,7 @@ void flush_cache_mm(struct mm_struct *mm)
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* If cache is only 4k-per-way, there are never any 'aliases'. Since
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* the cache is physically tagged, the data can just be left in there.
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*/
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if (current_cpu_data.dcache.n_aliases == 0)
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if (boot_cpu_data.dcache.n_aliases == 0)
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return;
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/*
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@ -403,7 +403,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
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unsigned long phys = pfn << PAGE_SHIFT;
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unsigned int alias_mask;
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alias_mask = current_cpu_data.dcache.alias_mask;
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alias_mask = boot_cpu_data.dcache.alias_mask;
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/* We only need to flush D-cache when we have alias */
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if ((address^phys) & alias_mask) {
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@ -417,7 +417,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
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phys);
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}
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alias_mask = current_cpu_data.icache.alias_mask;
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alias_mask = boot_cpu_data.icache.alias_mask;
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if (vma->vm_flags & VM_EXEC) {
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/*
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* Evict entries from the portion of the cache from which code
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@ -449,7 +449,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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* If cache is only 4k-per-way, there are never any 'aliases'. Since
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* the cache is physically tagged, the data can just be left in there.
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*/
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if (current_cpu_data.dcache.n_aliases == 0)
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if (boot_cpu_data.dcache.n_aliases == 0)
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return;
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/*
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@ -510,7 +510,7 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
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unsigned long a, ea, p;
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unsigned long temp_pc;
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dcache = ¤t_cpu_data.dcache;
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dcache = &boot_cpu_data.dcache;
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/* Write this way for better assembly. */
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way_count = dcache->ways;
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way_incr = dcache->way_incr;
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@ -585,7 +585,7 @@ static void __flush_dcache_segment_1way(unsigned long start,
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = ¤t_cpu_data.dcache;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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@ -627,7 +627,7 @@ static void __flush_dcache_segment_2way(unsigned long start,
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = ¤t_cpu_data.dcache;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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@ -686,7 +686,7 @@ static void __flush_dcache_segment_4way(unsigned long start,
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base_addr = ((base_addr >> 16) << 16);
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base_addr |= start;
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dcache = ¤t_cpu_data.dcache;
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dcache = &boot_cpu_data.dcache;
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linesz = dcache->linesz;
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way_incr = dcache->way_incr;
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way_size = dcache->way_size;
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