2010-05-21 08:08:55 +07:00
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#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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2014-05-11 04:10:43 +07:00
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#include <linux/hashtable.h>
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2015-04-07 22:20:36 +07:00
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#include "i915_gem_batch_pool.h"
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2014-05-11 04:10:43 +07:00
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#define I915_CMD_HASH_ORDER 9
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2014-07-24 23:04:28 +07:00
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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2015-06-20 01:07:01 +07:00
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#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
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2014-07-24 23:04:28 +07:00
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2012-12-03 23:43:32 +07:00
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/*
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
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* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
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* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
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*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
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* cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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#define I915_RING_FREE_SPACE 64
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2010-05-21 08:08:55 +07:00
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struct intel_hw_status_page {
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2012-04-27 04:28:16 +07:00
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u32 *page_addr;
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2010-05-21 08:08:55 +07:00
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unsigned int gfx_addr;
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2010-11-09 02:18:58 +07:00
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struct drm_i915_gem_object *obj;
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2010-05-21 08:08:55 +07:00
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};
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2011-04-26 01:22:22 +07:00
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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2010-08-02 21:29:44 +07:00
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2014-03-12 18:09:41 +07:00
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#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
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2014-04-02 22:36:07 +07:00
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#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
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2014-03-12 18:09:41 +07:00
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2014-06-30 23:53:37 +07:00
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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2016-04-07 13:29:14 +07:00
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#define gen8_semaphore_seqno_size sizeof(uint64_t)
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#define GEN8_SEMAPHORE_OFFSET(__from, __to) \
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(((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
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2014-06-30 23:53:37 +07:00
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#define GEN8_SIGNAL_OFFSET(__ring, to) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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2016-04-07 13:29:14 +07:00
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GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
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2014-06-30 23:53:37 +07:00
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#define GEN8_WAIT_OFFSET(__ring, from) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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2016-04-07 13:29:14 +07:00
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GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
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2014-06-30 23:53:37 +07:00
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2016-03-16 18:00:36 +07:00
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#define GEN8_RING_SEMAPHORE_INIT(e) do { \
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2014-06-30 23:53:37 +07:00
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if (!dev_priv->semaphore_obj) { \
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break; \
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} \
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2016-03-16 18:00:36 +07:00
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(e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \
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(e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \
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(e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \
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(e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \
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(e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \
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(e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \
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2014-06-30 23:53:37 +07:00
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} while(0)
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2013-08-11 16:44:01 +07:00
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enum intel_ring_hangcheck_action {
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2013-09-06 20:03:28 +07:00
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HANGCHECK_IDLE = 0,
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2013-08-11 16:44:01 +07:00
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HANGCHECK_WAIT,
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HANGCHECK_ACTIVE,
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HANGCHECK_KICK,
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HANGCHECK_HUNG,
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};
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2013-06-12 16:35:32 +07:00
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2014-01-31 00:04:43 +07:00
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#define HANGCHECK_SCORE_RING_HUNG 31
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2013-05-24 21:16:07 +07:00
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struct intel_ring_hangcheck {
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2014-03-21 19:41:53 +07:00
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u64 acthd;
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2013-05-24 21:16:07 +07:00
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u32 seqno;
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2016-04-09 16:57:55 +07:00
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unsigned user_interrupts;
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2013-05-30 13:04:29 +07:00
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int score;
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2013-06-12 16:35:32 +07:00
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enum intel_ring_hangcheck_action action;
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2014-06-06 16:22:29 +07:00
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int deadlock;
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2015-12-01 22:56:12 +07:00
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u32 instdone[I915_NUM_INSTDONE_REG];
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2013-05-24 21:16:07 +07:00
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};
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2014-05-22 20:13:34 +07:00
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struct intel_ringbuffer {
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struct drm_i915_gem_object *obj;
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void __iomem *virtual_start;
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2016-01-15 22:10:28 +07:00
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struct i915_vma *vma;
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2014-05-22 20:13:34 +07:00
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2016-03-16 18:00:38 +07:00
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struct intel_engine_cs *engine;
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2015-09-03 19:01:40 +07:00
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struct list_head link;
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2014-08-11 21:17:44 +07:00
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2014-05-22 20:13:34 +07:00
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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};
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2015-01-15 20:10:38 +07:00
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struct intel_context;
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2016-03-07 14:30:27 +07:00
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struct drm_i915_reg_table;
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2015-01-15 20:10:38 +07:00
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2015-06-20 01:07:01 +07:00
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/*
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* we use a single page to load ctx workarounds so all of these
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* values are referred in terms of dwords
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*
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* struct i915_wa_ctx_bb:
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* offset: specifies batch starting position, also helpful in case
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* if we want to have multiple batches at different offsets based on
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* some criteria. It is not a requirement at the moment but provides
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* an option for future use.
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* size: size of the batch in DWORDS
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*/
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struct i915_ctx_workarounds {
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struct i915_wa_ctx_bb {
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u32 offset;
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u32 size;
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} indirect_ctx, per_ctx;
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struct drm_i915_gem_object *obj;
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};
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2014-05-22 20:13:33 +07:00
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struct intel_engine_cs {
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2010-05-21 08:08:55 +07:00
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const char *name;
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2016-03-16 18:00:40 +07:00
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enum intel_engine_id {
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2016-01-15 22:12:50 +07:00
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RCS = 0,
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2011-12-14 19:57:00 +07:00
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BCS,
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2016-01-15 22:12:50 +07:00
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VCS,
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VCS2, /* Keep instances of the same type engine together. */
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VECS
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2010-09-18 17:02:01 +07:00
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} id;
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2016-03-16 18:00:39 +07:00
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#define I915_NUM_ENGINES 5
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2016-01-15 22:12:50 +07:00
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#define _VCS(n) (VCS + (n))
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2016-01-15 23:51:46 +07:00
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unsigned int exec_id;
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2016-01-24 02:58:14 +07:00
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unsigned int guc_id;
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2010-08-02 21:24:01 +07:00
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u32 mmio_base;
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2010-05-21 08:08:55 +07:00
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struct drm_device *dev;
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2014-05-22 20:13:34 +07:00
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struct intel_ringbuffer *buffer;
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2015-09-03 19:01:40 +07:00
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struct list_head buffers;
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2010-05-21 08:08:55 +07:00
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2015-04-07 22:20:36 +07:00
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/*
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* A pool of objects to use as shadow copies of client batch buffers
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* when the command parser is enabled. Prevents the client from
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* modifying the batch contents after software parsing.
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*/
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struct i915_gem_batch_pool batch_pool;
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2010-05-21 08:08:55 +07:00
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struct intel_hw_status_page status_page;
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2015-06-20 01:07:01 +07:00
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struct i915_ctx_workarounds wa_ctx;
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2010-05-21 08:08:55 +07:00
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2013-07-05 04:35:29 +07:00
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unsigned irq_refcount; /* protected by dev_priv->irq_lock */
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2012-04-12 03:12:46 +07:00
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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2014-11-25 01:49:39 +07:00
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struct drm_i915_gem_request *trace_irq_req;
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2014-05-22 20:13:33 +07:00
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bool __must_check (*irq_get)(struct intel_engine_cs *ring);
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void (*irq_put)(struct intel_engine_cs *ring);
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2010-05-21 08:08:55 +07:00
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2014-11-20 06:33:04 +07:00
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int (*init_hw)(struct intel_engine_cs *ring);
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2010-05-21 08:08:55 +07:00
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2015-05-29 23:43:44 +07:00
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int (*init_context)(struct drm_i915_gem_request *req);
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2014-08-26 20:44:50 +07:00
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2014-05-22 20:13:33 +07:00
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void (*write_tail)(struct intel_engine_cs *ring,
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2010-10-22 23:02:41 +07:00
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u32 value);
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2015-05-29 23:43:57 +07:00
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int __must_check (*flush)(struct drm_i915_gem_request *req,
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2011-01-05 00:34:02 +07:00
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u32 invalidate_domains,
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u32 flush_domains);
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2015-05-29 23:44:00 +07:00
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int (*add_request)(struct drm_i915_gem_request *req);
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2012-08-09 16:58:30 +07:00
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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2016-04-09 16:57:54 +07:00
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void (*irq_seqno_barrier)(struct intel_engine_cs *ring);
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u32 (*get_seqno)(struct intel_engine_cs *ring);
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2014-05-22 20:13:33 +07:00
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void (*set_seqno)(struct intel_engine_cs *ring,
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2012-12-19 16:13:05 +07:00
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u32 seqno);
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2015-05-29 23:44:02 +07:00
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int (*dispatch_execbuffer)(struct drm_i915_gem_request *req,
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2014-04-29 09:29:25 +07:00
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u64 offset, u32 length,
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2015-02-13 18:48:10 +07:00
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unsigned dispatch_flags);
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2012-10-17 18:09:54 +07:00
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#define I915_DISPATCH_SECURE 0x1
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2012-12-17 22:21:27 +07:00
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#define I915_DISPATCH_PINNED 0x2
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2015-06-16 17:39:40 +07:00
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#define I915_DISPATCH_RS 0x4
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2014-05-22 20:13:33 +07:00
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void (*cleanup)(struct intel_engine_cs *ring);
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2014-04-30 04:52:28 +07:00
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2014-06-30 23:53:37 +07:00
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/* GEN8 signal/wait table - never trust comments!
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* signal to signal to signal to signal to signal to
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
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* ie. transpose of g(x, y)
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*
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* sync from sync from sync from sync from sync from
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
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* ie. transpose of f(x, y)
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*/
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2014-04-30 04:52:28 +07:00
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struct {
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2016-03-16 18:00:39 +07:00
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u32 sync_seqno[I915_NUM_ENGINES-1];
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2014-04-30 04:52:29 +07:00
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2014-06-30 23:53:37 +07:00
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union {
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struct {
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/* our mbox written by others */
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2016-03-16 18:00:39 +07:00
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u32 wait[I915_NUM_ENGINES];
|
2014-06-30 23:53:37 +07:00
|
|
|
/* mboxes this ring signals to */
|
2016-03-16 18:00:39 +07:00
|
|
|
i915_reg_t signal[I915_NUM_ENGINES];
|
2014-06-30 23:53:37 +07:00
|
|
|
} mbox;
|
2016-03-16 18:00:39 +07:00
|
|
|
u64 signal_ggtt[I915_NUM_ENGINES];
|
2014-06-30 23:53:37 +07:00
|
|
|
};
|
2014-04-30 04:52:29 +07:00
|
|
|
|
|
|
|
/* AKA wait() */
|
2015-05-29 23:44:04 +07:00
|
|
|
int (*sync_to)(struct drm_i915_gem_request *to_req,
|
|
|
|
struct intel_engine_cs *from,
|
2014-04-30 04:52:29 +07:00
|
|
|
u32 seqno);
|
2015-05-29 23:44:05 +07:00
|
|
|
int (*signal)(struct drm_i915_gem_request *signaller_req,
|
2014-04-30 04:52:30 +07:00
|
|
|
/* num_dwords needed by caller */
|
|
|
|
unsigned int num_dwords);
|
2014-04-30 04:52:28 +07:00
|
|
|
} semaphore;
|
2013-05-29 09:22:18 +07:00
|
|
|
|
2014-07-24 23:04:27 +07:00
|
|
|
/* Execlists */
|
drm/i915: Move execlists irq handler to a bottom half
Doing a lot of work in the interrupt handler introduces huge
latencies to the system as a whole.
Most dramatic effect can be seen by running an all engine
stress test like igt/gem_exec_nop/all where, when the kernel
config is lean enough, the whole system can be brought into
multi-second periods of complete non-interactivty. That can
look for example like this:
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 23s! [kworker/u8:3:143]
Modules linked in: [redacted for brevity]
CPU: 0 PID: 143 Comm: kworker/u8:3 Tainted: G U L 4.5.0-160321+ #183
Hardware name: Intel Corporation Broadwell Client platform/WhiteTip Mountain 1
Workqueue: i915 gen6_pm_rps_work [i915]
task: ffff8800aae88000 ti: ffff8800aae90000 task.ti: ffff8800aae90000
RIP: 0010:[<ffffffff8104a3c2>] [<ffffffff8104a3c2>] __do_softirq+0x72/0x1d0
RSP: 0000:ffff88014f403f38 EFLAGS: 00000206
RAX: ffff8800aae94000 RBX: 0000000000000000 RCX: 00000000000006e0
RDX: 0000000000000020 RSI: 0000000004208060 RDI: 0000000000215d80
RBP: ffff88014f403f80 R08: 0000000b1b42c180 R09: 0000000000000022
R10: 0000000000000004 R11: 00000000ffffffff R12: 000000000000a030
R13: 0000000000000082 R14: ffff8800aa4d0080 R15: 0000000000000082
FS: 0000000000000000(0000) GS:ffff88014f400000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007fa53b90c000 CR3: 0000000001a0a000 CR4: 00000000001406f0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Stack:
042080601b33869f ffff8800aae94000 00000000fffc2678 ffff88010000000a
0000000000000000 000000000000a030 0000000000005302 ffff8800aa4d0080
0000000000000206 ffff88014f403f90 ffffffff8104a716 ffff88014f403fa8
Call Trace:
<IRQ>
[<ffffffff8104a716>] irq_exit+0x86/0x90
[<ffffffff81031e7d>] smp_apic_timer_interrupt+0x3d/0x50
[<ffffffff814f3eac>] apic_timer_interrupt+0x7c/0x90
<EOI>
[<ffffffffa01c5b40>] ? gen8_write64+0x1a0/0x1a0 [i915]
[<ffffffff814f2b39>] ? _raw_spin_unlock_irqrestore+0x9/0x20
[<ffffffffa01c5c44>] gen8_write32+0x104/0x1a0 [i915]
[<ffffffff8132c6a2>] ? n_tty_receive_buf_common+0x372/0xae0
[<ffffffffa017cc9e>] gen6_set_rps_thresholds+0x1be/0x330 [i915]
[<ffffffffa017eaf0>] gen6_set_rps+0x70/0x200 [i915]
[<ffffffffa0185375>] intel_set_rps+0x25/0x30 [i915]
[<ffffffffa01768fd>] gen6_pm_rps_work+0x10d/0x2e0 [i915]
[<ffffffff81063852>] ? finish_task_switch+0x72/0x1c0
[<ffffffff8105ab29>] process_one_work+0x139/0x350
[<ffffffff8105b186>] worker_thread+0x126/0x490
[<ffffffff8105b060>] ? rescuer_thread+0x320/0x320
[<ffffffff8105fa64>] kthread+0xc4/0xe0
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
[<ffffffff814f351f>] ret_from_fork+0x3f/0x70
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
I could not explain, or find a code path, which would explain
a +20 second lockup, but from some instrumentation it was
apparent the interrupts off proportion of time was between
10-25% under heavy load which is quite bad.
When a interrupt "cliff" is reached, which was >~320k irq/s on
my machine, the whole system goes into a terrible state of the
above described multi-second lockups.
By moving the GT interrupt handling to a tasklet in a most
simple way, the problem above disappears completely.
Testing the effect on sytem-wide latencies using
igt/gem_syslatency shows the following before this patch:
gem_syslatency: cycles=1532739, latency mean=416531.829us max=2499237us
gem_syslatency: cycles=1839434, latency mean=1458099.157us max=4998944us
gem_syslatency: cycles=1432570, latency mean=2688.451us max=1201185us
gem_syslatency: cycles=1533543, latency mean=416520.499us max=2498886us
This shows that the unrelated process is experiencing huge
delays in its wake-up latency. After the patch the results
look like this:
gem_syslatency: cycles=808907, latency mean=53.133us max=1640us
gem_syslatency: cycles=862154, latency mean=62.778us max=2117us
gem_syslatency: cycles=856039, latency mean=58.079us max=2123us
gem_syslatency: cycles=841683, latency mean=56.914us max=1667us
Showing a huge improvement in the unrelated process wake-up
latency. It also shows an approximate halving in the number
of total empty batches submitted during the test. This may
not be worrying since the test puts the driver under
a very unrealistic load with ncpu threads doing empty batch
submission to all GPU engines each.
Another benefit compared to the hard-irq handling is that now
work on all engines can be dispatched in parallel since we can
have up to number of CPUs active tasklets. (While previously
a single hard-irq would serially dispatch on one engine after
another.)
More interesting scenario with regards to throughput is
"gem_latency -n 100" which shows 25% better throughput and
CPU usage, and 14% better dispatch latencies.
I did not find any gains or regressions with Synmark2 or
GLbench under light testing. More benchmarking is certainly
required.
v2:
* execlists_lock should be taken as spin_lock_bh when
queuing work from userspace now. (Chris Wilson)
* uncore.lock must be taken with spin_lock_irq when
submitting requests since that now runs from either
softirq or process context.
v3:
* Expanded commit message with more testing data;
* converted missed locking sites to _bh;
* added execlist_lock comment. (Chris Wilson)
v4:
* Mention dispatch parallelism in commit. (Chris Wilson)
* Do not hold uncore.lock over MMIO reads since the block
is already serialised per-engine via the tasklet itself.
(Chris Wilson)
* intel_lrc_irq_handler should be static. (Chris Wilson)
* Cancel/sync the tasklet on GPU reset. (Chris Wilson)
* Document and WARN that tasklet cannot be active/pending
on engine cleanup. (Chris Wilson/Imre Deak)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Testcase: igt/gem_exec_nop/all
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94350
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1459768316-6670-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-04-04 18:11:56 +07:00
|
|
|
struct tasklet_struct irq_tasklet;
|
|
|
|
spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
|
2014-07-24 23:04:38 +07:00
|
|
|
struct list_head execlist_queue;
|
2016-04-12 20:37:31 +07:00
|
|
|
unsigned int fw_domains;
|
2016-02-26 23:58:32 +07:00
|
|
|
unsigned int next_context_status_buffer;
|
|
|
|
unsigned int idle_lite_restore_wa;
|
2016-01-15 22:10:27 +07:00
|
|
|
bool disable_lite_restore_wa;
|
|
|
|
u32 ctx_desc_template;
|
2014-07-24 23:04:31 +07:00
|
|
|
u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
|
2015-05-29 23:44:01 +07:00
|
|
|
int (*emit_request)(struct drm_i915_gem_request *request);
|
2015-05-29 23:43:59 +07:00
|
|
|
int (*emit_flush)(struct drm_i915_gem_request *request,
|
2014-07-24 23:04:28 +07:00
|
|
|
u32 invalidate_domains,
|
|
|
|
u32 flush_domains);
|
2015-05-29 23:44:03 +07:00
|
|
|
int (*emit_bb_start)(struct drm_i915_gem_request *req,
|
2015-02-13 18:48:10 +07:00
|
|
|
u64 offset, unsigned dispatch_flags);
|
2014-07-24 23:04:27 +07:00
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
/**
|
|
|
|
* List of objects currently involved in rendering from the
|
|
|
|
* ringbuffer.
|
|
|
|
*
|
|
|
|
* Includes buffers having the contents of their GPU caches
|
2014-11-25 01:49:26 +07:00
|
|
|
* flushed, not necessarily primitives. last_read_req
|
2010-05-21 08:08:55 +07:00
|
|
|
* represents when the rendering involved will be completed.
|
|
|
|
*
|
|
|
|
* A reference is held on the buffer while on this list.
|
|
|
|
*/
|
|
|
|
struct list_head active_list;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* List of breadcrumbs associated with GPU requests currently
|
|
|
|
* outstanding.
|
|
|
|
*/
|
|
|
|
struct list_head request_list;
|
|
|
|
|
2015-07-09 21:30:57 +07:00
|
|
|
/**
|
|
|
|
* Seqno of request most recently submitted to request_list.
|
|
|
|
* Used exclusively by hang checker to avoid grabbing lock while
|
|
|
|
* inspecting request list.
|
|
|
|
*/
|
|
|
|
u32 last_submitted_seqno;
|
2016-04-09 16:57:55 +07:00
|
|
|
unsigned user_interrupts;
|
2015-07-09 21:30:57 +07:00
|
|
|
|
2012-06-14 01:45:19 +07:00
|
|
|
bool gpu_caches_dirty;
|
2010-09-28 16:07:56 +07:00
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
wait_queue_head_t irq_queue;
|
2010-11-02 15:31:01 +07:00
|
|
|
|
2014-05-22 20:13:37 +07:00
|
|
|
struct intel_context *last_context;
|
2012-06-05 04:42:43 +07:00
|
|
|
|
2013-05-24 21:16:07 +07:00
|
|
|
struct intel_ring_hangcheck hangcheck;
|
|
|
|
|
2013-08-27 02:58:11 +07:00
|
|
|
struct {
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
u32 gtt_offset;
|
|
|
|
volatile u32 *cpu_page;
|
|
|
|
} scratch;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-05-11 04:10:43 +07:00
|
|
|
bool needs_cmd_parser;
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
/*
|
2014-05-11 04:10:43 +07:00
|
|
|
* Table of commands the command parser needs to know about
|
2014-02-19 01:15:46 +07:00
|
|
|
* for this ring.
|
|
|
|
*/
|
2014-05-11 04:10:43 +07:00
|
|
|
DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Table of registers allowed in commands that read/write registers.
|
|
|
|
*/
|
2016-03-07 14:30:27 +07:00
|
|
|
const struct drm_i915_reg_table *reg_tables;
|
|
|
|
int reg_table_count;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Returns the bitmask for the length field of the specified command.
|
|
|
|
* Return 0 for an unrecognized/invalid command.
|
|
|
|
*
|
|
|
|
* If the command parser finds an entry for a command in the ring's
|
|
|
|
* cmd_tables, it gets the command's length based on the table entry.
|
|
|
|
* If not, it calls this function to determine the per-ring length field
|
|
|
|
* encoding for the command (i.e. certain opcode ranges use certain bits
|
|
|
|
* to encode the command length in the header).
|
|
|
|
*/
|
|
|
|
u32 (*get_cmd_length_mask)(u32 cmd_header);
|
2010-05-21 08:08:55 +07:00
|
|
|
};
|
|
|
|
|
2015-12-08 22:02:36 +07:00
|
|
|
static inline bool
|
2016-03-16 18:00:40 +07:00
|
|
|
intel_engine_initialized(struct intel_engine_cs *engine)
|
2015-12-08 22:02:36 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
return engine->dev != NULL;
|
2015-12-08 22:02:36 +07:00
|
|
|
}
|
2012-05-11 20:29:30 +07:00
|
|
|
|
2011-12-14 19:57:00 +07:00
|
|
|
static inline unsigned
|
2016-03-16 18:00:39 +07:00
|
|
|
intel_engine_flag(struct intel_engine_cs *engine)
|
2011-12-14 19:57:00 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
return 1 << engine->id;
|
2011-12-14 19:57:00 +07:00
|
|
|
}
|
|
|
|
|
2010-12-04 18:30:53 +07:00
|
|
|
static inline u32
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_ring_sync_index(struct intel_engine_cs *engine,
|
2014-05-22 20:13:33 +07:00
|
|
|
struct intel_engine_cs *other)
|
2010-12-04 18:30:53 +07:00
|
|
|
{
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
/*
|
2014-06-30 23:51:11 +07:00
|
|
|
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
|
|
|
|
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
|
|
|
|
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
|
|
|
|
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
|
|
|
|
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
|
2010-12-04 18:30:53 +07:00
|
|
|
*/
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
idx = (other - engine) - 1;
|
2010-12-04 18:30:53 +07:00
|
|
|
if (idx < 0)
|
2016-03-16 18:00:39 +07:00
|
|
|
idx += I915_NUM_ENGINES;
|
2010-12-04 18:30:53 +07:00
|
|
|
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2015-08-14 22:35:27 +07:00
|
|
|
static inline void
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_flush_status_page(struct intel_engine_cs *engine, int reg)
|
2015-08-14 22:35:27 +07:00
|
|
|
{
|
2016-04-09 16:57:56 +07:00
|
|
|
mb();
|
|
|
|
clflush(&engine->status_page.page_addr[reg]);
|
|
|
|
mb();
|
2015-08-14 22:35:27 +07:00
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
static inline u32
|
2016-04-09 16:57:57 +07:00
|
|
|
intel_read_status_page(struct intel_engine_cs *engine, int reg)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2012-04-27 04:28:16 +07:00
|
|
|
/* Ensure that the compiler doesn't optimize away the load. */
|
2016-04-09 16:57:57 +07:00
|
|
|
return READ_ONCE(engine->status_page.page_addr[reg]);
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2012-12-19 16:13:05 +07:00
|
|
|
static inline void
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_write_status_page(struct intel_engine_cs *engine,
|
2012-12-19 16:13:05 +07:00
|
|
|
int reg, u32 value)
|
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.page_addr[reg] = value;
|
2012-12-19 16:13:05 +07:00
|
|
|
}
|
|
|
|
|
2016-01-18 14:19:47 +07:00
|
|
|
/*
|
2011-01-14 02:06:50 +07:00
|
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
|
|
* MI_STORE_DATA_IMM.
|
|
|
|
*
|
|
|
|
* The following dwords have a reserved meaning:
|
|
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
|
|
* 0x04: ring 0 head pointer
|
|
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
|
|
* 0x1f: Last written status offset. (GM45)
|
2015-02-18 18:48:21 +07:00
|
|
|
* 0x20-0x2f: Reserved (Gen6+)
|
2011-01-14 02:06:50 +07:00
|
|
|
*
|
2015-02-18 18:48:21 +07:00
|
|
|
* The area from dword 0x30 to 0x3ff is available for driver usage.
|
2011-01-14 02:06:50 +07:00
|
|
|
*/
|
2015-02-18 18:48:21 +07:00
|
|
|
#define I915_GEM_HWS_INDEX 0x30
|
2016-01-20 20:43:35 +07:00
|
|
|
#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
2015-02-18 18:48:21 +07:00
|
|
|
#define I915_GEM_HWS_SCRATCH_INDEX 0x40
|
2012-10-26 23:42:42 +07:00
|
|
|
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
2011-01-14 02:06:50 +07:00
|
|
|
|
2015-09-03 19:01:39 +07:00
|
|
|
struct intel_ringbuffer *
|
|
|
|
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
|
2014-11-13 17:28:56 +07:00
|
|
|
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
|
|
|
|
struct intel_ringbuffer *ringbuf);
|
2015-09-03 19:01:39 +07:00
|
|
|
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
|
|
|
|
void intel_ringbuffer_free(struct intel_ringbuffer *ring);
|
2014-07-24 23:04:15 +07:00
|
|
|
|
2016-03-16 18:00:40 +07:00
|
|
|
void intel_stop_engine(struct intel_engine_cs *engine);
|
|
|
|
void intel_cleanup_engine(struct intel_engine_cs *engine);
|
2011-03-20 08:14:27 +07:00
|
|
|
|
2015-03-19 19:30:08 +07:00
|
|
|
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
|
2015-05-29 23:44:06 +07:00
|
|
|
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
|
2016-03-16 18:00:37 +07:00
|
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static inline void intel_ring_emit(struct intel_engine_cs *engine,
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2010-10-27 18:18:21 +07:00
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u32 data)
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2010-08-04 21:18:14 +07:00
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{
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2016-03-16 18:00:37 +07:00
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struct intel_ringbuffer *ringbuf = engine->buffer;
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2014-05-22 20:13:36 +07:00
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iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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ringbuf->tail += 4;
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2010-08-04 21:18:14 +07:00
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}
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2016-03-16 18:00:37 +07:00
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static inline void intel_ring_emit_reg(struct intel_engine_cs *engine,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
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i915_reg_t reg)
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2015-11-05 04:20:07 +07:00
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{
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2016-03-16 18:00:37 +07:00
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intel_ring_emit(engine, i915_mmio_reg_offset(reg));
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2015-11-05 04:20:07 +07:00
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}
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2016-03-16 18:00:37 +07:00
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|
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static inline void intel_ring_advance(struct intel_engine_cs *engine)
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2013-08-11 04:16:32 +07:00
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|
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{
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2016-03-16 18:00:37 +07:00
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struct intel_ringbuffer *ringbuf = engine->buffer;
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2014-05-22 20:13:36 +07:00
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ringbuf->tail &= ringbuf->size - 1;
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2013-08-11 04:16:32 +07:00
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}
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2014-07-24 23:04:26 +07:00
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int __intel_ring_space(int head, int tail, int size);
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2014-11-27 18:22:49 +07:00
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void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
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2016-03-16 18:00:40 +07:00
|
|
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bool intel_engine_stopped(struct intel_engine_cs *engine);
|
2013-08-11 04:16:32 +07:00
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|
|
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2016-03-16 18:00:39 +07:00
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|
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int __must_check intel_engine_idle(struct intel_engine_cs *engine);
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2016-03-16 18:00:37 +07:00
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|
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void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno);
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2015-05-29 23:43:55 +07:00
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int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
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2015-05-29 23:43:53 +07:00
|
|
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int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
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void intel_fini_pipe_control(struct intel_engine_cs *engine);
|
|
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int intel_init_pipe_control(struct intel_engine_cs *engine);
|
2014-07-24 23:04:24 +07:00
|
|
|
|
2010-09-16 09:43:11 +07:00
|
|
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int intel_init_render_ring_buffer(struct drm_device *dev);
|
|
|
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
|
2014-04-17 09:37:37 +07:00
|
|
|
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
|
2010-10-19 17:19:32 +07:00
|
|
|
int intel_init_blt_ring_buffer(struct drm_device *dev);
|
2013-05-29 09:22:23 +07:00
|
|
|
int intel_init_vebox_ring_buffer(struct drm_device *dev);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
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u64 intel_ring_get_active_head(struct intel_engine_cs *engine);
|
2010-09-25 02:20:10 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
int init_workarounds_ring(struct intel_engine_cs *engine);
|
2014-11-11 23:47:33 +07:00
|
|
|
|
2014-07-03 22:28:04 +07:00
|
|
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static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
|
2012-02-15 18:25:36 +07:00
|
|
|
{
|
2014-07-03 22:28:04 +07:00
|
|
|
return ringbuf->tail;
|
2012-02-15 18:25:36 +07:00
|
|
|
}
|
|
|
|
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 19:10:09 +07:00
|
|
|
/*
|
|
|
|
* Arbitrary size for largest possible 'add request' sequence. The code paths
|
|
|
|
* are complex and variable. Empirical measurement shows that the worst case
|
|
|
|
* is ILK at 136 words. Reserving too much is better than reserving too little
|
|
|
|
* as that allows for corner cases that might have been missed. So the figure
|
|
|
|
* has been rounded up to 160 words.
|
|
|
|
*/
|
|
|
|
#define MIN_SPACE_FOR_ADD_REQUEST 160
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
#endif /* _INTEL_RINGBUFFER_H_ */
|