2010-05-21 08:08:55 +07:00
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#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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2014-05-11 04:10:43 +07:00
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#include <linux/hashtable.h>
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2015-04-07 22:20:36 +07:00
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#include "i915_gem_batch_pool.h"
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2014-05-11 04:10:43 +07:00
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#define I915_CMD_HASH_ORDER 9
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2014-07-24 23:04:28 +07:00
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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2015-06-20 01:07:01 +07:00
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#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
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2014-07-24 23:04:28 +07:00
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2012-12-03 23:43:32 +07:00
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/*
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
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* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
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* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
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*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
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* cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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#define I915_RING_FREE_SPACE 64
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2010-05-21 08:08:55 +07:00
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struct intel_hw_status_page {
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2012-04-27 04:28:16 +07:00
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u32 *page_addr;
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2010-05-21 08:08:55 +07:00
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unsigned int gfx_addr;
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2010-11-09 02:18:58 +07:00
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struct drm_i915_gem_object *obj;
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2010-05-21 08:08:55 +07:00
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};
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2011-04-26 01:22:22 +07:00
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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2010-11-09 16:17:32 +07:00
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2011-04-26 01:22:22 +07:00
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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2010-08-02 21:29:44 +07:00
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2014-03-12 18:09:41 +07:00
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#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
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2014-04-02 22:36:07 +07:00
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#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
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2014-03-12 18:09:41 +07:00
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2014-06-30 23:53:37 +07:00
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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#define i915_semaphore_seqno_size sizeof(uint64_t)
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#define GEN8_SIGNAL_OFFSET(__ring, to) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
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(i915_semaphore_seqno_size * (to)))
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#define GEN8_WAIT_OFFSET(__ring, from) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
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(i915_semaphore_seqno_size * (__ring)->id))
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#define GEN8_RING_SEMAPHORE_INIT do { \
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if (!dev_priv->semaphore_obj) { \
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break; \
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} \
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ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
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ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
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ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
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ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
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ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
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ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
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} while(0)
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2013-08-11 16:44:01 +07:00
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enum intel_ring_hangcheck_action {
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2013-09-06 20:03:28 +07:00
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HANGCHECK_IDLE = 0,
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2013-08-11 16:44:01 +07:00
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HANGCHECK_WAIT,
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HANGCHECK_ACTIVE,
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2014-08-05 21:16:26 +07:00
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HANGCHECK_ACTIVE_LOOP,
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2013-08-11 16:44:01 +07:00
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HANGCHECK_KICK,
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HANGCHECK_HUNG,
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};
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2013-06-12 16:35:32 +07:00
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2014-01-31 00:04:43 +07:00
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#define HANGCHECK_SCORE_RING_HUNG 31
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2013-05-24 21:16:07 +07:00
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struct intel_ring_hangcheck {
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2014-03-21 19:41:53 +07:00
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u64 acthd;
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2014-08-05 21:16:26 +07:00
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u64 max_acthd;
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2013-05-24 21:16:07 +07:00
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u32 seqno;
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2013-05-30 13:04:29 +07:00
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int score;
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2013-06-12 16:35:32 +07:00
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enum intel_ring_hangcheck_action action;
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2014-06-06 16:22:29 +07:00
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int deadlock;
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2013-05-24 21:16:07 +07:00
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};
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2014-05-22 20:13:34 +07:00
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struct intel_ringbuffer {
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struct drm_i915_gem_object *obj;
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void __iomem *virtual_start;
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2014-08-11 21:17:44 +07:00
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struct intel_engine_cs *ring;
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2014-05-22 20:13:34 +07:00
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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};
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2015-01-15 20:10:38 +07:00
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struct intel_context;
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2015-05-29 20:44:14 +07:00
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struct drm_i915_reg_descriptor;
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2015-01-15 20:10:38 +07:00
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2015-06-20 01:07:01 +07:00
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/*
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* we use a single page to load ctx workarounds so all of these
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* values are referred in terms of dwords
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*
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* struct i915_wa_ctx_bb:
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* offset: specifies batch starting position, also helpful in case
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* if we want to have multiple batches at different offsets based on
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* some criteria. It is not a requirement at the moment but provides
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* an option for future use.
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* size: size of the batch in DWORDS
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*/
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struct i915_ctx_workarounds {
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struct i915_wa_ctx_bb {
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u32 offset;
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u32 size;
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} indirect_ctx, per_ctx;
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struct drm_i915_gem_object *obj;
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};
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2014-05-22 20:13:33 +07:00
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struct intel_engine_cs {
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2010-05-21 08:08:55 +07:00
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const char *name;
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2010-09-18 17:02:01 +07:00
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enum intel_ring_id {
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2011-12-14 19:57:00 +07:00
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RCS = 0x0,
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VCS,
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BCS,
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2013-05-29 09:22:19 +07:00
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VECS,
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2014-04-17 09:37:37 +07:00
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VCS2
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2010-09-18 17:02:01 +07:00
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} id;
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2014-04-17 09:37:37 +07:00
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#define I915_NUM_RINGS 5
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2014-04-17 09:37:36 +07:00
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#define LAST_USER_RING (VECS + 1)
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2010-08-02 21:24:01 +07:00
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u32 mmio_base;
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2010-05-21 08:08:55 +07:00
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struct drm_device *dev;
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2014-05-22 20:13:34 +07:00
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struct intel_ringbuffer *buffer;
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2010-05-21 08:08:55 +07:00
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2015-04-07 22:20:36 +07:00
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/*
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* A pool of objects to use as shadow copies of client batch buffers
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* when the command parser is enabled. Prevents the client from
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* modifying the batch contents after software parsing.
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*/
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struct i915_gem_batch_pool batch_pool;
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2010-05-21 08:08:55 +07:00
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struct intel_hw_status_page status_page;
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2015-06-20 01:07:01 +07:00
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struct i915_ctx_workarounds wa_ctx;
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2010-05-21 08:08:55 +07:00
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2013-07-05 04:35:29 +07:00
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unsigned irq_refcount; /* protected by dev_priv->irq_lock */
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2012-04-12 03:12:46 +07:00
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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2014-11-25 01:49:39 +07:00
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struct drm_i915_gem_request *trace_irq_req;
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2014-05-22 20:13:33 +07:00
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bool __must_check (*irq_get)(struct intel_engine_cs *ring);
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void (*irq_put)(struct intel_engine_cs *ring);
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2010-05-21 08:08:55 +07:00
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2014-11-20 06:33:04 +07:00
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int (*init_hw)(struct intel_engine_cs *ring);
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2010-05-21 08:08:55 +07:00
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2014-11-11 23:47:33 +07:00
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int (*init_context)(struct intel_engine_cs *ring,
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struct intel_context *ctx);
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2014-08-26 20:44:50 +07:00
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2014-05-22 20:13:33 +07:00
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void (*write_tail)(struct intel_engine_cs *ring,
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2010-10-22 23:02:41 +07:00
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u32 value);
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2014-05-22 20:13:33 +07:00
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int __must_check (*flush)(struct intel_engine_cs *ring,
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2011-01-05 00:34:02 +07:00
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u32 invalidate_domains,
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u32 flush_domains);
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2014-05-22 20:13:33 +07:00
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int (*add_request)(struct intel_engine_cs *ring);
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2012-08-09 16:58:30 +07:00
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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2014-05-22 20:13:33 +07:00
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u32 (*get_seqno)(struct intel_engine_cs *ring,
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2012-08-09 16:58:30 +07:00
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bool lazy_coherency);
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2014-05-22 20:13:33 +07:00
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void (*set_seqno)(struct intel_engine_cs *ring,
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2012-12-19 16:13:05 +07:00
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u32 seqno);
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2014-05-22 20:13:33 +07:00
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int (*dispatch_execbuffer)(struct intel_engine_cs *ring,
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2014-04-29 09:29:25 +07:00
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u64 offset, u32 length,
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2015-02-13 18:48:10 +07:00
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unsigned dispatch_flags);
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2012-10-17 18:09:54 +07:00
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#define I915_DISPATCH_SECURE 0x1
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2012-12-17 22:21:27 +07:00
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#define I915_DISPATCH_PINNED 0x2
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2014-05-22 20:13:33 +07:00
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void (*cleanup)(struct intel_engine_cs *ring);
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2014-04-30 04:52:28 +07:00
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2014-06-30 23:53:37 +07:00
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/* GEN8 signal/wait table - never trust comments!
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* signal to signal to signal to signal to signal to
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
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* ie. transpose of g(x, y)
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*
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* sync from sync from sync from sync from sync from
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
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* ie. transpose of f(x, y)
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*/
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2014-04-30 04:52:28 +07:00
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struct {
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u32 sync_seqno[I915_NUM_RINGS-1];
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2014-04-30 04:52:29 +07:00
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2014-06-30 23:53:37 +07:00
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union {
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struct {
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/* our mbox written by others */
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u32 wait[I915_NUM_RINGS];
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/* mboxes this ring signals to */
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u32 signal[I915_NUM_RINGS];
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} mbox;
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u64 signal_ggtt[I915_NUM_RINGS];
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};
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2014-04-30 04:52:29 +07:00
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/* AKA wait() */
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2014-05-22 20:13:33 +07:00
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int (*sync_to)(struct intel_engine_cs *ring,
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struct intel_engine_cs *to,
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2014-04-30 04:52:29 +07:00
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u32 seqno);
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2014-05-22 20:13:33 +07:00
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int (*signal)(struct intel_engine_cs *signaller,
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2014-04-30 04:52:30 +07:00
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/* num_dwords needed by caller */
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unsigned int num_dwords);
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2014-04-30 04:52:28 +07:00
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} semaphore;
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2013-05-29 09:22:18 +07:00
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|
2014-07-24 23:04:27 +07:00
|
|
|
/* Execlists */
|
2014-07-24 23:04:38 +07:00
|
|
|
spinlock_t execlist_lock;
|
|
|
|
struct list_head execlist_queue;
|
2014-11-13 17:27:05 +07:00
|
|
|
struct list_head execlist_retired_req_list;
|
drm/i915/bdw: Handle context switch events
Handle all context status events in the context status buffer on every
context switch interrupt. We only remove work from the execlist queue
after a context status buffer reports that it has completed and we only
attempt to schedule new contexts on interrupt when a previously submitted
context completes (unless no contexts are queued, which means the GPU is
free).
We canot call intel_runtime_pm_get() in an interrupt (or with a spinlock
grabbed, FWIW), because it might sleep, which is not a nice thing to do.
Instead, do the runtime_pm get/put together with the create/destroy request,
and handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately, before trying to handle it (fix for
missing interrupts by Bob Beckett <robert.beckett@intel.com>).
- Update the Context Status Buffer Read Pointer, just in case (spotted
by Damien Lespiau).
v4: New namespace and multiple rebase changes.
v5: Squash with "drm/i915/bdw: Do not call intel_runtime_pm_get() in an
interrupt", as suggested by Daniel.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Checkpatch ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-24 23:04:39 +07:00
|
|
|
u8 next_context_status_buffer;
|
2014-07-24 23:04:31 +07:00
|
|
|
u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
|
2015-01-15 20:10:37 +07:00
|
|
|
int (*emit_request)(struct intel_ringbuffer *ringbuf,
|
|
|
|
struct drm_i915_gem_request *request);
|
2014-07-24 23:04:28 +07:00
|
|
|
int (*emit_flush)(struct intel_ringbuffer *ringbuf,
|
2015-01-15 20:10:38 +07:00
|
|
|
struct intel_context *ctx,
|
2014-07-24 23:04:28 +07:00
|
|
|
u32 invalidate_domains,
|
|
|
|
u32 flush_domains);
|
2014-07-24 23:04:32 +07:00
|
|
|
int (*emit_bb_start)(struct intel_ringbuffer *ringbuf,
|
2015-01-15 20:10:38 +07:00
|
|
|
struct intel_context *ctx,
|
2015-02-13 18:48:10 +07:00
|
|
|
u64 offset, unsigned dispatch_flags);
|
2014-07-24 23:04:27 +07:00
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
/**
|
|
|
|
* List of objects currently involved in rendering from the
|
|
|
|
* ringbuffer.
|
|
|
|
*
|
|
|
|
* Includes buffers having the contents of their GPU caches
|
2014-11-25 01:49:26 +07:00
|
|
|
* flushed, not necessarily primitives. last_read_req
|
2010-05-21 08:08:55 +07:00
|
|
|
* represents when the rendering involved will be completed.
|
|
|
|
*
|
|
|
|
* A reference is held on the buffer while on this list.
|
|
|
|
*/
|
|
|
|
struct list_head active_list;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* List of breadcrumbs associated with GPU requests currently
|
|
|
|
* outstanding.
|
|
|
|
*/
|
|
|
|
struct list_head request_list;
|
|
|
|
|
2010-09-28 16:07:56 +07:00
|
|
|
/**
|
|
|
|
* Do we have some not yet emitted requests outstanding?
|
|
|
|
*/
|
2014-11-25 01:49:29 +07:00
|
|
|
struct drm_i915_gem_request *outstanding_lazy_request;
|
2012-06-14 01:45:19 +07:00
|
|
|
bool gpu_caches_dirty;
|
2010-09-28 16:07:56 +07:00
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
wait_queue_head_t irq_queue;
|
2010-11-02 15:31:01 +07:00
|
|
|
|
2014-05-22 20:13:37 +07:00
|
|
|
struct intel_context *default_context;
|
|
|
|
struct intel_context *last_context;
|
2012-06-05 04:42:43 +07:00
|
|
|
|
2013-05-24 21:16:07 +07:00
|
|
|
struct intel_ring_hangcheck hangcheck;
|
|
|
|
|
2013-08-27 02:58:11 +07:00
|
|
|
struct {
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
u32 gtt_offset;
|
|
|
|
volatile u32 *cpu_page;
|
|
|
|
} scratch;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-05-11 04:10:43 +07:00
|
|
|
bool needs_cmd_parser;
|
|
|
|
|
2014-02-19 01:15:46 +07:00
|
|
|
/*
|
2014-05-11 04:10:43 +07:00
|
|
|
* Table of commands the command parser needs to know about
|
2014-02-19 01:15:46 +07:00
|
|
|
* for this ring.
|
|
|
|
*/
|
2014-05-11 04:10:43 +07:00
|
|
|
DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
|
2014-02-19 01:15:46 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Table of registers allowed in commands that read/write registers.
|
|
|
|
*/
|
2015-05-29 20:44:14 +07:00
|
|
|
const struct drm_i915_reg_descriptor *reg_table;
|
2014-02-19 01:15:46 +07:00
|
|
|
int reg_count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Table of registers allowed in commands that read/write registers, but
|
|
|
|
* only from the DRM master.
|
|
|
|
*/
|
2015-05-29 20:44:14 +07:00
|
|
|
const struct drm_i915_reg_descriptor *master_reg_table;
|
2014-02-19 01:15:46 +07:00
|
|
|
int master_reg_count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Returns the bitmask for the length field of the specified command.
|
|
|
|
* Return 0 for an unrecognized/invalid command.
|
|
|
|
*
|
|
|
|
* If the command parser finds an entry for a command in the ring's
|
|
|
|
* cmd_tables, it gets the command's length based on the table entry.
|
|
|
|
* If not, it calls this function to determine the per-ring length field
|
|
|
|
* encoding for the command (i.e. certain opcode ranges use certain bits
|
|
|
|
* to encode the command length in the header).
|
|
|
|
*/
|
|
|
|
u32 (*get_cmd_length_mask)(u32 cmd_header);
|
2010-05-21 08:08:55 +07:00
|
|
|
};
|
|
|
|
|
2014-07-24 23:04:23 +07:00
|
|
|
bool intel_ring_initialized(struct intel_engine_cs *ring);
|
2012-05-11 20:29:30 +07:00
|
|
|
|
2011-12-14 19:57:00 +07:00
|
|
|
static inline unsigned
|
2014-05-22 20:13:33 +07:00
|
|
|
intel_ring_flag(struct intel_engine_cs *ring)
|
2011-12-14 19:57:00 +07:00
|
|
|
{
|
|
|
|
return 1 << ring->id;
|
|
|
|
}
|
|
|
|
|
2010-12-04 18:30:53 +07:00
|
|
|
static inline u32
|
2014-05-22 20:13:33 +07:00
|
|
|
intel_ring_sync_index(struct intel_engine_cs *ring,
|
|
|
|
struct intel_engine_cs *other)
|
2010-12-04 18:30:53 +07:00
|
|
|
{
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
/*
|
2014-06-30 23:51:11 +07:00
|
|
|
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
|
|
|
|
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
|
|
|
|
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
|
|
|
|
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
|
|
|
|
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
|
2010-12-04 18:30:53 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
idx = (other - ring) - 1;
|
|
|
|
if (idx < 0)
|
|
|
|
idx += I915_NUM_RINGS;
|
|
|
|
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
static inline u32
|
2014-05-22 20:13:33 +07:00
|
|
|
intel_read_status_page(struct intel_engine_cs *ring,
|
2010-10-27 18:18:21 +07:00
|
|
|
int reg)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2012-04-27 04:28:16 +07:00
|
|
|
/* Ensure that the compiler doesn't optimize away the load. */
|
|
|
|
barrier();
|
|
|
|
return ring->status_page.page_addr[reg];
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2012-12-19 16:13:05 +07:00
|
|
|
static inline void
|
2014-05-22 20:13:33 +07:00
|
|
|
intel_write_status_page(struct intel_engine_cs *ring,
|
2012-12-19 16:13:05 +07:00
|
|
|
int reg, u32 value)
|
|
|
|
{
|
|
|
|
ring->status_page.page_addr[reg] = value;
|
|
|
|
}
|
|
|
|
|
2011-01-14 02:06:50 +07:00
|
|
|
/**
|
|
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
|
|
* MI_STORE_DATA_IMM.
|
|
|
|
*
|
|
|
|
* The following dwords have a reserved meaning:
|
|
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
|
|
* 0x04: ring 0 head pointer
|
|
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
|
|
* 0x1f: Last written status offset. (GM45)
|
2015-02-18 18:48:21 +07:00
|
|
|
* 0x20-0x2f: Reserved (Gen6+)
|
2011-01-14 02:06:50 +07:00
|
|
|
*
|
2015-02-18 18:48:21 +07:00
|
|
|
* The area from dword 0x30 to 0x3ff is available for driver usage.
|
2011-01-14 02:06:50 +07:00
|
|
|
*/
|
2015-02-18 18:48:21 +07:00
|
|
|
#define I915_GEM_HWS_INDEX 0x30
|
|
|
|
#define I915_GEM_HWS_SCRATCH_INDEX 0x40
|
2012-10-26 23:42:42 +07:00
|
|
|
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
|
2011-01-14 02:06:50 +07:00
|
|
|
|
2014-11-13 17:28:56 +07:00
|
|
|
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
|
|
|
|
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
|
|
|
|
struct intel_ringbuffer *ringbuf);
|
2014-07-24 23:04:15 +07:00
|
|
|
void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
|
|
|
|
int intel_alloc_ringbuffer_obj(struct drm_device *dev,
|
|
|
|
struct intel_ringbuffer *ringbuf);
|
|
|
|
|
2014-05-22 20:13:33 +07:00
|
|
|
void intel_stop_ring_buffer(struct intel_engine_cs *ring);
|
|
|
|
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
|
2011-03-20 08:14:27 +07:00
|
|
|
|
2015-03-19 19:30:08 +07:00
|
|
|
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
|
|
|
|
|
2014-05-22 20:13:33 +07:00
|
|
|
int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
|
|
|
|
int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
|
|
|
|
static inline void intel_ring_emit(struct intel_engine_cs *ring,
|
2010-10-27 18:18:21 +07:00
|
|
|
u32 data)
|
2010-08-04 21:18:14 +07:00
|
|
|
{
|
2014-05-22 20:13:36 +07:00
|
|
|
struct intel_ringbuffer *ringbuf = ring->buffer;
|
|
|
|
iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
|
|
|
|
ringbuf->tail += 4;
|
2010-08-04 21:18:14 +07:00
|
|
|
}
|
2014-05-22 20:13:33 +07:00
|
|
|
static inline void intel_ring_advance(struct intel_engine_cs *ring)
|
2013-08-11 04:16:32 +07:00
|
|
|
{
|
2014-05-22 20:13:36 +07:00
|
|
|
struct intel_ringbuffer *ringbuf = ring->buffer;
|
|
|
|
ringbuf->tail &= ringbuf->size - 1;
|
2013-08-11 04:16:32 +07:00
|
|
|
}
|
2014-07-24 23:04:26 +07:00
|
|
|
int __intel_ring_space(int head, int tail, int size);
|
2014-11-27 18:22:49 +07:00
|
|
|
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
|
2014-07-24 23:04:26 +07:00
|
|
|
int intel_ring_space(struct intel_ringbuffer *ringbuf);
|
|
|
|
bool intel_ring_stopped(struct intel_engine_cs *ring);
|
2014-05-22 20:13:33 +07:00
|
|
|
void __intel_ring_advance(struct intel_engine_cs *ring);
|
2013-08-11 04:16:32 +07:00
|
|
|
|
2014-05-22 20:13:33 +07:00
|
|
|
int __must_check intel_ring_idle(struct intel_engine_cs *ring);
|
|
|
|
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
|
|
|
|
int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
|
|
|
|
int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2014-07-24 23:04:24 +07:00
|
|
|
void intel_fini_pipe_control(struct intel_engine_cs *ring);
|
|
|
|
int intel_init_pipe_control(struct intel_engine_cs *ring);
|
|
|
|
|
2010-09-16 09:43:11 +07:00
|
|
|
int intel_init_render_ring_buffer(struct drm_device *dev);
|
|
|
|
int intel_init_bsd_ring_buffer(struct drm_device *dev);
|
2014-04-17 09:37:37 +07:00
|
|
|
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
|
2010-10-19 17:19:32 +07:00
|
|
|
int intel_init_blt_ring_buffer(struct drm_device *dev);
|
2013-05-29 09:22:23 +07:00
|
|
|
int intel_init_vebox_ring_buffer(struct drm_device *dev);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2014-05-22 20:13:33 +07:00
|
|
|
u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
|
2010-09-25 02:20:10 +07:00
|
|
|
|
2014-11-11 23:47:33 +07:00
|
|
|
int init_workarounds_ring(struct intel_engine_cs *ring);
|
|
|
|
|
2014-07-03 22:28:04 +07:00
|
|
|
static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
|
2012-02-15 18:25:36 +07:00
|
|
|
{
|
2014-07-03 22:28:04 +07:00
|
|
|
return ringbuf->tail;
|
2012-02-15 18:25:36 +07:00
|
|
|
}
|
|
|
|
|
2014-11-25 01:49:25 +07:00
|
|
|
static inline struct drm_i915_gem_request *
|
|
|
|
intel_ring_get_request(struct intel_engine_cs *ring)
|
|
|
|
{
|
2014-11-25 01:49:29 +07:00
|
|
|
BUG_ON(ring->outstanding_lazy_request == NULL);
|
|
|
|
return ring->outstanding_lazy_request;
|
2014-11-25 01:49:25 +07:00
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
#endif /* _INTEL_RINGBUFFER_H_ */
|