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linux_dsm_epyc7002/arch/m68k/include/asm/m5407sim.h

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
/****************************************************************************/
/*
* m5407sim.h -- ColdFire 5407 System Integration Module support.
*
* (C) Copyright 2000, Lineo (www.lineo.com)
* (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
*
* Modified by David W. Miller for the MCF5307 Eval Board.
*/
/****************************************************************************/
#ifndef m5407sim_h
#define m5407sim_h
/****************************************************************************/
m68knommu: fix clock rate value reported for ColdFire 54xx parts The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 14:40:37 +07:00
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
m68knommu: remove ColdFire CLOCK_DIV config option The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 11:19:08 +07:00
#define MCF_BUSCLK (MCF_CLK / 2)
m68knommu: move ColdFire CPU names into their headers Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-02 14:13:27 +07:00
m68knommu: move inclusion of ColdFire v4 cache registers Move the inclusion of the version 4 cache controller registers so that it is with all the other register bit flag definitions. This makes it consistent with the other version core inclusion points, and means we don't need "#ifdef"ery in odd-ball places for these definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-09 07:40:44 +07:00
#include <asm/m54xxacr.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
/*
* Define the 5407 SIM register set addresses.
*/
m68knommu: make ColdFire SYPCR and RSR register definitions absolute addresses Make all definitions of the ColdFire Reset and System registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the abolsute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-07-15 18:55:01 +07:00
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
m68knommu: make ColdFire watchdog register definitions absolute addresses Make all definitions of the ColdFire Software watchdog registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-07-15 19:01:08 +07:00
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
m68knommu: make ColdFire Pin Assignment register definitions absolute addresses Make all definitions of the ColdFire Pin Assignment registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-08-17 13:20:23 +07:00
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
m68knommu: make ColdFire Park and Assignment register definitions absolute addresses Make all definitions of the ColdFire MPARK and IRQ Assignment registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 13:09:59 +07:00
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
m68knommu: make ColdFire IMR and IPR register definitions absolute addresses Make all definitions of the ColdFire Interrupt Mask and Pending registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-07-15 18:42:47 +07:00
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
m68knommu: make ColdFire Interrupt Source register definitions absolute addresses Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-08-17 13:48:16 +07:00
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: make ColdFire Chip Select register definitions absolute addresses Make all definitions of the ColdFire Chip Select registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 12:36:02 +07:00
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: make ColdFire Chip Select register definitions absolute addresses Make all definitions of the ColdFire Chip Select registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-14 12:36:02 +07:00
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: clean up use of MBAR for DRAM registers on ColdFire start In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-06 20:01:46 +07:00
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: remove use of MBAR in old-style ColdFire timer Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-09 06:57:14 +07:00
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
m68knommu: make 5407 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5407 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 21:43:13 +07:00
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
m68knommu: move UART addressing to part specific includes The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2010-11-03 09:50:30 +07:00
generic GPIO support for the Freescale Coldfire 5407. Add support for the 5407. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 08:11:11 +07:00
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: move ColdFire DMA register addresses to per-cpu headers The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-03-05 21:54:36 +07:00
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
generic GPIO support for the Freescale Coldfire 5407. Add support for the 5407. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-06-20 08:11:11 +07:00
/*
* Generic GPIO support
*/
m68knommu: fix inconsistent formating in ColdFire 5407 definitions Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-18 12:50:48 +07:00
#define MCFGPIO_PIN_MAX 16
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
/* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
/* Clear to select par I/O */
/*
* Defines for the IRQPAR Register
*/
m68knommu: fix inconsistent formating in ColdFire 5407 definitions Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-18 12:50:48 +07:00
#define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
m68knommu: simplify ColdFire "timers" clock initialization The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-05-19 11:52:40 +07:00
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
m68knommu: make 5407 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5407 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2011-12-23 21:43:13 +07:00
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
/****************************************************************************/
#endif /* m5407sim_h */
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