2022-10-25 00:08:22 +07:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 Intel Corporation */
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#include "igc.h"
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/ptp_classify.h>
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#include <linux/clocksource.h>
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#include <linux/ktime.h>
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#define INCVALUE_MASK 0x7fffffff
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#define ISGN 0x80000000
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#define IGC_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
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#define IGC_PTP_TX_TIMEOUT (HZ * 15)
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2022-10-26 02:28:02 +07:00
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#define netdev_level_once(level, dev, fmt, ...) \
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do { \
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static bool __print_once __read_mostly; \
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\
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if (!__print_once) { \
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__print_once = true; \
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netdev_printk(level, dev, fmt, ##__VA_ARGS__); \
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} \
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} while (0)
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#define netdev_emerg_once(dev, fmt, ...) \
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netdev_level_once(KERN_EMERG, dev, fmt, ##__VA_ARGS__)
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#define netdev_alert_once(dev, fmt, ...) \
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netdev_level_once(KERN_ALERT, dev, fmt, ##__VA_ARGS__)
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#define netdev_crit_once(dev, fmt, ...) \
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netdev_level_once(KERN_CRIT, dev, fmt, ##__VA_ARGS__)
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#define netdev_err_once(dev, fmt, ...) \
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netdev_level_once(KERN_ERR, dev, fmt, ##__VA_ARGS__)
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#define netdev_warn_once(dev, fmt, ...) \
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netdev_level_once(KERN_WARNING, dev, fmt, ##__VA_ARGS__)
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#define netdev_notice_once(dev, fmt, ...) \
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netdev_level_once(KERN_NOTICE, dev, fmt, ##__VA_ARGS__)
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#define netdev_info_once(dev, fmt, ...) \
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netdev_level_once(KERN_INFO, dev, fmt, ##__VA_ARGS__)
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2022-10-25 00:08:22 +07:00
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/* SYSTIM read access for I225 */
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void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 sec, nsec;
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/* The timestamp is latched when SYSTIML is read. */
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nsec = rd32(IGC_SYSTIML);
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sec = rd32(IGC_SYSTIMH);
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ts->tv_sec = sec;
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ts->tv_nsec = nsec;
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}
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static void igc_ptp_write_i225(struct igc_adapter *adapter,
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const struct timespec64 *ts)
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{
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struct igc_hw *hw = &adapter->hw;
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wr32(IGC_SYSTIML, ts->tv_nsec);
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wr32(IGC_SYSTIMH, ts->tv_sec);
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}
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static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
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ptp_caps);
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struct igc_hw *hw = &igc->hw;
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int neg_adj = 0;
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u64 rate;
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u32 inca;
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if (scaled_ppm < 0) {
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neg_adj = 1;
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scaled_ppm = -scaled_ppm;
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}
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rate = scaled_ppm;
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rate <<= 14;
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rate = div_u64(rate, 78125);
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inca = rate & INCVALUE_MASK;
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if (neg_adj)
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inca |= ISGN;
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wr32(IGC_TIMINCA, inca);
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return 0;
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}
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static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
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{
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struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
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ptp_caps);
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struct timespec64 now, then = ns_to_timespec64(delta);
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unsigned long flags;
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spin_lock_irqsave(&igc->tmreg_lock, flags);
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igc_ptp_read(igc, &now);
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now = timespec64_add(now, then);
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igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
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spin_unlock_irqrestore(&igc->tmreg_lock, flags);
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return 0;
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}
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static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
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2022-10-26 02:28:02 +07:00
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struct timespec64 *ts)
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2022-10-25 00:08:22 +07:00
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{
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struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
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ptp_caps);
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struct igc_hw *hw = &igc->hw;
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unsigned long flags;
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spin_lock_irqsave(&igc->tmreg_lock, flags);
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ts->tv_nsec = rd32(IGC_SYSTIML);
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ts->tv_sec = rd32(IGC_SYSTIMH);
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spin_unlock_irqrestore(&igc->tmreg_lock, flags);
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return 0;
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}
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static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
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ptp_caps);
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unsigned long flags;
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spin_lock_irqsave(&igc->tmreg_lock, flags);
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igc_ptp_write_i225(igc, ts);
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spin_unlock_irqrestore(&igc->tmreg_lock, flags);
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return 0;
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}
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static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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return -EOPNOTSUPP;
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}
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/**
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* igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
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* @adapter: board private structure
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* @hwtstamps: timestamp structure to update
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* @systim: unsigned 64bit system time value
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*
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* We need to convert the system time value stored in the RX/TXSTMP registers
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* into a hwtstamp which can be used by the upper level timestamping functions.
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**/
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static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
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struct skb_shared_hwtstamps *hwtstamps,
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u64 systim)
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{
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switch (adapter->hw.mac.type) {
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case igc_i225:
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memset(hwtstamps, 0, sizeof(*hwtstamps));
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/* Upper 32 bits contain s, lower 32 bits contain ns. */
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hwtstamps->hwtstamp = ktime_set(systim >> 32,
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systim & 0xFFFFFFFF);
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break;
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default:
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break;
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}
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}
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/**
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* igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
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* @q_vector: Pointer to interrupt specific structure
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* @va: Pointer to address containing Rx buffer
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* @skb: Buffer containing timestamp and packet
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*
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* This function retrieves the timestamp saved in the beginning of packet
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* buffer. While two timestamps are available, one in timer0 reference and the
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* other in timer1 reference, this function considers only the timestamp in
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* timer0 reference.
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*/
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void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, __le32 *va,
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struct sk_buff *skb)
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{
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struct igc_adapter *adapter = q_vector->adapter;
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u64 regval;
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int adjust;
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/* Timestamps are saved in little endian at the beginning of the packet
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* buffer following the layout:
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*
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* DWORD: | 0 | 1 | 2 | 3 |
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* Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
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*
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* SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
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* part of the timestamp.
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*/
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regval = le32_to_cpu(va[2]);
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regval |= (u64)le32_to_cpu(va[3]) << 32;
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igc_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
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/* Adjust timestamp for the RX latency based on link speed */
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switch (adapter->link_speed) {
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case SPEED_10:
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adjust = IGC_I225_RX_LATENCY_10;
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break;
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case SPEED_100:
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adjust = IGC_I225_RX_LATENCY_100;
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break;
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case SPEED_1000:
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adjust = IGC_I225_RX_LATENCY_1000;
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break;
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case SPEED_2500:
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adjust = IGC_I225_RX_LATENCY_2500;
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break;
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default:
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adjust = 0;
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netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
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break;
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}
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skb_hwtstamps(skb)->hwtstamp =
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ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
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}
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static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 val;
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int i;
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wr32(IGC_TSYNCRXCTL, 0);
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for (i = 0; i < adapter->num_rx_queues; i++) {
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val = rd32(IGC_SRRCTL(i));
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val &= ~IGC_SRRCTL_TIMESTAMP;
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wr32(IGC_SRRCTL(i), val);
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}
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val = rd32(IGC_RXPBS);
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val &= ~IGC_RXPBS_CFG_TS_EN;
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wr32(IGC_RXPBS, val);
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}
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static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 val;
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int i;
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val = rd32(IGC_RXPBS);
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val |= IGC_RXPBS_CFG_TS_EN;
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wr32(IGC_RXPBS, val);
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for (i = 0; i < adapter->num_rx_queues; i++) {
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val = rd32(IGC_SRRCTL(i));
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/* FIXME: For now, only support retrieving RX timestamps from
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* timer 0.
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*/
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val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
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IGC_SRRCTL_TIMESTAMP;
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wr32(IGC_SRRCTL(i), val);
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}
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val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
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IGC_TSYNCRXCTL_RXSYNSIG;
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wr32(IGC_TSYNCRXCTL, val);
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}
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static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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wr32(IGC_TSYNCTXCTL, 0);
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}
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static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
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/* Read TXSTMP registers to discard any timestamp previously stored. */
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rd32(IGC_TXSTMPL);
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rd32(IGC_TXSTMPH);
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}
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/**
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* igc_ptp_set_timestamp_mode - setup hardware for timestamping
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* @adapter: networking device structure
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* @config: hwtstamp configuration
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*
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* Return: 0 in case of success, negative errno code otherwise.
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*/
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static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
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struct hwtstamp_config *config)
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{
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/* reserved for future extensions */
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if (config->flags)
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return -EINVAL;
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switch (config->tx_type) {
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case HWTSTAMP_TX_OFF:
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igc_ptp_disable_tx_timestamp(adapter);
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break;
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case HWTSTAMP_TX_ON:
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igc_ptp_enable_tx_timestamp(adapter);
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break;
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default:
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return -ERANGE;
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}
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switch (config->rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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igc_ptp_disable_rx_timestamp(adapter);
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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2022-10-26 02:28:02 +07:00
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// case HWTSTAMP_FILTER_NTP_ALL:
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2022-10-25 00:08:22 +07:00
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case HWTSTAMP_FILTER_ALL:
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igc_ptp_enable_rx_timestamp(adapter);
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config->rx_filter = HWTSTAMP_FILTER_ALL;
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break;
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default:
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return -ERANGE;
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}
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return 0;
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}
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static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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dev_kfree_skb_any(adapter->ptp_tx_skb);
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adapter->ptp_tx_skb = NULL;
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adapter->tx_hwtstamp_timeouts++;
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clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
|
|
|
|
/* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
|
|
|
|
rd32(IGC_TXSTMPH);
|
|
|
|
netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void igc_ptp_tx_hang(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
|
|
|
|
IGC_PTP_TX_TIMEOUT);
|
|
|
|
|
|
|
|
if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* If we haven't received a timestamp within the timeout, it is
|
|
|
|
* reasonable to assume that it will never occur, so we can unlock the
|
|
|
|
* timestamp bit when this occurs.
|
|
|
|
*/
|
|
|
|
if (timeout) {
|
|
|
|
cancel_work_sync(&adapter->ptp_tx_work);
|
|
|
|
igc_ptp_tx_timeout(adapter);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
|
|
|
|
* @adapter: Board private structure
|
|
|
|
*
|
|
|
|
* If we were asked to do hardware stamping and such a time stamp is
|
|
|
|
* available, then it must have been for this skb here because we only
|
|
|
|
* allow only one such packet into the queue.
|
|
|
|
*/
|
|
|
|
static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct sk_buff *skb = adapter->ptp_tx_skb;
|
|
|
|
struct skb_shared_hwtstamps shhwtstamps;
|
|
|
|
struct igc_hw *hw = &adapter->hw;
|
|
|
|
int adjust = 0;
|
|
|
|
u64 regval;
|
|
|
|
|
|
|
|
if (WARN_ON_ONCE(!skb))
|
|
|
|
return;
|
|
|
|
|
|
|
|
regval = rd32(IGC_TXSTMPL);
|
|
|
|
regval |= (u64)rd32(IGC_TXSTMPH) << 32;
|
|
|
|
igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
|
|
|
|
|
|
|
|
switch (adapter->link_speed) {
|
|
|
|
case SPEED_10:
|
|
|
|
adjust = IGC_I225_TX_LATENCY_10;
|
|
|
|
break;
|
|
|
|
case SPEED_100:
|
|
|
|
adjust = IGC_I225_TX_LATENCY_100;
|
|
|
|
break;
|
|
|
|
case SPEED_1000:
|
|
|
|
adjust = IGC_I225_TX_LATENCY_1000;
|
|
|
|
break;
|
|
|
|
case SPEED_2500:
|
|
|
|
adjust = IGC_I225_TX_LATENCY_2500;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
shhwtstamps.hwtstamp =
|
|
|
|
ktime_add_ns(shhwtstamps.hwtstamp, adjust);
|
|
|
|
|
|
|
|
/* Clear the lock early before calling skb_tstamp_tx so that
|
|
|
|
* applications are not woken up before the lock bit is clear. We use
|
|
|
|
* a copy of the skb pointer to ensure other threads can't change it
|
|
|
|
* while we're notifying the stack.
|
|
|
|
*/
|
|
|
|
adapter->ptp_tx_skb = NULL;
|
|
|
|
clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
|
|
|
|
|
|
|
|
/* Notify the stack and free the skb after we've unlocked */
|
|
|
|
skb_tstamp_tx(skb, &shhwtstamps);
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_tx_work
|
|
|
|
* @work: pointer to work struct
|
|
|
|
*
|
|
|
|
* This work function polls the TSYNCTXCTL valid bit to determine when a
|
|
|
|
* timestamp has been taken for the current stored skb.
|
|
|
|
*/
|
|
|
|
static void igc_ptp_tx_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct igc_adapter *adapter = container_of(work, struct igc_adapter,
|
|
|
|
ptp_tx_work);
|
|
|
|
struct igc_hw *hw = &adapter->hw;
|
|
|
|
u32 tsynctxctl;
|
|
|
|
|
|
|
|
if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
|
|
|
|
return;
|
|
|
|
|
|
|
|
tsynctxctl = rd32(IGC_TSYNCTXCTL);
|
|
|
|
if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
|
|
|
|
return;
|
|
|
|
|
|
|
|
igc_ptp_tx_hwtstamp(adapter);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_set_ts_config - set hardware time stamping config
|
|
|
|
* @netdev: network interface device structure
|
|
|
|
* @ifr: interface request data
|
|
|
|
*
|
|
|
|
**/
|
|
|
|
int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
|
|
|
|
{
|
|
|
|
struct igc_adapter *adapter = netdev_priv(netdev);
|
|
|
|
struct hwtstamp_config config;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
err = igc_ptp_set_timestamp_mode(adapter, &config);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* save these settings for future reference */
|
|
|
|
memcpy(&adapter->tstamp_config, &config,
|
|
|
|
sizeof(adapter->tstamp_config));
|
|
|
|
|
|
|
|
return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
|
|
|
|
-EFAULT : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_get_ts_config - get hardware time stamping config
|
|
|
|
* @netdev: network interface device structure
|
|
|
|
* @ifr: interface request data
|
|
|
|
*
|
|
|
|
* Get the hwtstamp_config settings to return to the user. Rather than attempt
|
|
|
|
* to deconstruct the settings from the registers, just return a shadow copy
|
|
|
|
* of the last known settings.
|
|
|
|
**/
|
|
|
|
int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
|
|
|
|
{
|
|
|
|
struct igc_adapter *adapter = netdev_priv(netdev);
|
|
|
|
struct hwtstamp_config *config = &adapter->tstamp_config;
|
|
|
|
|
|
|
|
return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
|
|
|
|
-EFAULT : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_init - Initialize PTP functionality
|
|
|
|
* @adapter: Board private structure
|
|
|
|
*
|
|
|
|
* This function is called at device probe to initialize the PTP
|
|
|
|
* functionality.
|
|
|
|
*/
|
|
|
|
void igc_ptp_init(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct net_device *netdev = adapter->netdev;
|
|
|
|
struct igc_hw *hw = &adapter->hw;
|
|
|
|
|
|
|
|
switch (hw->mac.type) {
|
|
|
|
case igc_i225:
|
|
|
|
snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
|
|
|
|
adapter->ptp_caps.owner = THIS_MODULE;
|
|
|
|
adapter->ptp_caps.max_adj = 62499999;
|
2022-10-26 02:28:02 +07:00
|
|
|
// adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
|
2022-10-25 00:08:22 +07:00
|
|
|
adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
|
2022-10-26 02:28:02 +07:00
|
|
|
adapter->ptp_caps.gettime64 = igc_ptp_gettimex64_i225;
|
2022-10-25 00:08:22 +07:00
|
|
|
adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
|
|
|
|
adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
adapter->ptp_clock = NULL;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_init(&adapter->tmreg_lock);
|
|
|
|
INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
|
|
|
|
|
|
|
|
adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
|
|
|
|
adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
|
|
|
|
|
|
|
|
adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
|
|
|
|
adapter->ptp_reset_start = ktime_get();
|
|
|
|
|
|
|
|
adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
|
|
|
|
&adapter->pdev->dev);
|
|
|
|
if (IS_ERR(adapter->ptp_clock)) {
|
|
|
|
adapter->ptp_clock = NULL;
|
|
|
|
netdev_err(netdev, "ptp_clock_register failed\n");
|
|
|
|
} else if (adapter->ptp_clock) {
|
|
|
|
netdev_info(netdev, "PHC added\n");
|
|
|
|
adapter->ptp_flags |= IGC_PTP_ENABLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void igc_ptp_time_save(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
igc_ptp_read(adapter, &adapter->prev_ptp_time);
|
|
|
|
adapter->ptp_reset_start = ktime_get();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void igc_ptp_time_restore(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct timespec64 ts = adapter->prev_ptp_time;
|
|
|
|
ktime_t delta;
|
|
|
|
|
|
|
|
delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
|
|
|
|
|
|
|
|
timespec64_add_ns(&ts, ktime_to_ns(delta));
|
|
|
|
|
|
|
|
igc_ptp_write_i225(adapter, &ts);
|
|
|
|
}
|
|
|
|
|
2022-11-03 19:39:35 +07:00
|
|
|
static void igc_ptm_stop(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct igc_hw *hw = &adapter->hw;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
ctrl = rd32(IGC_PTM_CTRL);
|
|
|
|
ctrl &= ~IGC_PTM_CTRL_EN;
|
|
|
|
|
|
|
|
wr32(IGC_PTM_CTRL, ctrl);
|
|
|
|
}
|
|
|
|
|
2022-10-25 00:08:22 +07:00
|
|
|
/**
|
|
|
|
* igc_ptp_suspend - Disable PTP work items and prepare for suspend
|
|
|
|
* @adapter: Board private structure
|
|
|
|
*
|
|
|
|
* This function stops the overflow check work and PTP Tx timestamp work, and
|
|
|
|
* will prepare the device for OS suspend.
|
|
|
|
*/
|
|
|
|
void igc_ptp_suspend(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
|
|
|
|
return;
|
|
|
|
|
|
|
|
cancel_work_sync(&adapter->ptp_tx_work);
|
|
|
|
dev_kfree_skb_any(adapter->ptp_tx_skb);
|
|
|
|
adapter->ptp_tx_skb = NULL;
|
|
|
|
clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
|
|
|
|
|
2022-11-03 19:39:35 +07:00
|
|
|
if (pci_device_is_present(adapter->pdev)) {
|
|
|
|
igc_ptp_time_save(adapter);
|
|
|
|
igc_ptm_stop(adapter);
|
|
|
|
}
|
2022-10-25 00:08:22 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_stop - Disable PTP device and stop the overflow check.
|
|
|
|
* @adapter: Board private structure.
|
|
|
|
*
|
|
|
|
* This function stops the PTP support and cancels the delayed work.
|
|
|
|
**/
|
|
|
|
void igc_ptp_stop(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
igc_ptp_suspend(adapter);
|
|
|
|
|
|
|
|
if (adapter->ptp_clock) {
|
|
|
|
ptp_clock_unregister(adapter->ptp_clock);
|
|
|
|
netdev_info(adapter->netdev, "PHC removed\n");
|
|
|
|
adapter->ptp_flags &= ~IGC_PTP_ENABLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* igc_ptp_reset - Re-enable the adapter for PTP following a reset.
|
|
|
|
* @adapter: Board private structure.
|
|
|
|
*
|
|
|
|
* This function handles the reset work required to re-enable the PTP device.
|
|
|
|
**/
|
|
|
|
void igc_ptp_reset(struct igc_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct igc_hw *hw = &adapter->hw;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
/* reset the tstamp_config */
|
|
|
|
igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&adapter->tmreg_lock, flags);
|
|
|
|
|
|
|
|
switch (adapter->hw.mac.type) {
|
|
|
|
case igc_i225:
|
|
|
|
wr32(IGC_TSAUXC, 0x0);
|
|
|
|
wr32(IGC_TSSDP, 0x0);
|
|
|
|
wr32(IGC_TSIM, IGC_TSICR_INTERRUPTS);
|
|
|
|
wr32(IGC_IMS, IGC_IMS_TS);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* No work to do. */
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Re-initialize the timer. */
|
|
|
|
if (hw->mac.type == igc_i225) {
|
|
|
|
igc_ptp_time_restore(adapter);
|
|
|
|
} else {
|
|
|
|
timecounter_init(&adapter->tc, &adapter->cc,
|
|
|
|
ktime_to_ns(ktime_get_real()));
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
|
|
|
|
|
|
|
|
wrfl();
|
|
|
|
}
|