mirror of
https://github.com/AuxXxilium/redpill-lkm5.git
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78 lines
4.3 KiB
C
78 lines
4.3 KiB
C
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#ifndef REDPILL_DEBUG_VUART_H
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#define REDPILL_DEBUG_VUART_H
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//Whether the code will print all internal state changes
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#ifdef VUART_DEBUG_LOG
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//Main print macro used everywhere below
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#define uart_prdbg(f, ...) pr_loc_dbg(f, ##__VA_ARGS__)
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#define reg_read(rN) uart_prdbg("Reading " rN " registry");
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#define reg_write(rN) uart_prdbg("Writing " rN " registry");
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#define reg_read_dump(d, rF, rN) reg_read(rN); dump_##rF(d);
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#define reg_write_dump(d, rF, rN) reg_write(rN); dump_##rF(d);
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#define dri(vdev, reg, flag) ((vdev)->reg&(flag)) ? 1:0 //Dump Register as 1-0 Integer
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#define diiri(vdev, flag) (((vdev)->iir&UART_IIR_ID) == (flag)) ? 1:0 //Dump IIR Interrupt type as 1-0 integer
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#define dump_ier(d) \
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uart_prdbg("IER[0x%02x]: DR_int=%d | THRe_int=%d | RLS_int=%d | " \
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"MS_int=%d", \
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(d)->ier, dri(d,ier,UART_IER_RDI), dri(d,ier,UART_IER_THRI), dri(d,ier,UART_IER_RLSI), \
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dri(d,ier,UART_IER_MSI));
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//Be careful interpreting the result of this macro - no_int_pend means "no interrupts pending" (so 0 if there are
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// pending interrupts and 1 if there are no interrupts pending); see Table 3-5 in TI doc
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//Also FIFO flags are slightly weird (it's 2 bit, see IIR table in https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming)
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// so fifoen=0_0 means "FIFO disabled", fifoen=1_1 means "FIFO enabled", and fifoen=0_1 means "FIFO enabled & broken"
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//Also, since MSI is 0-0-0 it's a special-ish case: it's only considered enabled when int is pending and all bits are 0
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#define dump_iir(d) \
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uart_prdbg("IIR/ISR[0x%02x]: no_int_pend=%d | int_MS=%d | " \
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"int_THRe=%d | int_DR=%d | int_RLS=%d | " \
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"fifoen=%d_%d", \
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(d)->iir, dri(d,iir,UART_IIR_NO_INT), (!((d)->iir&UART_IIR_NO_INT)&&((d)->iir&UART_IIR_ID)==UART_IIR_MSI)?1:0, \
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diiri(d,UART_IIR_THRI), diiri(d,UART_IIR_RDI), diiri(d,UART_IIR_RLSI), \
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(((d)->iir & UART_IIR_FIFEN_B6)?1:0), (((d)->iir & UART_IIR_FIFEN_B7)?1:0));
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#define dump_fcr(d) \
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uart_prdbg("FCR[0x%02x]: FIFOon=%d | RxFIFOrst=%d | " \
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"TxFIFOrst=%d | EnDMAend=%d", \
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(d)->fcr, dri(d,fcr,UART_FCR_ENABLE_FIFO), dri(d,fcr,UART_FCR_CLEAR_RCVR), \
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dri(d,fcr,UART_FCR_CLEAR_XMIT), dri(d,fcr,UART_FCR_DMA_SELECT));
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#define dump_lcr(d) \
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uart_prdbg("LCR[0x%02x]: Stop=%d | PairEN=%d | EvenP=%d | " \
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"ForcPair=%d | SetBrk=%d | DLAB=%d", \
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(d)->lcr, dri(d,lcr,UART_LCR_STOP), dri(d,lcr,UART_LCR_PARITY), dri(d,lcr,UART_LCR_EPAR), \
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dri(d,lcr,UART_LCR_SPAR), dri(d,lcr,UART_LCR_SBC), dri(d,lcr,UART_LCR_DLAB));
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#define dump_mcr(d) \
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uart_prdbg("MCR[0x%02x]: DTR=%d | RTS=%d | Out1=%d | " \
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"Out2/IntE=%d | Loop=%d", \
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(d)->mcr, dri(d,mcr,UART_MCR_DTR), dri(d,mcr,UART_MCR_RTS), dri(d,mcr,UART_MCR_OUT1), \
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dri(d,mcr,UART_MCR_OUT2), dri(d,mcr,UART_MCR_LOOP));
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#define dump_lsr(d) \
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uart_prdbg("LSR[0x%02x]: data_ready=%d | ovrunE=%d | pairE=%d | " \
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"frE=%d | break_req=%d | THRemp=%d | TransEMP=%d | " \
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"FIFOdE=%d", \
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(d)->lsr, dri(d,lsr,UART_LSR_DR), dri(d,lsr,UART_LSR_OE), dri(d,lsr,UART_LSR_PE), \
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dri(d,lsr,UART_LSR_FE), dri(d,lsr,UART_LSR_BI), dri(d,lsr,UART_LSR_THRE), dri(d,lsr,UART_LSR_TEMT), \
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dri(d,lsr,UART_LSR_FIFOE));
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#define dump_msr(d) \
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uart_prdbg("MSR[0x%02x]: delCTS=%d | delDSR=%d | trEdgRI=%d | " \
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"delCD=%d | CTS=%d | DSR=%d | RI=%d | " \
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"DCD=%d", \
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(d)->msr, dri(d,msr,UART_MSR_DCTS), dri(d,msr,UART_MSR_DDSR), dri(d,msr,UART_MSR_TERI), \
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dri(d,msr,UART_MSR_DDCD), dri(d,msr,UART_MSR_CTS), dri(d,msr,UART_MSR_DSR), dri(d,msr,UART_MSR_RI), \
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dri(d,msr,UART_MSR_DCD));
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#else //VUART_DEBUG_LOG disabled \/
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#define uart_prdbg(f, ...) { /* noop */ }
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#define reg_read(rN) { /* noop */ }
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#define reg_write(rN) { /* noop */ }
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#define reg_read_dump(d, rF, rN) { /* noop */ }
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#define reg_write_dump(d, rF, rN) { /* noop */ }
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#define dump_ier(d) { /* noop */ }
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#define dump_iir(d) { /* noop */ }
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#define dump_fcr(d) { /* noop */ }
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#define dump_lcr(d) { /* noop */ }
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#define dump_mcr(d) { /* noop */ }
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#define dump_lsr(d) { /* noop */ }
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#define dump_msr(d) { /* noop */ }
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#endif //VUART_DEBUG_LOG
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#endif //REDPILL_DEBUG_VUART_H
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