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39413ae009
Unlike standard powerpc, Powerpc 8xx doesn't have SPRN_DABR, but
it has a breakpoint support based on a set of comparators which
allow more flexibility.
Commit 4ad8622dc5 ("powerpc/8xx: Implement hw_breakpoint")
implemented breakpoints by emulating the DABR behaviour. It did
this by setting one comparator the match 4 bytes at breakpoint address
and the other comparator to match 4 bytes at breakpoint address + 4.
Rewrite 8xx hw_breakpoint to make breakpoints match all addresses
defined by the breakpoint address and length by making full use of
comparators.
Now, comparator E is set to match any address greater than breakpoint
address minus one. Comparator F is set to match any address lower than
breakpoint address plus breakpoint length. Addresses are aligned
to 32 bits.
When the breakpoint range starts at address 0, the breakpoint is set
to match comparator F only. When the breakpoint range end at address
0xffffffff, the breakpoint is set to match comparator E only.
Otherwise the breakpoint is set to match comparator E and F.
At the same time, use registers bit names instead of hardcoded values.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/05105deeaf63bc02151aea2cdeaf525534e0e9d4.1574790198.git.christophe.leroy@c-s.fr
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Contains register definitions common to PowerPC 8xx CPUs. Notice
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*/
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#ifndef _ASM_POWERPC_REG_8xx_H
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#define _ASM_POWERPC_REG_8xx_H
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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#define SPRN_IC_CST 560 /* Instruction cache control/status */
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#define SPRN_IC_ADR 561 /* Address needed for some commands */
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#define SPRN_IC_DAT 562 /* Read-only data register */
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#define SPRN_DC_CST 568 /* Data cache control/status */
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#define SPRN_DC_ADR 569 /* Address needed for some commands */
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#define SPRN_DC_DAT 570 /* Read-only data register */
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/* Misc Debug */
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#define SPRN_DPDR 630
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#define SPRN_MI_CAM 816
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#define SPRN_MI_RAM0 817
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#define SPRN_MI_RAM1 818
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#define SPRN_MD_CAM 824
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#define SPRN_MD_RAM0 825
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#define SPRN_MD_RAM1 826
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/* Special MSR manipulation registers */
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#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
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#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
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#define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
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/* Debug registers */
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#define SPRN_CMPA 144
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#define SPRN_COUNTA 150
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#define SPRN_CMPE 152
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#define SPRN_CMPF 153
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#define SPRN_LCTRL1 156
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#define LCTRL1_CTE_GT 0xc0000000
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#define LCTRL1_CTF_LT 0x14000000
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#define LCTRL1_CRWE_RW 0x00000000
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#define LCTRL1_CRWE_RO 0x00040000
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#define LCTRL1_CRWE_WO 0x000c0000
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#define LCTRL1_CRWF_RW 0x00000000
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#define LCTRL1_CRWF_RO 0x00010000
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#define LCTRL1_CRWF_WO 0x00030000
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#define SPRN_LCTRL2 157
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#define LCTRL2_LW0EN 0x80000000
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#define LCTRL2_LW0LA_E 0x00000000
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#define LCTRL2_LW0LA_F 0x04000000
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#define LCTRL2_LW0LA_EandF 0x08000000
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#define LCTRL2_LW0LADC 0x02000000
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#define LCTRL2_SLW0EN 0x00000002
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#ifdef CONFIG_PPC_8xx
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#define SPRN_ICTRL 158
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#endif
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#define SPRN_BAR 159
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/* Commands. Only the first few are available to the instruction cache.
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*/
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#define IDC_ENABLE 0x02000000 /* Cache enable */
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#define IDC_DISABLE 0x04000000 /* Cache disable */
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#define IDC_LDLCK 0x06000000 /* Load and lock */
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#define IDC_UNLINE 0x08000000 /* Unlock line */
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#define IDC_UNALL 0x0a000000 /* Unlock all */
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#define IDC_INVALL 0x0c000000 /* Invalidate all */
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#define DC_FLINE 0x0e000000 /* Flush data cache line */
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#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
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#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
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#define DC_SLES 0x05000000 /* Set little endian swap mode */
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#define DC_CLES 0x07000000 /* Clear little endian swap mode */
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/* Status.
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*/
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#define IDC_ENABLED 0x80000000 /* Cache is enabled */
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#define IDC_CERR1 0x00200000 /* Cache error 1 */
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#define IDC_CERR2 0x00100000 /* Cache error 2 */
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#define IDC_CERR3 0x00080000 /* Cache error 3 */
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#define DC_DFWT 0x40000000 /* Data cache is forced write through */
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#define DC_LES 0x20000000 /* Caches are little endian mode */
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#endif /* _ASM_POWERPC_REG_8xx_H */
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