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23eb7f560a
Similar to commit 22e9c88d48
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts the following ASM symbols to C:
flush_icache_range()
__flush_dcache_icache()
__flush_dcache_icache_phys()
This was done as we discovered a long-standing bug where the length of the
range was truncated due to using a 32 bit shift instead of a 64 bit one.
By converting these functions to C, it becomes easier to maintain.
flush_dcache_icache_phys() retains a critical assembler section as we must
ensure there are no memory accesses while the data MMU is disabled
(authored by Christophe Leroy). Since this has no external callers, it has
also been made static, allowing the compiler to inline it within
flush_dcache_icache_page().
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
[mpe: Minor fixups, don't export __flush_dcache_icache()]
Link: https://lore.kernel.org/r/20191104023305.9581-5-alastair@au1.ibm.com
147 lines
2.9 KiB
C
147 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_CACHE_H
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#define _ASM_POWERPC_CACHE_H
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#ifdef __KERNEL__
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/* bytes per L1 cache line */
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#if defined(CONFIG_PPC_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#define IFETCH_ALIGN_SHIFT 2
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#elif defined(CONFIG_PPC_E500MC)
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#define L1_CACHE_SHIFT 6
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#define MAX_COPY_PREFETCH 4
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#define IFETCH_ALIGN_SHIFT 3
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#elif defined(CONFIG_PPC32)
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#define MAX_COPY_PREFETCH 4
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#define IFETCH_ALIGN_SHIFT 3 /* 603 fetches 2 insn at a time */
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#if defined(CONFIG_PPC_47x)
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#define L1_CACHE_SHIFT 7
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#else
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#define L1_CACHE_SHIFT 5
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#endif
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#else /* CONFIG_PPC64 */
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#define L1_CACHE_SHIFT 7
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#define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT)
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#if !defined(__ASSEMBLY__)
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#ifdef CONFIG_PPC64
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struct ppc_cache_info {
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u32 size;
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u32 line_size;
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u32 block_size; /* L1 only */
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u32 log_block_size;
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u32 blocks_per_page;
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u32 sets;
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u32 assoc;
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};
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struct ppc64_caches {
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struct ppc_cache_info l1d;
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struct ppc_cache_info l1i;
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struct ppc_cache_info l2;
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struct ppc_cache_info l3;
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};
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extern struct ppc64_caches ppc64_caches;
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static inline u32 l1_dcache_shift(void)
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{
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return ppc64_caches.l1d.log_block_size;
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}
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static inline u32 l1_dcache_bytes(void)
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{
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return ppc64_caches.l1d.block_size;
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}
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static inline u32 l1_icache_shift(void)
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{
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return ppc64_caches.l1i.log_block_size;
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}
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static inline u32 l1_icache_bytes(void)
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{
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return ppc64_caches.l1i.block_size;
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}
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#else
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static inline u32 l1_dcache_shift(void)
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{
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return L1_CACHE_SHIFT;
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}
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static inline u32 l1_dcache_bytes(void)
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{
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return L1_CACHE_BYTES;
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}
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static inline u32 l1_icache_shift(void)
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{
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return L1_CACHE_SHIFT;
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}
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static inline u32 l1_icache_bytes(void)
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{
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return L1_CACHE_BYTES;
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}
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#endif
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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#ifdef CONFIG_PPC_BOOK3S_32
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extern long _get_L2CR(void);
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extern long _get_L3CR(void);
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extern void _set_L2CR(unsigned long);
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extern void _set_L3CR(unsigned long);
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#else
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#define _get_L2CR() 0L
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#define _get_L3CR() 0L
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#define _set_L2CR(val) do { } while(0)
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#define _set_L3CR(val) do { } while(0)
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#endif
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static inline void dcbz(void *addr)
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{
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__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
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}
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static inline void dcbi(void *addr)
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{
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__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
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}
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static inline void dcbf(void *addr)
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{
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__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
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}
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static inline void dcbst(void *addr)
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{
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__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
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}
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static inline void icbi(void *addr)
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{
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asm volatile ("icbi 0, %0" : : "r"(addr) : "memory");
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}
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static inline void iccci(void *addr)
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{
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asm volatile ("iccci 0, %0" : : "r"(addr) : "memory");
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHE_H */
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