mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4d2327ca9d
Commit 0998d06310
(device-core: Ensure drvdata = NULL when no
driver is bound) removes the need to set driver data field to
NULL.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
362 lines
9.3 KiB
C
362 lines
9.3 KiB
C
/*
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* drivers/watchdog/shwdt.c
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*
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* Watchdog driver for integrated watchdog in the SuperH processors.
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*
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* Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
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* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
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*
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* 19-Apr-2002 Rob Radez <rob@osinvestor.com>
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* Added expect close support, made emulated timeout runtime changeable
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* general cleanups, add some ioctls
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/pm_runtime.h>
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#include <linux/fs.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm/watchdog.h>
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#define DRV_NAME "sh-wdt"
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/*
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* Default clock division ratio is 5.25 msecs. For an additional table of
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* values, consult the asm-sh/watchdog.h. Overload this at module load
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* time.
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*
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* In order for this to work reliably we need to have HZ set to 1000 or
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* something quite higher than 100 (or we need a proper high-res timer
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* implementation that will deal with this properly), otherwise the 10ms
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* resolution of a jiffy is enough to trigger the overflow. For things like
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* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
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* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
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* necssary.
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*
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* As a result of this timing problem, the only modes that are particularly
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* feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
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* overflow periods respectively.
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*
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* Also, since we can't really expect userspace to be responsive enough
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* before the overflow happens, we maintain two separate timers .. One in
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* the kernel for clearing out WOVF every 2ms or so (again, this depends on
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* HZ == 1000), and another for monitoring userspace writes to the WDT device.
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*
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* As such, we currently use a configurable heartbeat interval which defaults
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* to 30s. In this case, the userspace daemon is only responsible for periodic
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* writes to the device before the next heartbeat is scheduled. If the daemon
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* misses its deadline, the kernel timer will allow the WDT to overflow.
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*/
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static int clock_division_ratio = WTCSR_CKS_4096;
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#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
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#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
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static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static unsigned long next_heartbeat;
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struct sh_wdt {
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void __iomem *base;
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struct device *dev;
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struct clk *clk;
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spinlock_t lock;
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struct timer_list timer;
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};
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static int sh_wdt_start(struct watchdog_device *wdt_dev)
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{
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struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned long flags;
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u8 csr;
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pm_runtime_get_sync(wdt->dev);
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clk_enable(wdt->clk);
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spin_lock_irqsave(&wdt->lock, flags);
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next_heartbeat = jiffies + (heartbeat * HZ);
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mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
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csr = sh_wdt_read_csr();
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csr |= WTCSR_WT | clock_division_ratio;
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sh_wdt_write_csr(csr);
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sh_wdt_write_cnt(0);
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/*
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* These processors have a bit of an inconsistent initialization
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* process.. starting with SH-3, RSTS was moved to WTCSR, and the
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* RSTCSR register was removed.
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*
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* On the SH-2 however, in addition with bits being in different
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* locations, we must deal with RSTCSR outright..
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*/
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csr = sh_wdt_read_csr();
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csr |= WTCSR_TME;
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csr &= ~WTCSR_RSTS;
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sh_wdt_write_csr(csr);
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#ifdef CONFIG_CPU_SH2
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csr = sh_wdt_read_rstcsr();
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csr &= ~RSTCSR_RSTS;
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sh_wdt_write_rstcsr(csr);
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#endif
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spin_unlock_irqrestore(&wdt->lock, flags);
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return 0;
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}
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static int sh_wdt_stop(struct watchdog_device *wdt_dev)
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{
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struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned long flags;
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u8 csr;
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spin_lock_irqsave(&wdt->lock, flags);
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del_timer(&wdt->timer);
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csr = sh_wdt_read_csr();
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csr &= ~WTCSR_TME;
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sh_wdt_write_csr(csr);
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spin_unlock_irqrestore(&wdt->lock, flags);
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clk_disable(wdt->clk);
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pm_runtime_put_sync(wdt->dev);
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return 0;
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}
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static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
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{
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struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned long flags;
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spin_lock_irqsave(&wdt->lock, flags);
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next_heartbeat = jiffies + (heartbeat * HZ);
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spin_unlock_irqrestore(&wdt->lock, flags);
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return 0;
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}
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static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
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{
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struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
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unsigned long flags;
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if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
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return -EINVAL;
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spin_lock_irqsave(&wdt->lock, flags);
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heartbeat = t;
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wdt_dev->timeout = t;
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spin_unlock_irqrestore(&wdt->lock, flags);
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return 0;
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}
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static void sh_wdt_ping(unsigned long data)
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{
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struct sh_wdt *wdt = (struct sh_wdt *)data;
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unsigned long flags;
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spin_lock_irqsave(&wdt->lock, flags);
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if (time_before(jiffies, next_heartbeat)) {
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u8 csr;
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csr = sh_wdt_read_csr();
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csr &= ~WTCSR_IOVF;
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sh_wdt_write_csr(csr);
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sh_wdt_write_cnt(0);
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mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
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} else
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dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
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"the watchdog\n");
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spin_unlock_irqrestore(&wdt->lock, flags);
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}
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static const struct watchdog_info sh_wdt_info = {
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE,
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.firmware_version = 1,
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.identity = "SH WDT",
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};
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static const struct watchdog_ops sh_wdt_ops = {
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.owner = THIS_MODULE,
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.start = sh_wdt_start,
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.stop = sh_wdt_stop,
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.ping = sh_wdt_keepalive,
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.set_timeout = sh_wdt_set_heartbeat,
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};
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static struct watchdog_device sh_wdt_dev = {
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.info = &sh_wdt_info,
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.ops = &sh_wdt_ops,
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};
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static int sh_wdt_probe(struct platform_device *pdev)
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{
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struct sh_wdt *wdt;
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struct resource *res;
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int rc;
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/*
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* As this driver only covers the global watchdog case, reject
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* any attempts to register per-CPU watchdogs.
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*/
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if (pdev->id != -1)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!res))
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return -EINVAL;
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wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
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if (unlikely(!wdt))
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return -ENOMEM;
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wdt->dev = &pdev->dev;
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wdt->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(wdt->clk)) {
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/*
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* Clock framework support is optional, continue on
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* anyways if we don't find a matching clock.
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*/
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wdt->clk = NULL;
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}
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wdt->base = devm_ioremap_resource(wdt->dev, res);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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watchdog_set_nowayout(&sh_wdt_dev, nowayout);
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watchdog_set_drvdata(&sh_wdt_dev, wdt);
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spin_lock_init(&wdt->lock);
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rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
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if (unlikely(rc)) {
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/* Default timeout if invalid */
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sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
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dev_warn(&pdev->dev,
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"heartbeat value must be 1<=x<=3600, using %d\n",
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sh_wdt_dev.timeout);
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}
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dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
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sh_wdt_dev.timeout, nowayout);
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rc = watchdog_register_device(&sh_wdt_dev);
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if (unlikely(rc)) {
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dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
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return rc;
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}
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init_timer(&wdt->timer);
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wdt->timer.function = sh_wdt_ping;
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wdt->timer.data = (unsigned long)wdt;
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wdt->timer.expires = next_ping_period(clock_division_ratio);
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platform_set_drvdata(pdev, wdt);
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dev_info(&pdev->dev, "initialized.\n");
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pm_runtime_enable(&pdev->dev);
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return 0;
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}
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static int sh_wdt_remove(struct platform_device *pdev)
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{
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struct sh_wdt *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&sh_wdt_dev);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static void sh_wdt_shutdown(struct platform_device *pdev)
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{
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sh_wdt_stop(&sh_wdt_dev);
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}
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static struct platform_driver sh_wdt_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.probe = sh_wdt_probe,
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.remove = sh_wdt_remove,
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.shutdown = sh_wdt_shutdown,
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};
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static int __init sh_wdt_init(void)
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{
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if (unlikely(clock_division_ratio < 0x5 ||
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clock_division_ratio > 0x7)) {
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clock_division_ratio = WTCSR_CKS_4096;
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pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
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clock_division_ratio);
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}
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return platform_driver_register(&sh_wdt_driver);
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}
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static void __exit sh_wdt_exit(void)
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{
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platform_driver_unregister(&sh_wdt_driver);
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}
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module_init(sh_wdt_init);
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module_exit(sh_wdt_exit);
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MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
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MODULE_DESCRIPTION("SuperH watchdog driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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module_param(clock_division_ratio, int, 0);
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MODULE_PARM_DESC(clock_division_ratio,
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"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
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"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
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__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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