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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b4e844f019
For ccm clock gate, both 2b'11 and 2b'01 should be treated as clock enabled, see below description in CCM, whenver CPU trys to check clock gate's status, system will be in run mode. 2b'00: clock is off during all modes; 2b'01: clock is on in run mode, but off in wait and stop mode; 2b'10: Not applicable; 2b'11: clock is on during all modes, except stop mode. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
120 lines
2.7 KiB
C
120 lines
2.7 KiB
C
/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include "clk.h"
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/**
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* DOC: basic gatable clock which can gate and ungate it's ouput
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static int clk_gate2_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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u32 reg;
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unsigned long flags = 0;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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reg = readl(gate->reg);
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reg |= 3 << gate->bit_idx;
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writel(reg, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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static void clk_gate2_disable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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u32 reg;
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unsigned long flags = 0;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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writel(reg, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int clk_gate2_is_enabled(struct clk_hw *hw)
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{
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u32 reg;
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struct clk_gate *gate = to_clk_gate(hw);
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reg = readl(gate->reg);
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if (((reg >> gate->bit_idx) & 1) == 1)
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return 1;
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return 0;
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}
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static struct clk_ops clk_gate2_ops = {
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.is_enabled = clk_gate2_is_enabled,
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};
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate2_flags, spinlock_t *lock)
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{
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struct clk_gate *gate;
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struct clk *clk;
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struct clk_init_data init;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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/* struct clk_gate assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->flags = clk_gate2_flags;
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gate->lock = lock;
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init.name = name;
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init.ops = &clk_gate2_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->hw.init = &init;
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clk = clk_register(dev, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}
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