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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ff7b0d2720
Add implementation for counter allocator. The ASIC has special memory pool for various counting purposes. Counter memory is distributed between equal size banks. The static sub-pool configuration should specify the following parameters for each sub-pool: - Number of required banks. - Maximum entry size. Each module can add dedicated sub-pool or use existing one. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
146 lines
4.7 KiB
C
146 lines
4.7 KiB
C
/*
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* drivers/net/ethernet/mellanox/mlxsw/resources.h
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* Copyright (c) 2016-2017 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2016-2017 Jiri Pirko <jiri@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MLXSW_RESOURCES_H
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#define _MLXSW_RESOURCES_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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enum mlxsw_res_id {
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MLXSW_RES_ID_KVD_SIZE,
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MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
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MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
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MLXSW_RES_ID_MAX_TRAP_GROUPS,
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MLXSW_RES_ID_COUNTER_POOL_SIZE,
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MLXSW_RES_ID_MAX_SPAN,
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MLXSW_RES_ID_MAX_SYSTEM_PORT,
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MLXSW_RES_ID_MAX_LAG,
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MLXSW_RES_ID_MAX_LAG_MEMBERS,
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MLXSW_RES_ID_MAX_BUFFER_SIZE,
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MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
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MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
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MLXSW_RES_ID_ACL_MAX_REGIONS,
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MLXSW_RES_ID_ACL_MAX_GROUPS,
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MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
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MLXSW_RES_ID_ACL_FLEX_KEYS,
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MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
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MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
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MLXSW_RES_ID_MAX_CPU_POLICERS,
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MLXSW_RES_ID_MAX_VRS,
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MLXSW_RES_ID_MAX_RIFS,
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/* Internal resources.
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* Determined by the SW, not queried from the HW.
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*/
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MLXSW_RES_ID_KVD_SINGLE_SIZE,
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MLXSW_RES_ID_KVD_DOUBLE_SIZE,
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MLXSW_RES_ID_KVD_LINEAR_SIZE,
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__MLXSW_RES_ID_MAX,
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};
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static u16 mlxsw_res_ids[] = {
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[MLXSW_RES_ID_KVD_SIZE] = 0x1001,
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[MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
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[MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
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[MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
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[MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
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[MLXSW_RES_ID_MAX_SPAN] = 0x2420,
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[MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
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[MLXSW_RES_ID_MAX_LAG] = 0x2520,
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[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
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[MLXSW_RES_ID_MAX_BUFFER_SIZE] = 0x2802, /* Bytes */
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[MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
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[MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
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[MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
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[MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
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[MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
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[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
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[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
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[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
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[MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
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[MLXSW_RES_ID_MAX_VRS] = 0x2C01,
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[MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
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};
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struct mlxsw_res {
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bool valid[__MLXSW_RES_ID_MAX];
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u64 values[__MLXSW_RES_ID_MAX];
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};
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static inline bool mlxsw_res_valid(struct mlxsw_res *res,
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enum mlxsw_res_id res_id)
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{
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return res->valid[res_id];
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}
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#define MLXSW_RES_VALID(res, short_res_id) \
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mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
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static inline u64 mlxsw_res_get(struct mlxsw_res *res,
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enum mlxsw_res_id res_id)
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{
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if (WARN_ON(!res->valid[res_id]))
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return 0;
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return res->values[res_id];
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}
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#define MLXSW_RES_GET(res, short_res_id) \
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mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
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static inline void mlxsw_res_set(struct mlxsw_res *res,
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enum mlxsw_res_id res_id, u64 value)
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{
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res->valid[res_id] = true;
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res->values[res_id] = value;
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}
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#define MLXSW_RES_SET(res, short_res_id, value) \
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mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
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static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
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if (mlxsw_res_ids[i] == id) {
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mlxsw_res_set(res, i, value);
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return;
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}
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}
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}
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#endif
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