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ff1e29ade4
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7803/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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| alchemy | ||
| ar7 | ||
| ath79 | ||
| bcm47xx | ||
| bcm63xx | ||
| boot | ||
| cavium-octeon | ||
| cobalt | ||
| configs | ||
| dec | ||
| emma | ||
| fw | ||
| include | ||
| jazz | ||
| jz4740 | ||
| kernel | ||
| kvm | ||
| lantiq | ||
| lasat | ||
| lib | ||
| loongson | ||
| loongson1 | ||
| math-emu | ||
| mm | ||
| mti-malta | ||
| mti-sead3 | ||
| net | ||
| netlogic | ||
| oprofile | ||
| paravirt | ||
| pci | ||
| pmcs-msp71xx | ||
| pnx833x | ||
| power | ||
| ralink | ||
| rb532 | ||
| sgi-ip22 | ||
| sgi-ip27 | ||
| sgi-ip32 | ||
| sibyte | ||
| sni | ||
| txx9 | ||
| vr41xx | ||
| Kbuild | ||
| Kbuild.platforms | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||