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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Some SoCs (such as Amlogic Meson GXL for example) share the reset line with other components (in case of the Meson GXL example there's a shared reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller). Additionally SoC implementations may prefer a reset pulse over level resets. For now this falls back to the old defaults, which are: - reset lines are exclusive - level resets are being used Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> |
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| .. | ||
| core.c | ||
| core.h | ||
| debug.h | ||
| debugfs.c | ||
| drd.c | ||
| dwc3-exynos.c | ||
| dwc3-keystone.c | ||
| dwc3-of-simple.c | ||
| dwc3-omap.c | ||
| dwc3-pci.c | ||
| dwc3-st.c | ||
| ep0.c | ||
| gadget.c | ||
| gadget.h | ||
| host.c | ||
| io.h | ||
| Kconfig | ||
| Makefile | ||
| trace.c | ||
| trace.h | ||
| ulpi.c | ||