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7cc7eaad49
The ifdeffery for atomic*_{fetch_,}andnot() is unlike that for all the
other atomics. If atomic*_andnot() is not defined, the corresponding
atomic*_fetch_andnot() is assumed to not be defined.
Additionally, the fallbacks for the various ordering cases are written
much later in atomic.h as static inlines.
This isn't problematic today, but gets in the way of scripting the
generation of atomics. To prepare for scripting, this patch:
* Switches to separate ifdefs for atomic*_andnot() and
atomic*_fetch_andnot(), updating implementations as appropriate.
* Moves the fallbacks into the standards ifdefs, as macro expansions
rather than static inlines.
* Removes trivial andnot implementations from architectures, where these
are superseded by core code.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/lkml/20180621121321.4761-19-mark.rutland@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
515 lines
12 KiB
C
515 lines
12 KiB
C
/*
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* arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ATOMIC_H
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#define __ASM_ARM_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/prefetch.h>
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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/*
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* On ARM, ordinary assignment (str instruction) doesn't clear the local
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* strex/ldrex monitor on some implementations. The reason we can use it for
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* atomic_set() is the clrex or dummy strex done on every exception return.
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*/
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
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#if __LINUX_ARM_ARCH__ >= 6
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/*
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* ARMv6 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*/
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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prefetchw(&v->counter); \
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__asm__ __volatile__("@ atomic_" #op "\n" \
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"1: ldrex %0, [%3]\n" \
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" " #asm_op " %0, %0, %4\n" \
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" strex %1, %0, [%3]\n" \
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" teq %1, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "Ir" (i) \
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: "cc"); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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prefetchw(&v->counter); \
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\
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__asm__ __volatile__("@ atomic_" #op "_return\n" \
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"1: ldrex %0, [%3]\n" \
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" " #asm_op " %0, %0, %4\n" \
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" strex %1, %0, [%3]\n" \
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" teq %1, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "Ir" (i) \
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: "cc"); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result, val; \
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\
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prefetchw(&v->counter); \
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\
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__asm__ __volatile__("@ atomic_fetch_" #op "\n" \
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"1: ldrex %0, [%4]\n" \
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" " #asm_op " %1, %0, %5\n" \
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" strex %2, %1, [%4]\n" \
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" teq %2, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "Ir" (i) \
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: "cc"); \
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\
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return result; \
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}
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_andnot_relaxed atomic_fetch_andnot_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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static inline int atomic_cmpxchg_relaxed(atomic_t *ptr, int old, int new)
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{
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int oldval;
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unsigned long res;
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prefetchw(&ptr->counter);
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do {
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__asm__ __volatile__("@ atomic_cmpxchg\n"
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"ldrex %1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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"strexeq %0, %5, [%3]\n"
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: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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return oldval;
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}
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#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed
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static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int oldval, newval;
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unsigned long tmp;
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smp_mb();
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prefetchw(&v->counter);
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__asm__ __volatile__ ("@ atomic_add_unless\n"
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"1: ldrex %0, [%4]\n"
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" teq %0, %5\n"
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" beq 2f\n"
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" add %1, %0, %6\n"
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" strex %2, %1, [%4]\n"
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" teq %2, #0\n"
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" bne 1b\n"
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"2:"
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: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
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: "r" (&v->counter), "r" (u), "r" (a)
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: "cc");
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if (oldval != u)
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smp_mb();
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return oldval;
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}
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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#else /* ARM_ARCH_6 */
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#ifdef CONFIG_SMP
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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int val; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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val = v->counter; \
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raw_local_irq_restore(flags); \
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\
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return val; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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int val; \
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\
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raw_local_irq_save(flags); \
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val = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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\
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return val; \
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}
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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unsigned long flags;
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raw_local_irq_save(flags);
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ret = v->counter;
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if (likely(ret == old))
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v->counter = new;
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raw_local_irq_restore(flags);
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return ret;
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}
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#define atomic_fetch_andnot atomic_fetch_andnot
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#endif /* __LINUX_ARM_ARCH__ */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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#define atomic_andnot atomic_andnot
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(andnot, &= ~, bic)
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ATOMIC_OPS(or, |=, orr)
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ATOMIC_OPS(xor, ^=, eor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#ifndef CONFIG_GENERIC_ATOMIC64
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typedef struct {
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long long counter;
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} atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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#ifdef CONFIG_ARM_LPAE
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long result;
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__asm__ __volatile__("@ atomic64_read\n"
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" ldrd %0, %H0, [%1]"
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: "=&r" (result)
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: "r" (&v->counter), "Qo" (v->counter)
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);
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return result;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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__asm__ __volatile__("@ atomic64_set\n"
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" strd %2, %H2, [%1]"
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: "=Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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);
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}
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#else
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long result;
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__asm__ __volatile__("@ atomic64_read\n"
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" ldrexd %0, %H0, [%1]"
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: "=&r" (result)
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: "r" (&v->counter), "Qo" (v->counter)
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);
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return result;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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long long tmp;
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prefetchw(&v->counter);
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__asm__ __volatile__("@ atomic64_set\n"
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"1: ldrexd %0, %H0, [%2]\n"
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" strexd %0, %3, %H3, [%2]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp), "=Qo" (v->counter)
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: "r" (&v->counter), "r" (i)
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: "cc");
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}
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#endif
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#define ATOMIC64_OP(op, op1, op2) \
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static inline void atomic64_##op(long long i, atomic64_t *v) \
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{ \
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long long result; \
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unsigned long tmp; \
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\
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prefetchw(&v->counter); \
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__asm__ __volatile__("@ atomic64_" #op "\n" \
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"1: ldrexd %0, %H0, [%3]\n" \
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" " #op1 " %Q0, %Q0, %Q4\n" \
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" " #op2 " %R0, %R0, %R4\n" \
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" strexd %1, %0, %H0, [%3]\n" \
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" teq %1, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "r" (i) \
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: "cc"); \
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} \
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#define ATOMIC64_OP_RETURN(op, op1, op2) \
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static inline long long \
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atomic64_##op##_return_relaxed(long long i, atomic64_t *v) \
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{ \
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long long result; \
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unsigned long tmp; \
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\
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prefetchw(&v->counter); \
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\
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__asm__ __volatile__("@ atomic64_" #op "_return\n" \
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"1: ldrexd %0, %H0, [%3]\n" \
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" " #op1 " %Q0, %Q0, %Q4\n" \
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" " #op2 " %R0, %R0, %R4\n" \
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" strexd %1, %0, %H0, [%3]\n" \
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" teq %1, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "r" (i) \
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: "cc"); \
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\
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return result; \
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}
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#define ATOMIC64_FETCH_OP(op, op1, op2) \
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static inline long long \
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atomic64_fetch_##op##_relaxed(long long i, atomic64_t *v) \
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{ \
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long long result, val; \
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unsigned long tmp; \
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\
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prefetchw(&v->counter); \
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\
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__asm__ __volatile__("@ atomic64_fetch_" #op "\n" \
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"1: ldrexd %0, %H0, [%4]\n" \
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" " #op1 " %Q1, %Q0, %Q5\n" \
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" " #op2 " %R1, %R0, %R5\n" \
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" strexd %2, %1, %H1, [%4]\n" \
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" teq %2, #0\n" \
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" bne 1b" \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
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: "r" (&v->counter), "r" (i) \
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: "cc"); \
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\
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return result; \
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}
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#define ATOMIC64_OPS(op, op1, op2) \
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ATOMIC64_OP(op, op1, op2) \
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ATOMIC64_OP_RETURN(op, op1, op2) \
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ATOMIC64_FETCH_OP(op, op1, op2)
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ATOMIC64_OPS(add, adds, adc)
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ATOMIC64_OPS(sub, subs, sbc)
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, op1, op2) \
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ATOMIC64_OP(op, op1, op2) \
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ATOMIC64_FETCH_OP(op, op1, op2)
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#define atomic64_andnot atomic64_andnot
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ATOMIC64_OPS(and, and, and)
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ATOMIC64_OPS(andnot, bic, bic)
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ATOMIC64_OPS(or, orr, orr)
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ATOMIC64_OPS(xor, eor, eor)
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_andnot_relaxed atomic64_fetch_andnot_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static inline long long
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atomic64_cmpxchg_relaxed(atomic64_t *ptr, long long old, long long new)
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{
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long long oldval;
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unsigned long res;
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prefetchw(&ptr->counter);
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do {
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__asm__ __volatile__("@ atomic64_cmpxchg\n"
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"ldrexd %1, %H1, [%3]\n"
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"mov %0, #0\n"
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"teq %1, %4\n"
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"teqeq %H1, %H4\n"
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"strexdeq %0, %5, %H5, [%3]"
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: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "r" (old), "r" (new)
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: "cc");
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} while (res);
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return oldval;
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}
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#define atomic64_cmpxchg_relaxed atomic64_cmpxchg_relaxed
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static inline long long atomic64_xchg_relaxed(atomic64_t *ptr, long long new)
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{
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long long result;
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unsigned long tmp;
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prefetchw(&ptr->counter);
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__asm__ __volatile__("@ atomic64_xchg\n"
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"1: ldrexd %0, %H0, [%3]\n"
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" strexd %1, %4, %H4, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
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: "r" (&ptr->counter), "r" (new)
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: "cc");
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return result;
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}
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#define atomic64_xchg_relaxed atomic64_xchg_relaxed
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static inline long long atomic64_dec_if_positive(atomic64_t *v)
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|
{
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|
long long result;
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|
unsigned long tmp;
|
|
|
|
smp_mb();
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|
prefetchw(&v->counter);
|
|
|
|
__asm__ __volatile__("@ atomic64_dec_if_positive\n"
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|
"1: ldrexd %0, %H0, [%3]\n"
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|
" subs %Q0, %Q0, #1\n"
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|
" sbc %R0, %R0, #0\n"
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|
" teq %R0, #0\n"
|
|
" bmi 2f\n"
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|
" strexd %1, %0, %H0, [%3]\n"
|
|
" teq %1, #0\n"
|
|
" bne 1b\n"
|
|
"2:"
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|
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
|
|
: "r" (&v->counter)
|
|
: "cc");
|
|
|
|
smp_mb();
|
|
|
|
return result;
|
|
}
|
|
#define atomic64_dec_if_positive atomic64_dec_if_positive
|
|
|
|
static inline long long atomic64_fetch_add_unless(atomic64_t *v, long long a,
|
|
long long u)
|
|
{
|
|
long long oldval, newval;
|
|
unsigned long tmp;
|
|
|
|
smp_mb();
|
|
prefetchw(&v->counter);
|
|
|
|
__asm__ __volatile__("@ atomic64_add_unless\n"
|
|
"1: ldrexd %0, %H0, [%4]\n"
|
|
" teq %0, %5\n"
|
|
" teqeq %H0, %H5\n"
|
|
" beq 2f\n"
|
|
" adds %Q1, %Q0, %Q6\n"
|
|
" adc %R1, %R0, %R6\n"
|
|
" strexd %2, %1, %H1, [%4]\n"
|
|
" teq %2, #0\n"
|
|
" bne 1b\n"
|
|
"2:"
|
|
: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
|
|
: "r" (&v->counter), "r" (u), "r" (a)
|
|
: "cc");
|
|
|
|
if (oldval != u)
|
|
smp_mb();
|
|
|
|
return oldval;
|
|
}
|
|
#define atomic64_fetch_add_unless atomic64_fetch_add_unless
|
|
|
|
#endif /* !CONFIG_GENERIC_ATOMIC64 */
|
|
#endif
|
|
#endif
|