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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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724142f8c4
This patch adds support for performance reporting private feature
for FPGA Management Engine (FME). Now it supports several different
performance counters, including 'basic', 'cache', 'fabric', 'vtd'
and 'vtd_sip'. It allows user to use standard linux tools to access
these performance counters.
e.g. List all events by "perf list"
perf list | grep fme
dfl_fme0/cache_read_hit/ [Kernel PMU event]
dfl_fme0/cache_read_miss/ [Kernel PMU event]
...
dfl_fme0/fab_mmio_read/ [Kernel PMU event]
dfl_fme0/fab_mmio_write/ [Kernel PMU event]
...
dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event]
dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event]
...
dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event]
dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event]
...
dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event]
dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event]
...
dfl_fme0/clock [Kernel PMU event]
...
e.g. check increased counter value after run one application using
"perf stat" command.
perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test
Performance counter stats for './test':
1 dfl_fme0/fab_mmio_read/
2 dfl_fme0/fab_mmio_write/
1.009496520 seconds time elapsed
Please note that fabric counters support both fab_* and fab_port_*, but
actually they are sharing one set of performance counters in hardware.
If user wants to monitor overall data events on fab_* then fab_port_*
can't be supported at the same time, see example below:
perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/
Performance counter stats for 'system wide':
0 dfl_fme0/fab_mmio_read/
<not supported> dfl_fme0/fab_port_mmio_write,portid=0/
2.141064085 seconds time elapsed
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
219 lines
6.8 KiB
Plaintext
219 lines
6.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# FPGA framework configuration
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#
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menuconfig FPGA
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tristate "FPGA Configuration Framework"
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help
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Say Y here if you want support for configuring FPGAs from the
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kernel. The FPGA framework adds a FPGA manager class and FPGA
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manager drivers.
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if FPGA
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config FPGA_MGR_SOCFPGA
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tristate "Altera SOCFPGA FPGA Manager"
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depends on ARCH_SOCFPGA || COMPILE_TEST
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help
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FPGA manager driver support for Altera SOCFPGA.
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config FPGA_MGR_SOCFPGA_A10
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tristate "Altera SoCFPGA Arria10"
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depends on ARCH_SOCFPGA || COMPILE_TEST
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select REGMAP_MMIO
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help
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FPGA manager driver support for Altera Arria10 SoCFPGA.
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config ALTERA_PR_IP_CORE
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tristate "Altera Partial Reconfiguration IP Core"
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help
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Core driver support for Altera Partial Reconfiguration IP component
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config ALTERA_PR_IP_CORE_PLAT
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tristate "Platform support of Altera Partial Reconfiguration IP Core"
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depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
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help
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Platform driver support for Altera Partial Reconfiguration IP
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component
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config FPGA_MGR_ALTERA_PS_SPI
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tristate "Altera FPGA Passive Serial over SPI"
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depends on SPI
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select BITREVERSE
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help
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FPGA manager driver support for Altera Arria/Cyclone/Stratix
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using the passive serial interface over SPI.
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config FPGA_MGR_ALTERA_CVP
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tristate "Altera CvP FPGA Manager"
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depends on PCI
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help
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FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
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Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
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config FPGA_MGR_ZYNQ_FPGA
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tristate "Xilinx Zynq FPGA"
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depends on ARCH_ZYNQ || COMPILE_TEST
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help
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FPGA manager driver support for Xilinx Zynq FPGAs.
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config FPGA_MGR_STRATIX10_SOC
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tristate "Intel Stratix10 SoC FPGA Manager"
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depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
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help
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FPGA manager driver support for the Intel Stratix10 SoC.
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config FPGA_MGR_XILINX_SPI
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tristate "Xilinx Configuration over Slave Serial (SPI)"
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depends on SPI
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help
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FPGA manager driver support for Xilinx FPGA configuration
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over slave serial interface.
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config FPGA_MGR_ICE40_SPI
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tristate "Lattice iCE40 SPI"
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depends on OF && SPI
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help
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FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
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config FPGA_MGR_MACHXO2_SPI
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tristate "Lattice MachXO2 SPI"
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depends on SPI
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help
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FPGA manager driver support for Lattice MachXO2 configuration
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over slave SPI interface.
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config FPGA_MGR_TS73XX
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tristate "Technologic Systems TS-73xx SBC FPGA Manager"
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depends on ARCH_EP93XX && MACH_TS72XX
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help
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FPGA manager driver support for the Altera Cyclone II FPGA
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present on the TS-73xx SBC boards.
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config FPGA_BRIDGE
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tristate "FPGA Bridge Framework"
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help
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Say Y here if you want to support bridges connected between host
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processors and FPGAs or between FPGAs.
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config SOCFPGA_FPGA_BRIDGE
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tristate "Altera SoCFPGA FPGA Bridges"
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depends on ARCH_SOCFPGA && FPGA_BRIDGE
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help
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Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
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devices.
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config ALTERA_FREEZE_BRIDGE
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tristate "Altera FPGA Freeze Bridge"
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depends on FPGA_BRIDGE && HAS_IOMEM
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help
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Say Y to enable drivers for Altera FPGA Freeze bridges. A
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freeze bridge is a bridge that exists in the FPGA fabric to
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isolate one region of the FPGA from the busses while that
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region is being reprogrammed.
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config XILINX_PR_DECOUPLER
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tristate "Xilinx LogiCORE PR Decoupler"
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depends on FPGA_BRIDGE
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depends on HAS_IOMEM
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help
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Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
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The PR Decoupler exists in the FPGA fabric to isolate one
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region of the FPGA from the busses while that region is
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being reprogrammed during partial reconfig.
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config FPGA_REGION
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tristate "FPGA Region"
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depends on FPGA_BRIDGE
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help
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FPGA Region common code. A FPGA Region controls a FPGA Manager
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and the FPGA Bridges associated with either a reconfigurable
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region of an FPGA or a whole FPGA.
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config OF_FPGA_REGION
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tristate "FPGA Region Device Tree Overlay Support"
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depends on OF && FPGA_REGION
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help
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Support for loading FPGA images by applying a Device Tree
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overlay.
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config FPGA_DFL
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tristate "FPGA Device Feature List (DFL) support"
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select FPGA_BRIDGE
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select FPGA_REGION
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help
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Device Feature List (DFL) defines a feature list structure that
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creates a linked list of feature headers within the MMIO space
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to provide an extensible way of adding features for FPGA.
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Driver can walk through the feature headers to enumerate feature
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devices (e.g. FPGA Management Engine, Port and Accelerator
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Function Unit) and their private features for target FPGA devices.
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Select this option to enable common support for Field-Programmable
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Gate Array (FPGA) solutions which implement Device Feature List.
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It provides enumeration APIs and feature device infrastructure.
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config FPGA_DFL_FME
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tristate "FPGA DFL FME Driver"
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depends on FPGA_DFL && HWMON && PERF_EVENTS
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help
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The FPGA Management Engine (FME) is a feature device implemented
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under Device Feature List (DFL) framework. Select this option to
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enable the platform device driver for FME which implements all
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FPGA platform level management features. There shall be one FME
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per DFL based FPGA device.
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config FPGA_DFL_FME_MGR
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tristate "FPGA DFL FME Manager Driver"
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depends on FPGA_DFL_FME && HAS_IOMEM
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help
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Say Y to enable FPGA Manager driver for FPGA Management Engine.
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config FPGA_DFL_FME_BRIDGE
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tristate "FPGA DFL FME Bridge Driver"
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depends on FPGA_DFL_FME && HAS_IOMEM
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help
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Say Y to enable FPGA Bridge driver for FPGA Management Engine.
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config FPGA_DFL_FME_REGION
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tristate "FPGA DFL FME Region Driver"
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depends on FPGA_DFL_FME && HAS_IOMEM
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help
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Say Y to enable FPGA Region driver for FPGA Management Engine.
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config FPGA_DFL_AFU
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tristate "FPGA DFL AFU Driver"
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depends on FPGA_DFL
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help
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This is the driver for FPGA Accelerated Function Unit (AFU) which
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implements AFU and Port management features. A User AFU connects
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to the FPGA infrastructure via a Port. There may be more than one
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Port/AFU per DFL based FPGA device.
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config FPGA_DFL_PCI
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tristate "FPGA DFL PCIe Device Driver"
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depends on PCI && FPGA_DFL
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help
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Select this option to enable PCIe driver for PCIe-based
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Field-Programmable Gate Array (FPGA) solutions which implement
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the Device Feature List (DFL). This driver provides interfaces
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for userspace applications to configure, enumerate, open and access
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FPGA accelerators on the FPGA DFL devices, enables system level
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management functions such as FPGA partial reconfiguration, power
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management and virtualization with DFL framework and DFL feature
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device drivers.
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To compile this as a module, choose M here.
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config FPGA_MGR_ZYNQMP_FPGA
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tristate "Xilinx ZynqMP FPGA"
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depends on ARCH_ZYNQMP || COMPILE_TEST
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help
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FPGA manager driver support for Xilinx ZynqMP FPGAs.
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This driver uses the processor configuration port(PCAP)
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to configure the programmable logic(PL) through PS
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on ZynqMP SoC.
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endif # FPGA
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