mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 02:27:02 +07:00
5186a6cc3e
V{PEND,PROP}BASER registers are actually located in VLPI_base frame
of the *redistributor*. Rename their accessors to reflect this fact.
No functional changes.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200206075711.1275-7-yuzenghui@huawei.com
376 lines
9.8 KiB
C
376 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
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#define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1)
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#define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0)
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#define ICC_SGI1R __ACCESS_CP15_64(0, c12)
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#define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0)
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#define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
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#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
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#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
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#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
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#define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3)
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#define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x)
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#define ICC_AP0R0 __ICC_AP0Rx(0)
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#define ICC_AP0R1 __ICC_AP0Rx(1)
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#define ICC_AP0R2 __ICC_AP0Rx(2)
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#define ICC_AP0R3 __ICC_AP0Rx(3)
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#define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x)
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#define ICC_AP1R0 __ICC_AP1Rx(0)
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#define ICC_AP1R1 __ICC_AP1Rx(1)
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#define ICC_AP1R2 __ICC_AP1Rx(2)
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#define ICC_AP1R3 __ICC_AP1Rx(3)
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#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
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#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
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#define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
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#define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
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#define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
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#define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
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#define ICH_ELRSR __ACCESS_CP15(c12, 4, c11, 5)
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#define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
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#define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
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#define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
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#define ICH_LR0 __LR0(0)
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#define ICH_LR1 __LR0(1)
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#define ICH_LR2 __LR0(2)
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#define ICH_LR3 __LR0(3)
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#define ICH_LR4 __LR0(4)
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#define ICH_LR5 __LR0(5)
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#define ICH_LR6 __LR0(6)
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#define ICH_LR7 __LR0(7)
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#define ICH_LR8 __LR8(0)
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#define ICH_LR9 __LR8(1)
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#define ICH_LR10 __LR8(2)
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#define ICH_LR11 __LR8(3)
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#define ICH_LR12 __LR8(4)
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#define ICH_LR13 __LR8(5)
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#define ICH_LR14 __LR8(6)
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#define ICH_LR15 __LR8(7)
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/* LR top half */
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#define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
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#define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
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#define ICH_LRC0 __LRC0(0)
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#define ICH_LRC1 __LRC0(1)
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#define ICH_LRC2 __LRC0(2)
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#define ICH_LRC3 __LRC0(3)
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#define ICH_LRC4 __LRC0(4)
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#define ICH_LRC5 __LRC0(5)
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#define ICH_LRC6 __LRC0(6)
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#define ICH_LRC7 __LRC0(7)
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#define ICH_LRC8 __LRC8(0)
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#define ICH_LRC9 __LRC8(1)
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#define ICH_LRC10 __LRC8(2)
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#define ICH_LRC11 __LRC8(3)
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#define ICH_LRC12 __LRC8(4)
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#define ICH_LRC13 __LRC8(5)
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#define ICH_LRC14 __LRC8(6)
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#define ICH_LRC15 __LRC8(7)
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#define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
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#define ICH_AP0R0 __ICH_AP0Rx(0)
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#define ICH_AP0R1 __ICH_AP0Rx(1)
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#define ICH_AP0R2 __ICH_AP0Rx(2)
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#define ICH_AP0R3 __ICH_AP0Rx(3)
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#define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
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#define ICH_AP1R0 __ICH_AP1Rx(0)
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#define ICH_AP1R1 __ICH_AP1Rx(1)
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#define ICH_AP1R2 __ICH_AP1Rx(2)
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#define ICH_AP1R3 __ICH_AP1Rx(3)
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/* A32-to-A64 mappings used by VGIC save/restore */
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#define CPUIF_MAP(a32, a64) \
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static inline void write_ ## a64(u32 val) \
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{ \
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write_sysreg(val, a32); \
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} \
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static inline u32 read_ ## a64(void) \
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{ \
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return read_sysreg(a32); \
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} \
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#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
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static inline void write_ ## a64(u64 val) \
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{ \
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write_sysreg(lower_32_bits(val), a32lo);\
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write_sysreg(upper_32_bits(val), a32hi);\
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} \
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static inline u64 read_ ## a64(void) \
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{ \
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u64 val = read_sysreg(a32lo); \
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\
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val |= (u64)read_sysreg(a32hi) << 32; \
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\
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return val; \
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}
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CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
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CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
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CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
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CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)
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CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
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CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)
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CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
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CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
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CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
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CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
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CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
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CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
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CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
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CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2)
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CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
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CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
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CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
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CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
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CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
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CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
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CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
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CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
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CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
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CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
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CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
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CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
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CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
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CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
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CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
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CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
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CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
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CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
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CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
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CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
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CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
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CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
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CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
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CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
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CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
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CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
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CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
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#define read_gicreg(r) read_##r()
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#define write_gicreg(v, r) write_##r(v)
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/* Low-level accessors */
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg(irq, ICC_EOIR1);
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isb();
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}
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static inline void gic_write_dir(u32 val)
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{
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write_sysreg(val, ICC_DIR);
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isb();
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}
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static inline u32 gic_read_iar(void)
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{
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u32 irqstat = read_sysreg(ICC_IAR1);
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dsb(sy);
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return irqstat;
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg(val, ICC_CTLR);
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isb();
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}
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static inline u32 gic_read_ctlr(void)
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{
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return read_sysreg(ICC_CTLR);
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg(val, ICC_IGRPEN1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg(val, ICC_SGI1R);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg(ICC_SRE);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg(val, ICC_SRE);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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write_sysreg(val, ICC_BPR1);
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}
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static inline u32 gic_read_pmr(void)
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{
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return read_sysreg(ICC_PMR);
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}
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg(val, ICC_PMR);
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}
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static inline u32 gic_read_rpr(void)
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{
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return read_sysreg(ICC_RPR);
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}
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/*
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* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
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* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
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* make much sense.
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* Moreover, 64bit I/O emulation is extremely difficult to implement on
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* AArch32, since the syndrome register doesn't provide any information for
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* them.
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* Consequently, the following IO helpers use 32bit accesses.
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*/
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static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
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{
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writel_relaxed((u32)val, addr);
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writel_relaxed((u32)(val >> 32), addr + 4);
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}
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static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
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{
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u64 val;
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val = readl_relaxed(addr);
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val |= (u64)readl_relaxed(addr + 4) << 32;
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return val;
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}
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#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
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/*
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* GICD_IROUTERn, contain the affinity values associated to each interrupt.
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* The upper-word (aff3) will always be 0, so there is no need for a lock.
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*/
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#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GICR_TYPER is an ID register and doesn't need atomicity.
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*/
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#define gic_read_typer(c) __gic_readq_nonatomic(c)
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/*
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* GITS_BASER - hi and lo bits may be accessed independently.
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*/
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#define gits_read_baser(c) __gic_readq_nonatomic(c)
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#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
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* won't be being used during any updates and can be changed non-atomically
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*/
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#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
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#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
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#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
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#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GICR_xLPIR - only the lower bits are significant
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*/
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#define gic_read_lpir(c) readl_relaxed(c)
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#define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c)
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/*
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* GITS_TYPER is an ID register and doesn't need atomicity.
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*/
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#define gits_read_typer(c) __gic_readq_nonatomic(c)
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/*
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* GITS_CBASER - hi and lo bits may be accessed independently.
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*/
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#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
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#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GITS_CWRITER - hi and lo bits may be accessed independently.
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*/
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#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GICR_VPROPBASER - hi and lo bits may be accessed independently.
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*/
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#define gicr_read_vpropbaser(c) __gic_readq_nonatomic(c)
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#define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
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/*
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* GICR_VPENDBASER - the Valid bit must be cleared before changing
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* anything else.
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*/
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static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
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{
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u32 tmp;
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tmp = readl_relaxed(addr + 4);
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if (tmp & (GICR_VPENDBASER_Valid >> 32)) {
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tmp &= ~(GICR_VPENDBASER_Valid >> 32);
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writel_relaxed(tmp, addr + 4);
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}
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/*
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* Use the fact that __gic_writeq_nonatomic writes the second
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* half of the 64bit quantity after the first.
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*/
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__gic_writeq_nonatomic(val, addr);
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}
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#define gicr_read_vpendbaser(c) __gic_readq_nonatomic(c)
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static inline bool gic_prio_masking_enabled(void)
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{
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return false;
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}
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static inline void gic_pmr_mask_irqs(void)
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{
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/* Should not get called. */
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WARN_ON_ONCE(true);
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}
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static inline void gic_arch_enable_irqs(void)
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{
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/* Should not get called. */
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WARN_ON_ONCE(true);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_ARCH_GICV3_H */
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