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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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755a9ba7bf
As with previous release, this continues to be among the largest branches we merge, with lots of new contents. New things for this release are among other things: - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request) - Qualcomm APQ8064 and APQ8084 SoCs and eval boards - Nvidia Jetson TK1 development board (Tegra T124-based) Two new SoCs that didn't need enough new platform code to stand out enough for me to notice when writing the SoC tag, but that adds new DT contents are: - TI DRA72 - Marvell Berlin 2Q -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTjNNQAAoJEIwa5zzehBx3KyYP/3TEJcXXEYDURXDB0SktPNyy cKp5HUnsu4+aq/Ae6jdjVGiX5FZa64Xije9b0kP3oxoPS+fuODvzhlnoEsT84Ab5 /jeygWJZYUIWAQTxShPT55K8WAEtL7H1WcvswdCZoTDxPBNCLR/nLzv084nv9Die IOUWDTKW4qB8+KYQxh2TBx0E1TorZ0J5OWf6qqepZ0i4J5dhL1VYtc/ZNU5C37V5 rZyyBQNOCBE/MK/Dw9CnResQf4f8DigHBYgpl7VxB+bBqfgzFuSSEPvg21MXLkfi ln64yYTVvqhleVjGriDV+mUHOCZr4sUWZPDzeF5HzpvqDAMDWTsWlHNh6WDU6dgo b+zFPqqnWaBiWrinY+o7MVvjVzu3Nf8id/GyjnDJEFbSc9ka/8uiC3v9UJXAFawF 3Huc3K6BC/3qOoCPfnBotzx7Xxxvjk2lPRfnonhSvBoSzPeFc6vz2k4USX1GbdkB y/v+Q+n52VebxiKknTMv9HOI06yTOJo2ji+2iKIULb+W86HzNRZL8ZlmNib4WysF z/OgHZl+YzbhJQJtvfBecCIH2Hu+A4GD2ES8hhklA0QhFHPiDfB9cqcsthSGS5oL dDaGv6XGpHoySlEm1ybgWhvH96dc7lTR+nPGZqCKtRBn5pJiEHczxQ2Jz3aBHYeW PUPlrVfYXzIKsh+OU1HO =OvOG -----END PGP SIGNATURE----- Merge tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull ARM SoC devicetree updates from Olof Johansson: "As with previous release, this continues to be among the largest branches we merge, with lots of new contents. New things for this release are among other things: - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request) - Qualcomm APQ8064 and APQ8084 SoCs and eval boards - Nvidia Jetson TK1 development board (Tegra T124-based) Two new SoCs that didn't need enough new platform code to stand out enough for me to notice when writing the SoC tag, but that adds new DT contents are: - TI DRA72 - Marvell Berlin 2Q" * tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (500 commits) ARM: dts: add secure firmware support for exynos5420-arndale-octa ARM: dts: add pmu sysreg node to exynos3250 ARM: dts: correct the usb phy node in exynos5800-peach-pi ARM: dts: correct the usb phy node in exynos5420-peach-pit ARM: dts: add dts files for exynos5410 and exynos5410-smdk5410 ARM: dts: add dts files for exynos3250 SoC ARM: dts: add mfc node for exynos5800 ARM: dts: add Vbus regulator for USB 3.0 on exynos5800-peach-pi ARM: dts: enable fimd for exynos5800-peach-pi ARM: dts: enable display controller for exynos5800-peach-pi ARM: dts: enable hdmi for exynos5800-peach-pi ARM: dts: add dts file for exynos5800-peach-pi board ARM: dts: add dts file for exynos5800 SoC ARM: dts: add dts file for exynos5260-xyref5260 board ARM: dts: add dts files for exynos5260 SoC ARM: dts: update watchdog node name in exynos5440 ARM: dts: use key code macros on Origen and Arndale boards ARM: dts: enable RTC and WDT nodes on Origen boards ARM: dts: qcom: Add APQ8084-MTP board support ARM: dts: qcom: Add APQ8084 SoC support ...
884 lines
25 KiB
Plaintext
884 lines
25 KiB
Plaintext
/*
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* Device Tree Source for the r8a7791 SoC
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7791-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7791";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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spi0 = &qspi;
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spi1 = &msiof0;
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spi2 = &msiof1;
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spi3 = &msiof2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1500000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
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};
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7791", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* The memory map in the User's Manual maps the cores to bus numbers */
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i2c0: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6540000 0 0x40>;
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interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
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status = "disabled";
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};
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i2c4: i2c@e6520000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6520000 0 0x40>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
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status = "disabled";
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};
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i2c5: i2c@e6528000 {
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/* doesn't need pinmux */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6528000 0 0x40>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
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status = "disabled";
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};
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i2c6: i2c@e60b0000 {
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/* doesn't need pinmux */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
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reg = <0 0xe60b0000 0 0x425>;
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interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
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status = "disabled";
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};
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i2c7: i2c@e6500000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
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reg = <0 0xe6500000 0 0x425>;
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interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
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status = "disabled";
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};
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i2c8: i2c@e6510000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
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reg = <0 0xe6510000 0 0x425>;
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interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
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status = "disabled";
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};
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a7791";
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reg = <0 0xe6060000 0 0x250>;
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#gpio-range-cells = <3>;
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};
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sdhi0: sd@ee100000 {
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compatible = "renesas,sdhi-r8a7791";
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reg = <0 0xee100000 0 0x200>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
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status = "disabled";
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};
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sdhi1: sd@ee140000 {
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compatible = "renesas,sdhi-r8a7791";
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reg = <0 0xee140000 0 0x100>;
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interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
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status = "disabled";
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};
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sdhi2: sd@ee160000 {
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compatible = "renesas,sdhi-r8a7791";
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reg = <0 0xee160000 0 0x100>;
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interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
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status = "disabled";
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c60000 0 64>;
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interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c70000 0 64>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa4: serial@e6c78000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c78000 0 64>;
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interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa5: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7791", "renesas,scifa";
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reg = <0 0xe6c80000 0 64>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb0: serial@e6c20000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6c20000 0 64>;
|
|
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb1: serial@e6c30000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6c30000 0 64>;
|
|
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb2: serial@e6ce0000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6ce0000 0 64>;
|
|
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e58000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e58000 0 64>;
|
|
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6ea8000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ea8000 0 64>;
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6ee0000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ee0000 0 64>;
|
|
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6ee8000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ee8000 0 64>;
|
|
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e62c0000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62c0000 0 96>;
|
|
interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e62c8000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62c8000 0 96>;
|
|
interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e62d0000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62d0000 0 96>;
|
|
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
ether: ethernet@ee700000 {
|
|
compatible = "renesas,ether-r8a7791";
|
|
reg = <0 0xee700000 0 0x400>;
|
|
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
|
|
phy-mode = "rmii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata0: sata@ee300000 {
|
|
compatible = "renesas,sata-r8a7791";
|
|
reg = <0 0xee300000 0 0x2000>;
|
|
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata1: sata@ee500000 {
|
|
compatible = "renesas,sata-r8a7791";
|
|
reg = <0 0xee500000 0 0x2000>;
|
|
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* External root clock */
|
|
extal_clk: extal_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overriden by the board. */
|
|
clock-frequency = <0>;
|
|
clock-output-names = "extal";
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
compatible = "renesas,r8a7791-cpg-clocks",
|
|
"renesas,rcar-gen2-cpg-clocks";
|
|
reg = <0 0xe6150000 0 0x1000>;
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
"lb", "qspi", "sdh", "sd0", "z";
|
|
};
|
|
|
|
/* Variable factor clocks */
|
|
sd1_clk: sd2_clk@e6150078 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150078 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd1";
|
|
};
|
|
sd2_clk: sd3_clk@e615007c {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615007c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd2";
|
|
};
|
|
mmc0_clk: mmc0_clk@e6150240 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150240 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mmc0";
|
|
};
|
|
ssp_clk: ssp_clk@e6150248 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150248 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "ssp";
|
|
};
|
|
ssprs_clk: ssprs_clk@e615024c {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615024c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "ssprs";
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
pll1_div2_clk: pll1_div2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "pll1_div2";
|
|
};
|
|
zg_clk: zg_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zg";
|
|
};
|
|
zx_clk: zx_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zx";
|
|
};
|
|
zs_clk: zs_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zs";
|
|
};
|
|
hp_clk: hp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "hp";
|
|
};
|
|
i_clk: i_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "i";
|
|
};
|
|
b_clk: b_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "b";
|
|
};
|
|
p_clk: p_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "p";
|
|
};
|
|
cl_clk: cl_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cl";
|
|
};
|
|
m2_clk: m2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "m2";
|
|
};
|
|
imp_clk: imp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "imp";
|
|
};
|
|
rclk_clk: rclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(48 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "rclk";
|
|
};
|
|
oscclk_clk: oscclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(12 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "oscclk";
|
|
};
|
|
zb3_clk: zb3_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3";
|
|
};
|
|
zb3d2_clk: zb3d2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3d2";
|
|
};
|
|
ddr_clk: ddr_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "ddr";
|
|
};
|
|
mp_clk: mp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <15>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "mp";
|
|
};
|
|
cp_clk: cp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cp";
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
|
clocks = <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
|
|
clock-output-names = "msiof0";
|
|
};
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
|
clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
|
|
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
|
|
R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
|
|
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
|
|
>;
|
|
clock-output-names =
|
|
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
|
|
"vsp1-du0", "vsp1-sy";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&mp_clk>, <&mp_clk>, <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
|
|
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
|
|
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
|
|
>;
|
|
clock-output-names =
|
|
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
|
"scifb1", "msiof1", "scifb2";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
|
clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
|
|
<&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
|
|
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
|
|
>;
|
|
clock-output-names =
|
|
"tpu0", "sdhi2", "sdhi1", "sdhi0",
|
|
"mmcif0", "i2c7", "i2c8", "cmt1";
|
|
};
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
|
clocks = <&extal_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
|
|
clock-output-names = "thermal", "pwm";
|
|
};
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
<&zx_clk>, <&zx_clk>, <&zx_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
|
|
R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
|
|
R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
|
|
R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
|
|
R8A7791_CLK_LVDS0
|
|
>;
|
|
clock-output-names =
|
|
"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
|
"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
|
|
};
|
|
mstp8_clks: mstp8_clks@e6150990 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
|
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
|
|
R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
|
|
>;
|
|
clock-output-names =
|
|
"vin2", "vin1", "vin0", "ether", "sata1", "sata0";
|
|
};
|
|
mstp9_clks: mstp9_clks@e6150994 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
|
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
|
|
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
|
<&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
|
|
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
|
|
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
|
|
R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
|
|
R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
|
|
"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
|
|
"i2c1", "i2c0";
|
|
};
|
|
mstp11_clks: mstp11_clks@e615099c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
|
|
>;
|
|
clock-output-names = "scifa3", "scifa4", "scifa5";
|
|
};
|
|
};
|
|
|
|
qspi: spi@e6b10000 {
|
|
compatible = "renesas,qspi-r8a7791", "renesas,qspi";
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e20000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e20000 0 0x0064>;
|
|
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6e10000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e10000 0 0x0064>;
|
|
interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6e00000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e00000 0 0x0064>;
|
|
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|