mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 09:56:16 +07:00
fdf2f6c56e
Drop use of drmP.h in all files named amdgpu* in drm/amd/amdgpu/ Fix fallout. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-10-sam@ravnborg.org
685 lines
17 KiB
C
685 lines
17 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu_amdkfd.h"
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#include "amd_shared.h"
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include <linux/module.h>
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#include <linux/dma-buf.h>
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static const unsigned int compute_vmid_bitmap = 0xFF00;
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/* Total memory size in system memory and all GPU VRAM. Used to
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* estimate worst case amount of memory to reserve for page tables
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*/
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uint64_t amdgpu_amdkfd_total_mem_size;
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int amdgpu_amdkfd_init(void)
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{
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struct sysinfo si;
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int ret;
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si_meminfo(&si);
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amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
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amdgpu_amdkfd_total_mem_size *= si.mem_unit;
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#ifdef CONFIG_HSA_AMD
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ret = kgd2kfd_init();
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amdgpu_amdkfd_gpuvm_init_mem_limits();
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#else
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ret = -ENOENT;
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#endif
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return ret;
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}
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void amdgpu_amdkfd_fini(void)
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{
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kgd2kfd_exit();
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}
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void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
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{
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const struct kfd2kgd_calls *kfd2kgd;
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switch (adev->asic_type) {
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_KAVERI:
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case CHIP_HAWAII:
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kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
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break;
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#endif
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case CHIP_CARRIZO:
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case CHIP_TONGA:
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case CHIP_FIJI:
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case CHIP_POLARIS10:
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case CHIP_POLARIS11:
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case CHIP_POLARIS12:
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kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
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break;
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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case CHIP_RAVEN:
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kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
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break;
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default:
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dev_info(adev->dev, "kfd not supported on this ASIC\n");
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return;
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}
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adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
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adev->pdev, kfd2kgd);
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if (adev->kfd.dev)
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amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
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}
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/**
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* amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
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* setup amdkfd
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*
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* @adev: amdgpu_device pointer
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* @aperture_base: output returning doorbell aperture base physical address
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* @aperture_size: output returning doorbell aperture size in bytes
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* @start_offset: output returning # of doorbell bytes reserved for amdgpu.
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*
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* amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
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* takes doorbells required for its own rings and reports the setup to amdkfd.
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* amdgpu reserved doorbells are at the start of the doorbell aperture.
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*/
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static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
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phys_addr_t *aperture_base,
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size_t *aperture_size,
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size_t *start_offset)
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{
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/*
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* The first num_doorbells are used by amdgpu.
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* amdkfd takes whatever's left in the aperture.
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*/
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if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
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*aperture_base = adev->doorbell.base;
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*aperture_size = adev->doorbell.size;
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*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
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} else {
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*aperture_base = 0;
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*aperture_size = 0;
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*start_offset = 0;
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}
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}
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void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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{
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int i;
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int last_valid_bit;
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if (adev->kfd.dev) {
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struct kgd2kfd_shared_resources gpu_resources = {
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.compute_vmid_bitmap = compute_vmid_bitmap,
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.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
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.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
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.gpuvm_size = min(adev->vm_manager.max_pfn
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<< AMDGPU_GPU_PAGE_SHIFT,
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AMDGPU_GMC_HOLE_START),
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.drm_render_minor = adev->ddev->render->index,
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.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
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};
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/* this is going to have a few of the MSBs set that we need to
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* clear */
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bitmap_complement(gpu_resources.queue_bitmap,
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adev->gfx.mec.queue_bitmap,
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KGD_MAX_QUEUES);
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/* remove the KIQ bit as well */
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if (adev->gfx.kiq.ring.sched.ready)
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clear_bit(amdgpu_gfx_queue_to_bit(adev,
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adev->gfx.kiq.ring.me - 1,
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adev->gfx.kiq.ring.pipe,
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adev->gfx.kiq.ring.queue),
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gpu_resources.queue_bitmap);
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/* According to linux/bitmap.h we shouldn't use bitmap_clear if
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* nbits is not compile time constant */
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last_valid_bit = 1 /* only first MEC can have compute queues */
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* adev->gfx.mec.num_pipe_per_mec
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* adev->gfx.mec.num_queue_per_pipe;
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for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
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clear_bit(i, gpu_resources.queue_bitmap);
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amdgpu_doorbell_get_kfd_info(adev,
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&gpu_resources.doorbell_physical_address,
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&gpu_resources.doorbell_aperture_size,
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&gpu_resources.doorbell_start_offset);
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/* Since SOC15, BIF starts to statically use the
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* lower 12 bits of doorbell addresses for routing
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* based on settings in registers like
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* SDMA0_DOORBELL_RANGE etc..
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* In order to route a doorbell to CP engine, the lower
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* 12 bits of its address has to be outside the range
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* set for SDMA, VCN, and IH blocks.
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*/
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if (adev->asic_type >= CHIP_VEGA10) {
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gpu_resources.non_cp_doorbells_start =
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adev->doorbell_index.first_non_cp;
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gpu_resources.non_cp_doorbells_end =
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adev->doorbell_index.last_non_cp;
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}
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kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
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}
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}
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void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
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{
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if (adev->kfd.dev) {
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kgd2kfd_device_exit(adev->kfd.dev);
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adev->kfd.dev = NULL;
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}
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}
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void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
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const void *ih_ring_entry)
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{
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if (adev->kfd.dev)
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kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
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}
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void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
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{
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if (adev->kfd.dev)
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kgd2kfd_suspend(adev->kfd.dev);
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}
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int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
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{
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int r = 0;
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if (adev->kfd.dev)
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r = kgd2kfd_resume(adev->kfd.dev);
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return r;
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}
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int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
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{
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int r = 0;
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if (adev->kfd.dev)
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r = kgd2kfd_pre_reset(adev->kfd.dev);
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return r;
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}
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int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
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{
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int r = 0;
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if (adev->kfd.dev)
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r = kgd2kfd_post_reset(adev->kfd.dev);
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return r;
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}
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void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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if (amdgpu_device_should_recover_gpu(adev))
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amdgpu_device_gpu_recover(adev, NULL);
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}
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int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr, bool mqd_gfx9)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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struct amdgpu_bo *bo = NULL;
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struct amdgpu_bo_param bp;
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int r;
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void *cpu_ptr_tmp = NULL;
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_GTT;
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bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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if (mqd_gfx9)
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bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
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r = amdgpu_bo_create(adev, &bp, &bo);
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if (r) {
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dev_err(adev->dev,
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"failed to allocate BO for amdkfd (%d)\n", r);
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return r;
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}
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/* map the buffer */
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r = amdgpu_bo_reserve(bo, true);
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if (r) {
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dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
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goto allocate_mem_reserve_bo_failed;
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}
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r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
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if (r) {
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dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
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goto allocate_mem_pin_bo_failed;
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}
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r = amdgpu_ttm_alloc_gart(&bo->tbo);
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if (r) {
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dev_err(adev->dev, "%p bind failed\n", bo);
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goto allocate_mem_kmap_bo_failed;
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}
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r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
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if (r) {
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dev_err(adev->dev,
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"(%d) failed to map bo to kernel for amdkfd\n", r);
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goto allocate_mem_kmap_bo_failed;
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}
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*mem_obj = bo;
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*gpu_addr = amdgpu_bo_gpu_offset(bo);
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*cpu_ptr = cpu_ptr_tmp;
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amdgpu_bo_unreserve(bo);
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return 0;
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allocate_mem_kmap_bo_failed:
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amdgpu_bo_unpin(bo);
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allocate_mem_pin_bo_failed:
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amdgpu_bo_unreserve(bo);
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allocate_mem_reserve_bo_failed:
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amdgpu_bo_unref(&bo);
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return r;
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}
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void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
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{
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struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
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amdgpu_bo_reserve(bo, true);
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amdgpu_bo_kunmap(bo);
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amdgpu_bo_unpin(bo);
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amdgpu_bo_unreserve(bo);
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amdgpu_bo_unref(&(bo));
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}
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uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
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enum kgd_engine_type type)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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switch (type) {
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case KGD_ENGINE_PFP:
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return adev->gfx.pfp_fw_version;
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case KGD_ENGINE_ME:
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return adev->gfx.me_fw_version;
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case KGD_ENGINE_CE:
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return adev->gfx.ce_fw_version;
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case KGD_ENGINE_MEC1:
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return adev->gfx.mec_fw_version;
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case KGD_ENGINE_MEC2:
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return adev->gfx.mec2_fw_version;
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case KGD_ENGINE_RLC:
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return adev->gfx.rlc_fw_version;
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case KGD_ENGINE_SDMA1:
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return adev->sdma.instance[0].fw_version;
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case KGD_ENGINE_SDMA2:
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return adev->sdma.instance[1].fw_version;
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default:
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return 0;
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}
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return 0;
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}
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void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
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struct kfd_local_mem_info *mem_info)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
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~((1ULL << 32) - 1);
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resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
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memset(mem_info, 0, sizeof(*mem_info));
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if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
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mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
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mem_info->local_mem_size_private = adev->gmc.real_vram_size -
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adev->gmc.visible_vram_size;
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} else {
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mem_info->local_mem_size_public = 0;
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mem_info->local_mem_size_private = adev->gmc.real_vram_size;
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}
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mem_info->vram_width = adev->gmc.vram_width;
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pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
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&adev->gmc.aper_base, &aper_limit,
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mem_info->local_mem_size_public,
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mem_info->local_mem_size_private);
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if (amdgpu_sriov_vf(adev))
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mem_info->mem_clk_max = adev->clock.default_mclk / 100;
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else if (adev->powerplay.pp_funcs)
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mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
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else
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mem_info->mem_clk_max = 100;
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}
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uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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if (adev->gfx.funcs->get_gpu_clock_counter)
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return adev->gfx.funcs->get_gpu_clock_counter(adev);
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return 0;
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}
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uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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/* the sclk is in quantas of 10kHz */
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if (amdgpu_sriov_vf(adev))
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return adev->clock.default_sclk / 100;
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else if (adev->powerplay.pp_funcs)
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return amdgpu_dpm_get_sclk(adev, false) / 100;
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else
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return 100;
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}
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void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
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memset(cu_info, 0, sizeof(*cu_info));
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if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
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return;
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cu_info->cu_active_number = acu_info.number;
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cu_info->cu_ao_mask = acu_info.ao_cu_mask;
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memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
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sizeof(acu_info.bitmap));
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cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
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cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
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cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
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cu_info->simd_per_cu = acu_info.simd_per_cu;
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cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
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cu_info->wave_front_size = acu_info.wave_front_size;
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cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
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cu_info->lds_size = acu_info.lds_size;
|
|
}
|
|
|
|
int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
|
|
struct kgd_dev **dma_buf_kgd,
|
|
uint64_t *bo_size, void *metadata_buffer,
|
|
size_t buffer_size, uint32_t *metadata_size,
|
|
uint32_t *flags)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
|
|
struct dma_buf *dma_buf;
|
|
struct drm_gem_object *obj;
|
|
struct amdgpu_bo *bo;
|
|
uint64_t metadata_flags;
|
|
int r = -EINVAL;
|
|
|
|
dma_buf = dma_buf_get(dma_buf_fd);
|
|
if (IS_ERR(dma_buf))
|
|
return PTR_ERR(dma_buf);
|
|
|
|
if (dma_buf->ops != &amdgpu_dmabuf_ops)
|
|
/* Can't handle non-graphics buffers */
|
|
goto out_put;
|
|
|
|
obj = dma_buf->priv;
|
|
if (obj->dev->driver != adev->ddev->driver)
|
|
/* Can't handle buffers from different drivers */
|
|
goto out_put;
|
|
|
|
adev = obj->dev->dev_private;
|
|
bo = gem_to_amdgpu_bo(obj);
|
|
if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
|
|
AMDGPU_GEM_DOMAIN_GTT)))
|
|
/* Only VRAM and GTT BOs are supported */
|
|
goto out_put;
|
|
|
|
r = 0;
|
|
if (dma_buf_kgd)
|
|
*dma_buf_kgd = (struct kgd_dev *)adev;
|
|
if (bo_size)
|
|
*bo_size = amdgpu_bo_size(bo);
|
|
if (metadata_size)
|
|
*metadata_size = bo->metadata_size;
|
|
if (metadata_buffer)
|
|
r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
|
|
metadata_size, &metadata_flags);
|
|
if (flags) {
|
|
*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
|
|
ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT;
|
|
|
|
if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
|
|
*flags |= ALLOC_MEM_FLAGS_PUBLIC;
|
|
}
|
|
|
|
out_put:
|
|
dma_buf_put(dma_buf);
|
|
return r;
|
|
}
|
|
|
|
uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
|
|
|
|
return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
|
|
}
|
|
|
|
uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
|
|
|
|
return adev->gmc.xgmi.hive_id;
|
|
}
|
|
|
|
int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
|
|
uint32_t vmid, uint64_t gpu_addr,
|
|
uint32_t *ib_cmd, uint32_t ib_len)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_ib *ib;
|
|
struct amdgpu_ring *ring;
|
|
struct dma_fence *f = NULL;
|
|
int ret;
|
|
|
|
switch (engine) {
|
|
case KGD_ENGINE_MEC1:
|
|
ring = &adev->gfx.compute_ring[0];
|
|
break;
|
|
case KGD_ENGINE_SDMA1:
|
|
ring = &adev->sdma.instance[0].ring;
|
|
break;
|
|
case KGD_ENGINE_SDMA2:
|
|
ring = &adev->sdma.instance[1].ring;
|
|
break;
|
|
default:
|
|
pr_err("Invalid engine in IB submission: %d\n", engine);
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
ret = amdgpu_job_alloc(adev, 1, &job, NULL);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ib = &job->ibs[0];
|
|
memset(ib, 0, sizeof(struct amdgpu_ib));
|
|
|
|
ib->gpu_addr = gpu_addr;
|
|
ib->ptr = ib_cmd;
|
|
ib->length_dw = ib_len;
|
|
/* This works for NO_HWS. TODO: need to handle without knowing VMID */
|
|
job->vmid = vmid;
|
|
|
|
ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
|
|
if (ret) {
|
|
DRM_ERROR("amdgpu: failed to schedule IB.\n");
|
|
goto err_ib_sched;
|
|
}
|
|
|
|
ret = dma_fence_wait(f, false);
|
|
|
|
err_ib_sched:
|
|
dma_fence_put(f);
|
|
amdgpu_job_free(job);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
|
|
|
|
if (adev->powerplay.pp_funcs &&
|
|
adev->powerplay.pp_funcs->switch_power_profile)
|
|
amdgpu_dpm_switch_power_profile(adev,
|
|
PP_SMC_POWER_PROFILE_COMPUTE,
|
|
!idle);
|
|
}
|
|
|
|
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
|
|
{
|
|
if (adev->kfd.dev) {
|
|
if ((1 << vmid) & compute_vmid_bitmap)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
#ifndef CONFIG_HSA_AMD
|
|
bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
|
|
{
|
|
}
|
|
|
|
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
|
|
struct amdgpu_vm *vm)
|
|
{
|
|
}
|
|
|
|
struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
|
|
const struct kfd2kgd_calls *f2g)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
bool kgd2kfd_device_init(struct kfd_dev *kfd,
|
|
const struct kgd2kfd_shared_resources *gpu_resources)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
void kgd2kfd_device_exit(struct kfd_dev *kfd)
|
|
{
|
|
}
|
|
|
|
void kgd2kfd_exit(void)
|
|
{
|
|
}
|
|
|
|
void kgd2kfd_suspend(struct kfd_dev *kfd)
|
|
{
|
|
}
|
|
|
|
int kgd2kfd_resume(struct kfd_dev *kfd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int kgd2kfd_pre_reset(struct kfd_dev *kfd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int kgd2kfd_post_reset(struct kfd_dev *kfd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
|
|
{
|
|
}
|
|
|
|
void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
|
|
{
|
|
}
|
|
#endif
|