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e78c637127
Trying to boot an RK3328 box with an HS200-capable eMMC, I see said eMMC fail to initialise as it can't run its tuning procedure, because the sample clock is missing. Upon closer inspection, whilst the clock is present in the DT, its name is subtly incorrect per the binding, so __of_clk_get_by_name() never finds it. By inspection, the drive clock suffers from a similar problem, so has never worked properly either. This error has propagated across the 32-bit DTs too, so fix those up. Fixes:187d7967a5("ARM: dts: rockchip: add the sdio/sdmmc node for rk3036") Fixes:faea098e18("ARM: dts: rockchip: add core rk3036 dtsi") Fixes:9848ebeb95("ARM: dts: rockchip: add core rk3228 dtsi") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1115 lines
28 KiB
Plaintext
1115 lines
28 KiB
Plaintext
/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3228-cru.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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spi0 = &spi0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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resets = <&cru SRST_CORE0>;
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operating-points-v2 = <&cpu0_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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enable-method = "psci";
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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operating-points-v2 = <&cpu0_opp_table>;
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enable-method = "psci";
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};
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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resets = <&cru SRST_CORE2>;
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operating-points-v2 = <&cpu0_opp_table>;
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enable-method = "psci";
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};
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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resets = <&cru SRST_CORE3>;
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operating-points-v2 = <&cpu0_opp_table>;
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enable-method = "psci";
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <975000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1000000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1175000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1275000>;
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@110f0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x110f0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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i2s1: i2s1@100b0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100b0000 0x4000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
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dmas = <&pdma 14>, <&pdma 15>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s0: i2s0@100c0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100c0000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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dmas = <&pdma 11>, <&pdma 12>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spdif: spdif@100d0000 {
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compatible = "rockchip,rk3228-spdif";
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reg = <0x100d0000 0x1000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
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clock-names = "mclk", "hclk";
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dmas = <&pdma 10>;
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dma-names = "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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status = "disabled";
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};
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i2s2: i2s2@100e0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100e0000 0x4000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
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dmas = <&pdma 0>, <&pdma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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grf: syscon@11000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x11000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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io_domains: io-domains {
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compatible = "rockchip,rk3228-io-voltage-domain";
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status = "disabled";
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};
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u2phy0: usb2-phy@760 {
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compatible = "rockchip,rk3228-usb2phy";
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reg = <0x0760 0x0c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy0";
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#clock-cells = <0>;
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status = "disabled";
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u2phy0_otg: otg-port {
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id",
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"linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy0_host: host-port {
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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u2phy1: usb2-phy@800 {
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compatible = "rockchip,rk3228-usb2phy";
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reg = <0x0800 0x0c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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status = "disabled";
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u2phy1_otg: otg-port {
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy1_host: host-port {
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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uart0: serial@11010000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11010000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@11020000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11020000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@11030000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11030000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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efuse: efuse@11040000 {
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compatible = "rockchip,rk3228-efuse";
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reg = <0x11040000 0x20>;
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clocks = <&cru PCLK_EFUSE_256>;
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clock-names = "pclk_efuse";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Data cells */
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efuse_id: id@7 {
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reg = <0x7 0x10>;
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};
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cpu_leakage: cpu_leakage@17 {
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reg = <0x17 0x1>;
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};
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};
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i2c0: i2c@11050000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11050000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c1: i2c@11060000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11060000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c2: i2c@11070000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11070000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@11080000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11080000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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spi0: spi@11090000 {
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compatible = "rockchip,rk3228-spi";
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reg = <0x11090000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
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status = "disabled";
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};
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wdt: watchdog@110a0000 {
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compatible = "snps,dw-wdt";
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reg = <0x110a0000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_CPU>;
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status = "disabled";
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};
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pwm0: pwm@110b0000 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0000 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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status = "disabled";
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};
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pwm1: pwm@110b0010 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0010 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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status = "disabled";
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};
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pwm2: pwm@110b0020 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0020 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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|
clock-names = "pwm";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_pin>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@110b0030 {
|
|
compatible = "rockchip,rk3288-pwm";
|
|
reg = <0x110b0030 0x10>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cru PCLK_PWM>;
|
|
clock-names = "pwm";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_pin>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer: timer@110c0000 {
|
|
compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
|
|
reg = <0x110c0000 0x20>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&xin24m>, <&cru PCLK_TIMER>;
|
|
clock-names = "timer", "pclk";
|
|
};
|
|
|
|
cru: clock-controller@110e0000 {
|
|
compatible = "rockchip,rk3228-cru";
|
|
reg = <0x110e0000 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks =
|
|
<&cru PLL_GPLL>, <&cru ARMCLK>,
|
|
<&cru PLL_CPLL>, <&cru ACLK_PERI>,
|
|
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
|
|
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
|
|
<&cru PCLK_CPU>;
|
|
assigned-clock-rates =
|
|
<594000000>, <816000000>,
|
|
<500000000>, <150000000>,
|
|
<150000000>, <75000000>,
|
|
<150000000>, <150000000>,
|
|
<75000000>;
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu_thermal: cpu-thermal {
|
|
polling-delay-passive = <100>; /* milliseconds */
|
|
polling-delay = <5000>; /* milliseconds */
|
|
|
|
thermal-sensors = <&tsadc 0>;
|
|
|
|
trips {
|
|
cpu_alert0: cpu_alert0 {
|
|
temperature = <70000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
cpu_alert1: cpu_alert1 {
|
|
temperature = <75000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
cpu_crit: cpu_crit {
|
|
temperature = <90000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_alert0>;
|
|
cooling-device =
|
|
<&cpu0 THERMAL_NO_LIMIT 6>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu_alert1>;
|
|
cooling-device =
|
|
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tsadc: tsadc@11150000 {
|
|
compatible = "rockchip,rk3228-tsadc";
|
|
reg = <0x11150000 0x100>;
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
assigned-clocks = <&cru SCLK_TSADC>;
|
|
assigned-clock-rates = <32768>;
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
pinctrl-names = "init", "default", "sleep";
|
|
pinctrl-0 = <&otp_gpio>;
|
|
pinctrl-1 = <&otp_out>;
|
|
pinctrl-2 = <&otp_gpio>;
|
|
#thermal-sensor-cells = <0>;
|
|
rockchip,hw-tshut-temp = <95000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu: gpu@20000000 {
|
|
compatible = "rockchip,rk3228-mali", "arm,mali-400";
|
|
reg = <0x20000000 0x10000>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gp",
|
|
"gpmmu",
|
|
"pp0",
|
|
"ppmmu0",
|
|
"pp1",
|
|
"ppmmu1";
|
|
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
|
clock-names = "core", "bus";
|
|
resets = <&cru SRST_GPU_A>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vpu_mmu: iommu@20020800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x20020800 0x100>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vpu_mmu";
|
|
iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdec_mmu: iommu@20030480 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vdec_mmu";
|
|
iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop_mmu: iommu@20053f00 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x20053f00 0x100>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vop_mmu";
|
|
iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@20070800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x20070800 0x100>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "iep_mmu";
|
|
iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc: dwmmc@30000000 {
|
|
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x30000000 0x4000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
|
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio: dwmmc@30010000 {
|
|
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x30010000 0x4000>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
|
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: dwmmc@30020000 {
|
|
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x30020000 0x4000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <37500000>;
|
|
max-frequency = <37500000>;
|
|
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
|
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
bus-width = <8>;
|
|
default-sample-phase = <158>;
|
|
fifo-depth = <0x100>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
|
resets = <&cru SRST_EMMC>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_otg: usb@30040000 {
|
|
compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
|
|
"snps,dwc2";
|
|
reg = <0x30040000 0x40000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_OTG>;
|
|
clock-names = "otg";
|
|
dr_mode = "otg";
|
|
g-np-tx-fifo-size = <16>;
|
|
g-rx-fifo-size = <280>;
|
|
g-tx-fifo-size = <256 128 128 64 32 16>;
|
|
g-use-dma;
|
|
phys = <&u2phy0_otg>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ehci: usb@30080000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x30080000 0x20000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy0_host>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ohci: usb@300a0000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x300a0000 0x20000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy0_host>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host1_ehci: usb@300c0000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x300c0000 0x20000>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy1_otg>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host1_ohci: usb@300e0000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x300e0000 0x20000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy1_otg>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host2_ehci: usb@30100000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x30100000 0x20000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
|
|
phys = <&u2phy1_host>;
|
|
phy-names = "usb";
|
|
clock-names = "usbhost", "utmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host2_ohci: usb@30120000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x30120000 0x20000>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy1_host>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac: ethernet@30200000 {
|
|
compatible = "rockchip,rk3228-gmac";
|
|
reg = <0x30200000 0x10000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
|
|
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
|
|
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
|
|
<&cru PCLK_GMAC>;
|
|
clock-names = "stmmaceth", "mac_clk_rx",
|
|
"mac_clk_tx", "clk_mac_ref",
|
|
"clk_mac_refout", "aclk_mac",
|
|
"pclk_mac";
|
|
resets = <&cru SRST_GMAC>;
|
|
reset-names = "stmmaceth";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@32010000 {
|
|
compatible = "arm,gic-400";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
|
|
reg = <0x32011000 0x1000>,
|
|
<0x32012000 0x2000>,
|
|
<0x32014000 0x2000>,
|
|
<0x32016000 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3228-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@11110000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11110000 0x100>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@11120000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11120000 0x100>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@11130000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11130000 0x100>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@11140000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11140000 0x100>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
};
|
|
|
|
sdio {
|
|
sdio_clk: sdio-clk {
|
|
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdio_cmd: sdio-cmd {
|
|
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdio_bus4: sdio-bus4 {
|
|
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
|
|
<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
|
|
<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
|
|
<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 27 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 28 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 29 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 30 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 31 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 12 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 25 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 21 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 20 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 11 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 12 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 25 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 8 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 15 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
phy_pins: phy-pins {
|
|
rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 8 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi-0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi-1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_bus: i2s1-bus {
|
|
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 9 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 11 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 12 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 13 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 14 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 2 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 4 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 5 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 27 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 10 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart21_xfer: uart21-xfer {
|
|
rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 9 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_cts: uart2-cts {
|
|
rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_rts: uart2-rts {
|
|
rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|