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When using per channel DMA interrupts the transmit interrupt (TI) and the receive interrupt (RI) are masked off so as to not generate an interrupt to the main ISR. However, should another interrupt fire for the DMA channel that is handled by the main ISR the TI/RI bits can still be set. This will cause the wrong and uninitialized napi structure to be used causing a panic. Add a check to be sure per channel DMA interrupts are not enabled before acting on those bit flags. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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xgbe | ||
7990.c | ||
7990.h | ||
a2065.c | ||
a2065.h | ||
am79c961a.c | ||
am79c961a.h | ||
amd8111e.c | ||
amd8111e.h | ||
ariadne.c | ||
ariadne.h | ||
atarilance.c | ||
au1000_eth.c | ||
au1000_eth.h | ||
declance.c | ||
hplance.c | ||
hplance.h | ||
Kconfig | ||
lance.c | ||
Makefile | ||
mvme147.c | ||
ni65.c | ||
ni65.h | ||
nmclan_cs.c | ||
pcnet32.c | ||
sun3lance.c | ||
sunlance.c |