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e95008a121
If cpu_name_string() is used in non-atomic context when preemption is enabled, it can trigger a BUG such as this one: BUG: using smp_processor_id() in preemptible [00000000] code: unaligned/156 caller is __show_regs+0x1e4/0x330 CPU: 2 PID: 156 Comm: unaligned Tainted: G W 4.3.0-00366-ga3592179816d-dirty #1501 Stack : ffffffff80900000 ffffffff8019bc18 000000000000005f ffffffff80a20000 0000000000000000 0000000000000009 ffffffff8019c0e0 ffffffff80835648 a8000000ff2bdec0 ffffffff80a1e628 000000000000009c 0000000000000002 ffffffff80840000 a8000000fff2ffb0 0000000000000020 ffffffff8020e43c a8000000fff2fcf8 ffffffff80a20000 0000000000000000 ffffffff808f2607 ffffffff8082b138 ffffffff8019cd1c 0000000000000030 ffffffff8082b138 0000000000000002 000000000000009c 0000000000000000 0000000000000000 0000000000000000 a8000000fff2fc40 0000000000000000 ffffffff8044dbf4 0000000000000000 0000000000000000 0000000000000000 ffffffff8010c400 ffffffff80855bb0 ffffffff8010d008 0000000000000000 ffffffff8044dbf4 ... Call Trace: [<ffffffff8010d008>] show_stack+0x90/0xb0 [<ffffffff8044dbf4>] dump_stack+0x84/0xe0 [<ffffffff8046d4ec>] check_preemption_disabled+0x10c/0x110 [<ffffffff8010c40c>] __show_regs+0x1e4/0x330 [<ffffffff8010d060>] show_registers+0x28/0xc0 [<ffffffff80110748>] do_ade+0xcc8/0xce0 [<ffffffff80105b84>] resume_userspace_check+0x0/0x10 This is possible because cpu_name_string() is used by __show_regs(), which is used by both show_regs() and show_registers(). These two functions are used by various exception handling functions, only some of which ensure that interrupts or preemption is disabled. However the following have interrupts explicitly enabled or not explicitly disabled: - do_reserved() (irqs enabled) - do_ade() (irqs not disabled) This can be hit by setting /sys/kernel/debug/mips/unaligned_action to 2, and triggering an address error exception, e.g. an unaligned access or access to kernel segment from user mode. To fix the above cases, use raw_smp_processor_id() instead. It is unusual for CPU names to be different in the same system, and even if they were, its possible the process has migrated between the exception of interest and the cpu_name_string() call anyway. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12212/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
135 lines
3.9 KiB
C
135 lines
3.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_CPU_INFO_H
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#define __ASM_CPU_INFO_H
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#include <linux/types.h>
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#include <asm/cache.h>
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned int waysize; /* Bytes per way */
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unsigned short sets; /* Number of lines per set */
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unsigned char ways; /* Number of ways */
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unsigned char linesz; /* Size of line in bytes */
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unsigned char waybit; /* Bits to select in a cache set */
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unsigned char flags; /* Flags describing cache properties */
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};
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/*
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* Flag definitions
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*/
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#define MIPS_CACHE_NOT_PRESENT 0x00000001
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#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
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#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
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#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
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#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
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#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
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struct cpuinfo_mips {
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unsigned long asid_cache;
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/*
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* Capability and feature descriptor structure for MIPS CPU
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*/
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unsigned long ases;
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unsigned long long options;
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unsigned int udelay_val;
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unsigned int processor_id;
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unsigned int fpu_id;
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unsigned int fpu_csr31;
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unsigned int fpu_msk31;
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unsigned int msa_id;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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int tlbsizevtlb;
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int tlbsizeftlbsets;
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int tlbsizeftlbways;
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int srsets; /* Shadow register sets */
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int package;/* physical package number */
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int core; /* physical core number */
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#ifdef CONFIG_64BIT
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int vmbits; /* Virtual memory size in bits */
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#endif
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#ifdef CONFIG_MIPS_MT_SMP
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/*
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* There is not necessarily a 1:1 mapping of VPE num to CPU number
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* in particular on multi-core systems.
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*/
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int vpe_id; /* Virtual Processor number */
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#endif
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void *data; /* Additional data */
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unsigned int watch_reg_count; /* Number that exist */
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unsigned int watch_reg_use_cnt; /* Usable by ptrace */
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#define NUM_WATCH_REGS 4
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u16 watch_reg_masks[NUM_WATCH_REGS];
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unsigned int kscratch_mask; /* Usable KScratch mask. */
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/*
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* Cache Coherency attribute for write-combine memory writes.
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* (shifted by _CACHE_SHIFT)
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*/
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unsigned int writecombine;
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/*
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* Simple counter to prevent enabling HTW in nested
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* htw_start/htw_stop calls
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*/
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unsigned int htw_seq;
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} __attribute__((aligned(SMP_CACHE_BYTES)));
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extern struct cpuinfo_mips cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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#define boot_cpu_data cpu_data[0]
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extern void cpu_probe(void);
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extern void cpu_report(void);
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extern const char *__cpu_name[];
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#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
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struct seq_file;
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struct notifier_block;
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extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
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extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
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#define proc_cpuinfo_notifier(fn, pri) \
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({ \
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static struct notifier_block fn##_nb = { \
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.notifier_call = fn, \
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.priority = pri \
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}; \
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\
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register_proc_cpuinfo_notifier(&fn##_nb); \
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})
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struct proc_cpuinfo_notifier_args {
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struct seq_file *m;
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unsigned long n;
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};
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#ifdef CONFIG_MIPS_MT_SMP
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# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
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#else
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# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
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#endif
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#endif /* __ASM_CPU_INFO_H */
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