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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8f8f484bf3
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "clk.h"
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static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
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return sync->rate;
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}
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static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
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if (rate > sync->max_rate)
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return -EINVAL;
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else
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return rate;
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}
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static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
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sync->rate = rate;
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return 0;
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}
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const struct clk_ops tegra_clk_sync_source_ops = {
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.round_rate = clk_sync_source_round_rate,
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.set_rate = clk_sync_source_set_rate,
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.recalc_rate = clk_sync_source_recalc_rate,
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};
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struct clk *tegra_clk_register_sync_source(const char *name,
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unsigned long rate, unsigned long max_rate)
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{
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struct tegra_clk_sync_source *sync;
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struct clk_init_data init;
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struct clk *clk;
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sync = kzalloc(sizeof(*sync), GFP_KERNEL);
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if (!sync) {
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pr_err("%s: could not allocate sync source clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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sync->rate = rate;
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sync->max_rate = max_rate;
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init.ops = &tegra_clk_sync_source_ops;
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init.name = name;
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init.flags = CLK_IS_ROOT;
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init.parent_names = NULL;
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init.num_parents = 0;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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sync->hw.init = &init;
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clk = clk_register(NULL, &sync->hw);
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if (IS_ERR(clk))
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kfree(sync);
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return clk;
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}
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