Koji Matsuoka fd1adef3bf drm: rcar-du: Fix H/V sync signal polarity configuration ... The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>		2016-11-15 01:44:50 +02:00
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drm	drm: rcar-du: Fix H/V sync signal polarity configuration	2016-11-15 01:44:50 +02:00
host1x	drm/tegra: dsi: Enhance runtime power management	2016-08-24 15:58:57 +02:00
ipu-v3	gpu: ipu-v3: Add queued image conversion support	2016-09-19 08:30:27 +02:00
vga	vgaarbiter: rst-ifiy and polish kerneldoc	2016-08-16 18:49:56 +02:00
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