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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 16:30:52 +07:00
b4178ab58a
paride_register() returns 1 on success, 0 on failure and module init
code looks like
static int __init foo_init(void)
{
return paride_register(&foo) - 1;
}
which is not what one get used to. Converted to usual 0/-E convention.
In case of kbic driver, unwind registration. It was just
return (paride_register(&k951)||paride_register(&k971))-1;
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
314 lines
7.3 KiB
C
314 lines
7.3 KiB
C
/*
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frpw.c (c) 1996-8 Grant R. Guenther <grant@torque.net>
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Under the terms of the GNU General Public License
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frpw.c is a low-level protocol driver for the Freecom "Power"
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parallel port IDE adapter.
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Some applications of this adapter may require a "printer" reset
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prior to loading the driver. This can be done by loading and
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unloading the "lp" driver, or it can be done by this driver
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if you define FRPW_HARD_RESET. The latter is not recommended
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as it may upset devices on other ports.
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*/
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/* Changes:
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1.01 GRG 1998.05.06 init_proto, release_proto
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fix chip detect
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added EPP-16 and EPP-32
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1.02 GRG 1998.09.23 added hard reset to initialisation process
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1.03 GRG 1998.12.14 made hard reset conditional
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*/
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#define FRPW_VERSION "1.03"
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <asm/io.h>
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#include "paride.h"
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#define cec4 w2(0xc);w2(0xe);w2(0xe);w2(0xc);w2(4);w2(4);w2(4);
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#define j44(l,h) (((l>>4)&0x0f)|(h&0xf0))
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/* cont = 0 - access the IDE register file
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cont = 1 - access the IDE command set
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*/
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static int cont_map[2] = { 0x08, 0x10 };
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static int frpw_read_regr( PIA *pi, int cont, int regr )
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{ int h,l,r;
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r = regr + cont_map[cont];
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w2(4);
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w0(r); cec4;
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w2(6); l = r1();
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w2(4); h = r1();
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w2(4);
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return j44(l,h);
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}
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static void frpw_write_regr( PIA *pi, int cont, int regr, int val)
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{ int r;
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r = regr + cont_map[cont];
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w2(4); w0(r); cec4;
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w0(val);
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w2(5);w2(7);w2(5);w2(4);
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}
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static void frpw_read_block_int( PIA *pi, char * buf, int count, int regr )
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{ int h, l, k, ph;
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switch(pi->mode) {
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case 0: w2(4); w0(regr); cec4;
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for (k=0;k<count;k++) {
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w2(6); l = r1();
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w2(4); h = r1();
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buf[k] = j44(l,h);
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}
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w2(4);
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break;
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case 1: ph = 2;
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w2(4); w0(regr + 0xc0); cec4;
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w0(0xff);
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for (k=0;k<count;k++) {
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w2(0xa4 + ph);
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buf[k] = r0();
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ph = 2 - ph;
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}
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w2(0xac); w2(0xa4); w2(4);
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break;
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case 2: w2(4); w0(regr + 0x80); cec4;
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for (k=0;k<count;k++) buf[k] = r4();
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w2(0xac); w2(0xa4);
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w2(4);
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break;
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case 3: w2(4); w0(regr + 0x80); cec4;
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for (k=0;k<count-2;k++) buf[k] = r4();
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w2(0xac); w2(0xa4);
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buf[count-2] = r4();
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buf[count-1] = r4();
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w2(4);
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break;
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case 4: w2(4); w0(regr + 0x80); cec4;
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for (k=0;k<(count/2)-1;k++) ((u16 *)buf)[k] = r4w();
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w2(0xac); w2(0xa4);
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buf[count-2] = r4();
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buf[count-1] = r4();
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w2(4);
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break;
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case 5: w2(4); w0(regr + 0x80); cec4;
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for (k=0;k<(count/4)-1;k++) ((u32 *)buf)[k] = r4l();
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buf[count-4] = r4();
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buf[count-3] = r4();
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w2(0xac); w2(0xa4);
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buf[count-2] = r4();
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buf[count-1] = r4();
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w2(4);
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break;
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}
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}
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static void frpw_read_block( PIA *pi, char * buf, int count)
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{ frpw_read_block_int(pi,buf,count,0x08);
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}
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static void frpw_write_block( PIA *pi, char * buf, int count )
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{ int k;
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switch(pi->mode) {
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case 0:
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case 1:
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case 2: w2(4); w0(8); cec4; w2(5);
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for (k=0;k<count;k++) {
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w0(buf[k]);
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w2(7);w2(5);
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}
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w2(4);
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break;
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case 3: w2(4); w0(0xc8); cec4; w2(5);
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for (k=0;k<count;k++) w4(buf[k]);
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w2(4);
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break;
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case 4: w2(4); w0(0xc8); cec4; w2(5);
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for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]);
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w2(4);
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break;
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case 5: w2(4); w0(0xc8); cec4; w2(5);
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for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]);
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w2(4);
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break;
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}
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}
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static void frpw_connect ( PIA *pi )
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{ pi->saved_r0 = r0();
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pi->saved_r2 = r2();
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w2(4);
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}
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static void frpw_disconnect ( PIA *pi )
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{ w2(4); w0(0x20); cec4;
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w0(pi->saved_r0);
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w2(pi->saved_r2);
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}
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/* Stub logic to see if PNP string is available - used to distinguish
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between the Xilinx and ASIC implementations of the Freecom adapter.
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*/
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static int frpw_test_pnp ( PIA *pi )
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/* returns chip_type: 0 = Xilinx, 1 = ASIC */
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{ int olddelay, a, b;
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#ifdef FRPW_HARD_RESET
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w0(0); w2(8); udelay(50); w2(0xc); /* parallel bus reset */
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mdelay(1500);
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#endif
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olddelay = pi->delay;
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pi->delay = 10;
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pi->saved_r0 = r0();
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pi->saved_r2 = r2();
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w2(4); w0(4); w2(6); w2(7);
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a = r1() & 0xff; w2(4); b = r1() & 0xff;
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w2(0xc); w2(0xe); w2(4);
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pi->delay = olddelay;
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w0(pi->saved_r0);
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w2(pi->saved_r2);
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return ((~a&0x40) && (b&0x40));
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}
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/* We use the pi->private to remember the result of the PNP test.
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To make this work, private = port*2 + chip. Yes, I know it's
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a hack :-(
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*/
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static int frpw_test_proto( PIA *pi, char * scratch, int verbose )
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{ int j, k, r;
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int e[2] = {0,0};
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if ((pi->private>>1) != pi->port)
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pi->private = frpw_test_pnp(pi) + 2*pi->port;
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if (((pi->private%2) == 0) && (pi->mode > 2)) {
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if (verbose)
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printk("%s: frpw: Xilinx does not support mode %d\n",
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pi->device, pi->mode);
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return 1;
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}
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if (((pi->private%2) == 1) && (pi->mode == 2)) {
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if (verbose)
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printk("%s: frpw: ASIC does not support mode 2\n",
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pi->device);
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return 1;
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}
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frpw_connect(pi);
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for (j=0;j<2;j++) {
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frpw_write_regr(pi,0,6,0xa0+j*0x10);
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for (k=0;k<256;k++) {
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frpw_write_regr(pi,0,2,k^0xaa);
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frpw_write_regr(pi,0,3,k^0x55);
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if (frpw_read_regr(pi,0,2) != (k^0xaa)) e[j]++;
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}
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}
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frpw_disconnect(pi);
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frpw_connect(pi);
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frpw_read_block_int(pi,scratch,512,0x10);
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r = 0;
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for (k=0;k<128;k++) if (scratch[k] != k) r++;
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frpw_disconnect(pi);
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if (verbose) {
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printk("%s: frpw: port 0x%x, chip %ld, mode %d, test=(%d,%d,%d)\n",
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pi->device,pi->port,(pi->private%2),pi->mode,e[0],e[1],r);
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}
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return (r || (e[0] && e[1]));
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}
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static void frpw_log_adapter( PIA *pi, char * scratch, int verbose )
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{ char *mode_string[6] = {"4-bit","8-bit","EPP",
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"EPP-8","EPP-16","EPP-32"};
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printk("%s: frpw %s, Freecom (%s) adapter at 0x%x, ", pi->device,
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FRPW_VERSION,((pi->private%2) == 0)?"Xilinx":"ASIC",pi->port);
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printk("mode %d (%s), delay %d\n",pi->mode,
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mode_string[pi->mode],pi->delay);
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}
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static struct pi_protocol frpw = {
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.owner = THIS_MODULE,
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.name = "frpw",
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.max_mode = 6,
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.epp_first = 2,
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.default_delay = 2,
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.max_units = 1,
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.write_regr = frpw_write_regr,
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.read_regr = frpw_read_regr,
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.write_block = frpw_write_block,
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.read_block = frpw_read_block,
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.connect = frpw_connect,
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.disconnect = frpw_disconnect,
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.test_proto = frpw_test_proto,
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.log_adapter = frpw_log_adapter,
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};
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static int __init frpw_init(void)
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{
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return paride_register(&frpw);
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}
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static void __exit frpw_exit(void)
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{
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paride_unregister(&frpw);
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}
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MODULE_LICENSE("GPL");
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module_init(frpw_init)
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module_exit(frpw_exit)
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