mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 11:58:21 +07:00
1afa9c3b7c
New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants
of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST
+ Reference boards for stm32mp15
- ST Ericsson
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
variants of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner:
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic:
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip:
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST:
+ Reference boards for stm32mp15
- ST Ericsson:
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP:
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm:
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
arm64: dts: ti: k3-am65-main Add CAL node
arm64: dts: ti: k3-j721e-main: Add McASP nodes
arm64: dts: ti: k3-am654-main: Add McASP nodes
arm64: dts: ti: k3-j721e: DMA support
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
arm64: dts: ti: k3-am65: DMA support
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
ARM: dts: aspeed: rainier: Switch PSUs to unknown version
arm64: dts: rockchip: Kill off "simple-panel" compatibles
ARM: dts: rockchip: Kill off "simple-panel" compatibles
arm64: dts: rockchip: rename dwmmc node names to mmc
ARM: dts: rockchip: rename dwmmc node names to mmc
arm64: dts: exynos: Rename Samsung and Exynos to lowercase
arm64: dts: uniphier: add reset-names to NAND controller node
...
509 lines
12 KiB
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509 lines
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#include <dt-bindings/pinctrl/bcm2835.h>
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#include <dt-bindings/clock/bcm2835.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/bcm2835-pm.h>
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/* firmware-provided startup stubs live here, where the secondary CPUs are
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* spinning.
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*/
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/memreserve/ 0x00000000 0x00001000;
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/* This include file covers the common peripherals and configuration between
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* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
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* bcm2835.dtsi and bcm2836.dtsi.
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*/
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/ {
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compatible = "brcm,bcm2835";
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model = "BCM2835";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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rmem: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cma: linux,cma {
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compatible = "shared-dma-pool";
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size = <0x4000000>; /* 64MB */
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reusable;
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linux,cma-default;
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};
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <1000>;
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trips {
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cpu-crit {
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temperature = <90000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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system_timer: timer@7e003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7e003000 0x1000>;
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interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
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/* This could be a reference to BCM2835_CLOCK_TIMER,
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* but we don't have the driver using the common clock
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* support yet.
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*/
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clock-frequency = <1000000>;
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};
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txp: txp@7e004000 {
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compatible = "brcm,bcm2835-txp";
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reg = <0x7e004000 0x20>;
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interrupts = <1 11>;
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};
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clocks: cprman@7e101000 {
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compatible = "brcm,bcm2835-cprman";
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#clock-cells = <1>;
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reg = <0x7e101000 0x2000>;
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/* CPRMAN derives almost everything from the
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* platform's oscillator. However, the DSI
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* pixel clocks come from the DSI analog PHY.
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*/
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clocks = <&clk_osc>,
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<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
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<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
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};
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mailbox: mailbox@7e00b880 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7e00b880 0x40>;
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interrupts = <0 1>;
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#mbox-cells = <0>;
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};
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gpio: gpio@7e200000 {
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compatible = "brcm,bcm2835-gpio";
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reg = <0x7e200000 0xb4>;
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/*
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* The GPIO IP block is designed for 3 banks of GPIOs.
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* Each bank has a GPIO interrupt for itself.
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* There is an overall "any bank" interrupt.
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* In order, these are GIC interrupts 17, 18, 19, 20.
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* Since the BCM2835 only has 2 banks, the 2nd bank
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* interrupt output appears to be mirrored onto the
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* 3rd bank's interrupt signal.
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* So, a bank0 interrupt shows up on 17, 20, and
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* a bank1 interrupt shows up on 18, 19, 20!
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*/
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interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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/* Defines common pin muxing groups
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*
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* While each pin can have its mux selected
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* for various functions individually, some
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* groups only make sense to switch to a
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* particular function together.
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*/
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dpi_gpio0: dpi_gpio0 {
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brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
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12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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emmc_gpio22: emmc_gpio22 {
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brcm,pins = <22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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emmc_gpio34: emmc_gpio34 {
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brcm,pins = <34 35 36 37 38 39>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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brcm,pull = <BCM2835_PUD_OFF
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP>;
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};
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emmc_gpio48: emmc_gpio48 {
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brcm,pins = <48 49 50 51 52 53>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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gpclk0_gpio4: gpclk0_gpio4 {
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brcm,pins = <4>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio5: gpclk1_gpio5 {
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brcm,pins = <5>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio42: gpclk1_gpio42 {
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brcm,pins = <42>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio44: gpclk1_gpio44 {
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brcm,pins = <44>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk2_gpio6: gpclk2_gpio6 {
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brcm,pins = <6>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk2_gpio43: gpclk2_gpio43 {
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brcm,pins = <43>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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brcm,pull = <BCM2835_PUD_OFF>;
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};
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i2c0_gpio0: i2c0_gpio0 {
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brcm,pins = <0 1>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c0_gpio28: i2c0_gpio28 {
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brcm,pins = <28 29>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c0_gpio44: i2c0_gpio44 {
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brcm,pins = <44 45>;
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brcm,function = <BCM2835_FSEL_ALT1>;
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};
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i2c1_gpio2: i2c1_gpio2 {
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brcm,pins = <2 3>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c1_gpio44: i2c1_gpio44 {
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brcm,pins = <44 45>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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jtag_gpio22: jtag_gpio22 {
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brcm,pins = <22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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pcm_gpio18: pcm_gpio18 {
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brcm,pins = <18 19 20 21>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pcm_gpio28: pcm_gpio28 {
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brcm,pins = <28 29 30 31>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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sdhost_gpio48: sdhost_gpio48 {
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brcm,pins = <48 49 50 51 52 53>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi0_gpio7: spi0_gpio7 {
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brcm,pins = <7 8 9 10 11>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi0_gpio35: spi0_gpio35 {
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brcm,pins = <35 36 37 38 39>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi1_gpio16: spi1_gpio16 {
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brcm,pins = <16 17 18 19 20 21>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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spi2_gpio40: spi2_gpio40 {
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brcm,pins = <40 41 42 43 44 45>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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uart0_gpio14: uart0_gpio14 {
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brcm,pins = <14 15>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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/* Separate from the uart0_gpio14 group
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* because it conflicts with spi1_gpio16, and
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* people often run uart0 on the two pins
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* without flow control.
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*/
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uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
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brcm,pins = <16 17>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
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brcm,pins = <30 31>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
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};
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uart0_gpio32: uart0_gpio32 {
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brcm,pins = <32 33>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
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};
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uart0_gpio36: uart0_gpio36 {
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brcm,pins = <36 37>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
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brcm,pins = <38 39>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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uart1_gpio14: uart1_gpio14 {
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brcm,pins = <14 15>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
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brcm,pins = <16 17>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_gpio32: uart1_gpio32 {
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brcm,pins = <32 33>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
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brcm,pins = <30 31>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_gpio40: uart1_gpio40 {
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brcm,pins = <40 41>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
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brcm,pins = <42 43>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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};
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uart0: serial@7e201000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7e201000 0x200>;
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interrupts = <2 25>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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};
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sdhost: mmc@7e202000 {
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compatible = "brcm,bcm2835-sdhost";
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reg = <0x7e202000 0x100>;
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interrupts = <2 24>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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status = "disabled";
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};
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i2s: i2s@7e203000 {
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compatible = "brcm,bcm2835-i2s";
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reg = <0x7e203000 0x24>;
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clocks = <&clocks BCM2835_CLOCK_PCM>;
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status = "disabled";
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};
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spi: spi@7e204000 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204000 0x200>;
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interrupts = <2 22>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@7e205000 {
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compatible = "brcm,bcm2835-i2c";
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reg = <0x7e205000 0x200>;
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interrupts = <2 21>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpi: dpi@7e208000 {
|
|
compatible = "brcm,bcm2835-dpi";
|
|
reg = <0x7e208000 0x8c>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>,
|
|
<&clocks BCM2835_CLOCK_DPI>;
|
|
clock-names = "core", "pixel";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi0: dsi@7e209000 {
|
|
compatible = "brcm,bcm2835-dsi0";
|
|
reg = <0x7e209000 0x78>;
|
|
interrupts = <2 4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&clocks BCM2835_PLLA_DSI0>,
|
|
<&clocks BCM2835_CLOCK_DSI0E>,
|
|
<&clocks BCM2835_CLOCK_DSI0P>;
|
|
clock-names = "phy", "escape", "pixel";
|
|
|
|
clock-output-names = "dsi0_byte",
|
|
"dsi0_ddr2",
|
|
"dsi0_ddr";
|
|
|
|
};
|
|
|
|
aux: aux@7e215000 {
|
|
compatible = "brcm,bcm2835-aux";
|
|
#clock-cells = <1>;
|
|
reg = <0x7e215000 0x8>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
};
|
|
|
|
uart1: serial@7e215040 {
|
|
compatible = "brcm,bcm2835-aux-uart";
|
|
reg = <0x7e215040 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@7e215080 {
|
|
compatible = "brcm,bcm2835-aux-spi";
|
|
reg = <0x7e215080 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@7e2150c0 {
|
|
compatible = "brcm,bcm2835-aux-spi";
|
|
reg = <0x7e2150c0 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@7e20c000 {
|
|
compatible = "brcm,bcm2835-pwm";
|
|
reg = <0x7e20c000 0x28>;
|
|
clocks = <&clocks BCM2835_CLOCK_PWM>;
|
|
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
|
|
assigned-clock-rates = <10000000>;
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: sdhci@7e300000 {
|
|
compatible = "brcm,bcm2835-sdhci";
|
|
reg = <0x7e300000 0x100>;
|
|
interrupts = <2 30>;
|
|
clocks = <&clocks BCM2835_CLOCK_EMMC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hvs@7e400000 {
|
|
compatible = "brcm,bcm2835-hvs";
|
|
reg = <0x7e400000 0x6000>;
|
|
interrupts = <2 1>;
|
|
};
|
|
|
|
dsi1: dsi@7e700000 {
|
|
compatible = "brcm,bcm2835-dsi1";
|
|
reg = <0x7e700000 0x8c>;
|
|
interrupts = <2 12>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&clocks BCM2835_PLLD_DSI1>,
|
|
<&clocks BCM2835_CLOCK_DSI1E>,
|
|
<&clocks BCM2835_CLOCK_DSI1P>;
|
|
clock-names = "phy", "escape", "pixel";
|
|
|
|
clock-output-names = "dsi1_byte",
|
|
"dsi1_ddr2",
|
|
"dsi1_ddr";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@7e804000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e804000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vec: vec@7e806000 {
|
|
compatible = "brcm,bcm2835-vec";
|
|
reg = <0x7e806000 0x1000>;
|
|
clocks = <&clocks BCM2835_CLOCK_VEC>;
|
|
interrupts = <2 27>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb: usb@7e980000 {
|
|
compatible = "brcm,bcm2835-usb";
|
|
reg = <0x7e980000 0x10000>;
|
|
interrupts = <1 9>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk_usb>;
|
|
clock-names = "otg";
|
|
phys = <&usbphy>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
/* The oscillator is the root of the clock tree. */
|
|
clk_osc: clk-osc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "osc";
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
clk_usb: clk-usb {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "otg";
|
|
clock-frequency = <480000000>;
|
|
};
|
|
};
|
|
|
|
usbphy: phy {
|
|
compatible = "usb-nop-xceiv";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|